JPS6230494B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device having multilayer wiring.

First, in FIG. 1, a method for manufacturing an N-channel Si gate MOS semiconductor device will be described as a representative example of a conventional method for manufacturing a semiconductor device having multilayer wiring, and the problems thereof will be pointed out.

A thickness of approximately 1 is selectively applied to a P-type single crystal silicon substrate 1.
Field oxide films 2a and 2b with a thickness of μm are formed, and a gate oxide film 3 with a thickness of about 1000 Å is further formed. Next, on the surfaces of the gate oxide film 3 and field oxide films 2a and 2b, a gate electrode 4 made of polycrystalline silicon with a thickness of approximately 0.5 μm is formed using a known vapor phase growth technique and a photoetching technique. Form. Next, source/drain regions 6 and 7 having N-type conductivity are formed in the area where the surface not covered by the gate electrode 4 is etched away by a known diffusion technique or ion implantation technique, and further, the interlayer dielectric breakdown voltage is increased. In order to increase the height of
c, 8d (Fig. 1A). Next, a phosphorus glass layer 9 of about 1 μm is grown by a known vapor phase growth method, and in order to make the surface smooth, for example, N ₂
Heat treatment in an atmosphere. The phosphorus glass layer 9 can also be formed by diffusion of phosphorus (FIG. 1B). This flat phosphorus glass layer allows wiring to be made by crossing over the gate electrode 4 and the polycrystalline silicon wiring layer 5.
Disconnection of the wiring layer can be prevented. Next, by a known photoetching technique, a phosphor glass layer 9,
Oxide films 8a, 8b, 8c, and 8d are selectively removed, and first contact holes 10, 11, and 12 are opened (FIG. 1C). Next, in order to reduce the step difference in the phosphor glass layer 9 at the first contact holes 10, 11, and 12, heat treatment is performed again. Furthermore, a silicon oxide film 13 of approximately 0.5 μm is grown by a known vapor phase growth method (FIG. 1O). Next, the vapor-grown oxide film 13 is selectively removed again using a known photo-etching technique, and second contact holes 14, 15, 16 are formed in the same locations as the first contact holes 10, 11, 12. Open a hole (Fig. 1E). Next, about 1 μm of Al is vapor-deposited, and selectively Al
Wiring layers 17, 18, and 19 are formed into a wiring layer to form an N channel.
A Si gate MOS semiconductor device is completed (Fig. 1F). As described above, in FIG. 1, the first contact holes 10, 11, 12, the second contact hole 14,
15 and 16 are shown to match graphically,
However, in reality, as shown in FIG. 2, there is a mask misalignment between the mask A of the first contact hole and the second contact hole B, and when the second contact hole is opened, that is, When the vapor-phase grown oxide film 13 is etched, the phosphorus glass layer 9 under the vapor-phase growth oxide film 13 is largely overetched using, for example, a hydrofluoric acid-based etching solution, and the phosphorus glass is gouged out. If the Al wiring layer 18 passes through it, the probability of disconnection increases. As described above, according to the conventional manufacturing method, a decrease in yield was unavoidable considering the capabilities of current photoetching technology. In addition, if the vapor-phase grown oxide film 13 prevents the phosphorus glass layer 9 and the Al wiring layer 18 from coming into direct contact with each other, and the vapor-phase grown oxide film 13 has few defects, it will have some effect on water resistance, but in reality, The vapor-phase grown oxide film 13 has many defects, and as a result, has insufficient water resistance, has a low dielectric strength voltage, and has many problems with reliability.

An object of the present invention is to provide a method for manufacturing a semiconductor device having an interlayer insulating film with very few disconnections at the contact hole portion of the A1 wiring layer, excellent water resistance, and excellent dielectric strength.

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a surface of a semiconductor substrate, and a step of selectively etching the first insulating film to expose a partial region of the semiconductor substrate. a step of forming a second insulating film made of a silicon nitride film on the region exposed by the first contact hole;
forming a third insulating film made of a silicon oxide film on the second insulating film by vapor phase growth;
A step of selectively etching the third insulating film to form a second contact hole that exposes at least a portion of the second insulating film that is in direct contact with the region; and diffusing impurities over the entire surface. and converting the surfaces of the second insulating film and the third insulating film exposed by the second contact hole into phosphor glass layers, and removing the glass layer to expose a part of the region. and a step of forming a wiring layer made of metal on the exposed region. Here, since the entire thickness of the silicon nitride film must be converted into a phosphorus glass layer, the film thickness cannot be increased very much, for example, from 500 to 600 Å. On the other hand, the interlayer insulating film requires a certain film thickness, for example, in order to reduce the capacitance between upper and lower wiring layers. For this purpose, a silicon oxide film is provided on the silicon nitride film. Alternatively, after the silicon nitride film is deposited on the entire surface, only the area near the contact portion may be left and the rest may be removed by a PR process. However, if you do it like this, PR
Additional processes are required. There is no problem in leaving it behind, and the probability of pinholes occurring in the composite film is smaller, and selectively removing it as described above increases the number of steps, so in the examples described later, , the silicon nitride film is left as it is on the first insulating film other than the contact portion and the vicinity thereof.

An embodiment of the present invention will be described below with reference to FIGS. 3A to 3G.

Here, since the steps from FIG. 3A to FIG. 3-C are the same as the conventional process, their explanation will be omitted.

After opening the first contact holes 10, 11, and 12, a silicon nitride film 1 of about 500 Å is formed by a known vapor phase growth method, for example, after heat treatment in an _N2 atmosphere.
After forming 20, a silicon oxide film 113 of about 0.5 μm is formed thereon (FIG. 3O). Next, as in the prior art, second contact holes 114, 115, 116 are formed using a known photoetching technique.
Drill a hole. At this time, the silicon nitride film 120 under the vapor grown oxide film 113 acts as an etching stopper, and even if the first contact holes 10, 1
1, 12 and second contact holes 114, 11
Even if there is a mask shift of 5,116, the phosphor glass layer 9 is not etched (FIG. 3E). Next, by diffusing phosphorus over the entire surface, a vapor-phase grown oxide film 1 is formed.
13 and the second contact hole 114,1
The silicon nitride film below 15 and 116 is replaced with a second phosphorous glass layer 121 (FIG. 3F). This phosphorus diffusion has the effect of making the vapor grown oxide film 113 denser and the second contact holes 114, 115, 11
At the same time, it has the effect of alleviating the step difference in the vapor-phase grown oxide film 113 in step 6. Next, the second phosphor glass layer 121 is removed using, for example, a hydrofluoric acid-based etching solution, and then approximately 1 μm of Al is deposited, selectively forming the Al wiring layer 121.
17, 118, and 119 are formed to complete an N-channel Si gate MOS semiconductor device. (Figure 3G).

According to the present invention, as shown in FIG. 4, even if there is a mask misalignment between the mask C of the first contact hole and the mask O of the second contact hole, etching is stopped at the silicon nitride film 120, so the phosphor glass layer 9
There is no gouging and etching, and the level difference in the vapor-grown oxide film 113 at the second contact hole is alleviated by phosphorus diffusion, so the contact hole part is gentle. Al wiring layer 118 passing through
There is no disconnection. Further, on the phosphorus glass layer 9, there are two layers, a silicon nitride film 120 and a vapor-grown oxide film 113 which has become dense due to phosphorus diffusion, and has a sufficient effect on water resistance. Regarding the withstand voltage of the interlayer insulating film, the silicon nitride film 120
The withstand voltage is higher than before. As explained above, according to the manufacturing method of the present invention, yield and reliability can be greatly improved compared to conventional manufacturing methods. Note that in the present invention, as in the embodiment, N
Needless to say, the present invention is not limited to the method of manufacturing a channel Si gate MOS semiconductor device, but can be applied to a method of manufacturing a semiconductor device having a multilayer wiring structure having an impurity region of N-type conductivity.

[Brief explanation of the drawing]

1A to 1F are process cross-sectional views of a conventional semiconductor device manufacturing method, FIG. 2 is an enlarged view of a contact hole portion of a semiconductor device manufactured by the conventional manufacturing method, and FIGS. 3A to 3G are FIG. 4 is a cross-sectional view showing the manufacturing method according to an embodiment of the present invention in the order of steps, and FIG. 4 is an enlarged view of a contact hole portion of a semiconductor device manufactured by the manufacturing method of the present invention. 1: Semiconductor substrate, 2a, 2b: Field oxide film, 3: Gate insulating film.

Claims (1)

[Claims] 1. A step of forming a first insulating film on the surface of the semiconductor substrate; and a step of selectively etching the first insulating film to form a first contact hole exposing a partial region of the semiconductor substrate. , a step of forming a second insulating film made of a silicon nitride film on the entire surface, a step of forming a third insulating film made of a silicon oxide film on the second insulating film, and a step of forming the third insulating film. forming a second contact hole that exposes at least a portion of the second insulating film by selectively etching the second insulating film exposed by the second contact hole; The method includes the steps of: changing the surface of the film into a glass layer; removing the glass layer to expose a part of the region; and forming a wiring layer on the exposed region. A method for manufacturing a semiconductor device.