JPS58147046A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent melting away of phosphorus due to absorbed humidity and enhance reliability of semiconductor device by surrounding an insulating film with other insulating film such as Si3N4 at the time of providing an interlayer insulating film containing high concentration phosphorus to an IC, LSI, and the like. CONSTITUTION:A thick field SiO2 film 15 is formed with an inversion preventing P<+> type region 16 used as a base layer at the periphery of a P type Si substrate 11 and a gate SiO2 film 17 is deposited on the active region of a MOS transistor surrounded thereby. Then, a gate electrode 18 consisting of a polycrystalline Si is formed at the center of film 17, the SiO2 film 19 and Si3N4 film 21 are deposited thereon and an N type source, drain region 20 are formed by diffusion within the substrate 11 in both sides thereof with such films used as the mask. Thereafter, the region 20 is covered with the Si3N4 film 21, a SiO2 film 22 is provided between the region 20 and electrode 18, and interlayer insulating films 23, 24 of PSG containing a large amount of phosphorus are formed using said film as the base layer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a conductor device which is improved so as to extend over an interlayer insulating film in the contact area and to improve the value of the conductor.

High reliability is becoming more and more required for highly integrated IC and LSI conductor devices. In such a semiconductor device, a layer 5ai2I edge film is formed on a semiconductor substrate having an element region.
Phosph.

5ilicate Glass! An insulator whose main component is iF phosphor sintered glass) is used, and the concentration PSG film or the like is reflowed to smooth the element surface. This is also intended to prevent disconnection of the wiring layer due to unevenness at the underlying stepped portion of the wiring metal layer.

However, such an interlayer insulating film is made of PSGM containing a high concentration of phosphorus, so when this PSG film absorbs moisture, the phosphorus dissolves out under high temperature and high humidity conditions.
Corrosion occurs in the upper wiring metal layer, for example, the aluminum wiring layer, which may lead to disconnection accidents.

In addition, when moisture is absorbed, polarization occurs in the PSG film part, and for example
Also consider the case where the parasitic field Mo5t- becomes unstable*elementary. Furthermore, as an example, as a semiconductor device, C.
- When configuring a MOS, when performing a PSG film bonding flow to be used as an interlayer insulating film in this manufacturing process, the PSG film is applied to the P region of the source/drain region of the P channel Mos transistor at the contact hole portion.
There are also openings in which phosphorus is diffused from the membrane and the properties of MOS (MOS) Rangemetal are impaired.

This invention is based on the above-mentioned points, and the layer FKL is made of an insulating material containing high concentration of phosphorus.
Even in the case of forming a third layer, it is possible to prevent accidents such as those caused by phosphorus dissolving and dissolving when wet, and also to prevent phosphorus from being diffused. It is an object of the present invention to provide a semiconductor device for IC and LSI applications that can reliably obtain high 411@ characteristics.

That is, the semiconductor device according to the present invention has an interlayer I! containing a high concentration of phosphorus or the like. The l-rim film may be made of, for example, silicon nitride. A semiconductor according to an embodiment of the present invention will be described with reference to the drawings. 7.
I will explain it to Seth. First, as a semiconductor substrate
As shown in 10, Plil~10Ω・csC1o o
) A single crystal silicon substrate 11 having a crystal plane is used, and a 209 to 100 OAC) thermal oxide film 12 is formed on -11 of this substrate 11, and a silicon nitride (81s I4) film is further formed on this thermally oxidized film 1z. Then, as shown in FIG. 2, the silicon nitride waist 1st is
As a means for partially removing the OII silicon film 130, a mask of 7 photoresist is formed on the silicon film 11, and the film is masked with the photoresist by plasma etching using CF4-Os gas. Remove the silicon nitride film in the h portion and
The state is as shown in Fig. 42.

As shown in 1E21gl, the patterned and warped silicon nitride film 1s acts as a electrification-resistant mask against the thermal oxidation of the silicone 1 board 110, and using this oxidation-resistant mask, - As shown in FIG. 3, a field region 15 is formed in a portion excluding the active region 14 by selective oxidation. After forming this field region 1j, silicon nitride 5 is formed as shown in FIG. When the film 11 and the thermal oxide film 11 are removed, the field region 15 is sufficiently oxidized at Q, 7 to 1.2 μS degrees. Silicon base 1 using resist as master
1x1 (Potato is implanted in the Q part outside the DWi area 14JjA using ion implantation droplets, parasitic field MOB) KPII channel stopper 1 for transistor OIL spinning
The field region of the silicon substrate 11 of the zero order forming σ] j″e type 1iL, that is, the active region 14s, is heated as gate pus by thermal oxidation.
oO~l0GOX
The active region 14 is formed as shown in s15 in this way.
After forming the silicon diilide film 11, the entire area of the silicon substrate JJO including the field region III is coated with a polycrystalline film 11 doped with phosphorus or arsenic at a high concentration, or with a high melting point. The metals tungsten (W) and molybdenum (M
・) or O silinide etc. over the entire surface at 0.3
For convenience of explanation, polycrystalline silicon is used as a representative in this example. - Yes 0 Next, as mentioned above, the entire surface of the polycrystalline silicon 110M08) gate part or wiring
The portions that will become plI are successively masked with a 7-photoresist, and residual polycrystalline silicon IIIt is etched as shown in the iris 5aiq.O by plasma etching using, for example, '/dCF4◆O1-based gas. Then, after forming the silicon dioxide film 1# of polycrystalline silicon with the O pattern formed thereon, a phosphor layer is applied to the active region 14 except for the patterned portion of the polycrystalline silicon 1- by ion implantation. In this case, in the above example, the source and drain regions 2# are formed by implanting ions or arsenic.
In the region 01111 where the drain is to be formed, 500 P
It has been explained that ion implantation is performed with the silicon dioxide film 11 formed by -1000 μm O gate oxidation remaining, but this is because the ion implantation is performed in the region where the source and drain are to be formed.
Of course, it is possible to do this with the 119th surface of the ts board exposed.In addition, it can also be done without forming the patterned polycrystalline silicon xxO@WAK silicon dioxide film III'. Next, a silicon nitride film is deposited on the metal surface of the silicon substrate 11 shaped as described above.
00 to 1,000 µm, and plasma etching using a mask made of 7 photoresist in the same manner as described above, as shown in Figure 6, for example, the portions that will become the source and drain, and the portions that will become the gate, corresponding to polycrystalline silicon 18NK. Then, a patterned electrified silicon film 21 is formed.

After forming the Kll-containing film z1 in this way, S
Polycrystalline silicon 18 and source and drain placed 2 in steam at a temperature of OO~1000°C at a relatively low temperature.
Oxidize 0 etc. to 2000 to 500 as shown in Figure 7.
A selective oxide film region x1 having a relatively thick thickness is formed.

Then, 8 to 12 coulomb-versen) I! A CVD 810m film containing phosphorus (hereinafter referred to as PSG film) is formed on the eclipse surface using l1O thick stone, and this PEG film forms an interlayer insulator tszx. Then, a series of contact holes 24 extending to the selective oxide film region 22 are formed in the contact region corresponding to the silicon nitride film jJK using an HF aqueous etching solution.

After forming the interlayer insulating film 2s having the third contact hole z4 in this way, it was heated in nitrogen or steam.
Heat II & ring is performed at around 000υ, and the interlayer insulating film 22
By paper-forming the PSG film (so-called PEG reflow), the acute angle part of the first contact hole 24 in particular is made gentler. Then, as shown in figure s8, for example, a silicon nitride film or a silicon dioxide film, Furthermore, 2
~7% by weight) Low concentration containing phosphorus of Il&*P15
A G film or the like is deposited over the entire surface to form an insulating film z6.

In this embodiment, a case will be explained in which the insulating film z5 is formed by depositing a special KviIi compound □Silin j[.

In other words, as shown in O above, there is Jl on the eating surface! When it comes to the state where the ferrite JJ is formed, as is clear from the figure, the electrified silicon film 11 is formed corresponding to the contact hole 24 part of the cylindrical part 1.
Then, the embrittlement silicone forming the insulating film 25 is removed, and the interlayer insulator Hzx is surrounded by the two layers 11.

1I9 is an enlarged view of the contact hole 24 part in GSTM for *@0flit), and the silicon nitride film 21 is with KI
The IA edge film 25 is removed using an etching solution. That is, the silicon nitride film 11 [11 and the insulating film z5 are etched using the resist as a mask until the surfaces of the silicon dioxide 111r and 1e are etched corresponding to the contact hole IIK, and then the silicon dioxide film 11 is etched. 17.1 g is etched using, for example, a hydrofluoric acid-based etching solution so that the surfaces of the substrate 11 and the polycrystalline silicon 180 are exposed. Therefore, the interlayer insulator II is formed by the selective oxide film z2 and the insulating film Xi, and the contact hole xi@yc
becomes a hailstorm.

In the above example, the silicon diironide group 11.19 was formed, but this may also be done without forming it.

Then, as shown in Figure J110, an aluminum layer containing approximately 1% silicon is deposited by sputtering deposition method to form wiring metal layer 7F, and so-called plasma nitride is deposited on the entire surface of the metal layer by plasma deposition method. This is to form layer 2B (gM silicone film).

That is, according to the conductor device configured as described above, the PSA film used as the interlayer insulation 821 is covered over the surface metal body of the substrate 11 by the insulating film 26 made of silicon nitride and the selective oxide film z2. As a result, accidents such as phosphorus being dissolved under high-temperature conditions and corroding the lining metal layer z1 can be reliably prevented. In addition, since there is a selectively modified film xx-pQ made of II#-21L silicon under this interlayer insulation J[25, the interlayer insulation film 2
10P8G Reflow Implicitly, there will be no shadow on the substrate JJK, and even if high-vertical PEG material is not used or reflow is performed in steam, there will be no shadow on the semiconductor substrate 11 as described above. Nourishment is prevented by stones. As a result, it is possible to lower the temperature of the sauce,
The redistribution of the diffusion layer as a drain is suppressed, making it possible to achieve non-IK performance in shortening channels and promoting miniaturization, making it possible to create semiconductor devices with high Illability and high integration. Incidentally, although the above embodiments have been discussed in correspondence with N-MOB IC and IJI, the present invention is not limited to this, and is applicable to P-MOB IC and IJI.
, C-MOB, bipolar IC, etc., of course. In addition, in this embodiment, an insulating material made of silicon nitride, a selective oxide film, and an envelope i!
Although the PSG film as a 1% 1I5I8IIR film is shown as a single layer, it may have a multilayer structure.

As described above, according to the present invention, the arrangement 1llI! There is a contact hole IIK where the metal layer connects with the semiconductor device,
The layer of PSG film containing 5 ave of phosphorus is wrapped around the layer, and phosphorus does not dissolve at high temperatures and high humidity.

Therefore, not only the top surface but also the contact hole area
〇 Accidents such as corrosion and wire breakage can be prevented from occurring, and reliability can be improved.

[Brief explanation of drawings]

111 to '1IIilO are cross-sectional diagrams for explaining a semiconductor device according to an embodiment of the present invention based on its manufacturing process. 11... Semiconductor substrate, 14... Element value range, 16...
・Field region, 17.19...Silicon dioxide film, 18...Polycrystalline silicon, 20...Source, drain region, jl...Silicon nitride film, 22...Selective oxidation MI#I region, 23... Interlayer insulator film (P8GI [
) '26...Insulating film, 21... Wiring metal layer. Patent attorney representing applicant Takehiko Suzue Figure 1 Figure 3 Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] Selective oxidation I formed on a semiconductor substrate having an element region
II! A contact region connected to the selective oxide film region 1IiI, and a contact region formed on the selective oxide film region.
an interlayer insulating film mainly composed of phosphorus gas, and an insulating film formed on at least the upper surface of the interlayer insulating film and the selective oxide film region at the chest circumference of the contact region, Semiconductor-0 whose insulating film is surrounded by a selective oxide film and an insulating film is 41 mold.