JPH02231719A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the coverage for a contact hole for a wiring by forming a silicon oxide film on the entire surface of a plate including a hole part, and performing etching so that the silicon oxide film remains on the side wall of the hole part. CONSTITUTION:After an element region is formed on a substrate 4, a silicon oxide film is formed by CVD, sputtering, plasma or the like, and an interlayer insulating film 5 is provided. A contact hole 6 reaching the element region is formed at a desired place. A silicon oxide film 7 is formed on the entire surface of the substrate including the contact hole 6. When the silicon oxide film 7 undergoes anisotropic etching, the silicon oxide film 7 remains on the side wall of the contact hole 6. The contact hole becomes the tapered shape. Therefore, the shape of the contact hole which is equivalent to the shape when heat treatment is performed can be obtained. Thus, the change in gate length of a transistor and diffusion of impurities from the interlayer insulating film into source and drain regions can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and particularly to a method for manufacturing a semiconductor integrated circuit including a method for forming contact holes. [Prior art] In the manufacturing process of semiconductor integrated circuits, there are
The method for forming the contact hole formed in the interlayer insulating film, which connects the formed semiconductor element and the wiring for connecting this semiconductor element as an electronic circuit, is to reduce the contact resistance, reduce the area, and remove the metal wiring above. Conventionally, various forming methods have been used in consideration of coverage and the like.

A method of forming a contact hole according to the prior art will be explained with reference to the drawings.

FIGS. 2(a) to 3(c) and 3 are cross-sectional views of a semiconductor chip, briefly illustrating a method for forming contact holes using a conventional manufacturing method. First, Figure 2(a)
A semiconductor element is provided on a substrate as shown in FIG. (In this figure, it is a MOS} transistor.) Next, apply a CV on this element.
A silicon-based oxide film is formed by D, sputtering, plasma, etc. to form the interlayer insulating film 5. Next, as shown in FIG. 2(c), a hole 6 is opened at a desired location in order to arrange the semiconductor element in the lower layer as an electronic circuit. In this figure, for the sake of simplicity, contact holes are formed only on the source and drain regions, but of course they may be formed on the gate electrodes. Next, as shown in FIG. 3, after the contact hole 6 is opened, a heat treatment is applied to form the end portion of the contact hole. This heat treatment is necessary to improve the coverage of the next wiring film to the contact hole, and is usually performed at a high temperature of about 900°C to 1000°C.
It is normal to do this for a few minutes. If this process is not performed, the coverage to the contact hole will be poor.
This can cause wire breakage or cause the wiring in the contact hole stage to warp, reducing the life of the wiring.

[Problem to be solved by the invention]

In the conventional contact hole formation method described above, after the contact hole is opened, donor-acceptor impurities in the source and drain regions are absorbed into the substrate due to heat treatment at 900°C to 1000°C to make the contact hole stage sloppy. , diffusion, and the effective gate length of the transistor is shortened, and at the time of design, it is necessary to take into account the reduction in the effective gate length due to this heat treatment, which hinders the miniaturization of semiconductor integrated circuits. In addition, due to the heat treatment at 900°C to 1000°C, impurities contained in the interlayer insulating film, such as phosphorus and poron, diffuse into the source and drain regions, resulting in contact resistance between the wiring in the contact hole and the source and drain regions. This had the disadvantage of causing problems such as an increase in

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that can form a contact hole with improved coverage of wiring to the contact hole without heat treatment.

[Means to solve the problem]

A method for manufacturing a semiconductor integrated circuit according to the present invention includes a step of forming an insulating film on a semiconductor substrate on which an element region is formed, a step of forming a contact opening reaching the element region,
The method includes a step of forming a silicon oxide film on the surface of the substrate including the opening, and a step of etching so that the silicon oxide film remains on the sidewall of the opening.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention. First of all
As shown in Figure (a), element regions such as gate electrodes and source/drain regions are formed on the substrate 4. In this embodiment, an example of a MOS transistor is given, but the device region is not limited to this in the present invention. Next, as shown in FIG. 1(b), a silicon oxide film is formed by CVD, sputtering, plasma, etc. to form an interlayer insulating film 5. Next, as shown in FIG. 1(c), a contact hole 6 reaching the element region is formed at a desired location. Next, Figure 1 (
As shown in d), a silicon oxide film 7 is formed on the gold surface of the substrate including the contact hole 6.

Next, as shown in FIG. 1(e), the silicon oxide film 7 is anisotropically etched to leave the silicon oxide film 7 on the side wall of the contact hole 6, making the contact hole tapered. According to this example, the contact hole becomes tapered without making the end of the contact hole sloppy due to heat treatment, and it is possible to improve the coverage of the contact hole with the wiring formed in the next step.

〔Effect of the invention〕

The method for forming a contact hole according to the present invention does not require the conventional heat treatment at 900 to 1000° C. for sloping the contact hole stage after the contact hole is opened, and can produce contact holes equivalent to those obtained by heat treatment. Since the shape can be obtained, there is an effect that problems such as changes in the gate length of the transistor and diffusion of impurities from the interlayer insulating film into the source and drain regions do not occur.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIGS. 2(a) to (c) and FIG. 3 are conventional examples. FIG. 3 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the process. 1...Gate electrode, 2...Source/drain region, 3...Field oxide film, 4...
...Substrate, 5...Interlayer insulating film, 6...
...Contact hole, 7...Silicon oxide film. Agent Patent Attorney Susumu Uchihara Figure Z

Claims (1)

[Claims] A step of forming an insulating film on a semiconductor substrate on which an element region is formed, a step of forming a contact opening reaching the element region, and a step of forming a silicon oxide film on a sheet metal surface including the opening. and a step of etching the silicon oxide film so as to remain on the side wall of the opening.