JPS6230364A - Manufacture of mis semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the cost by removing a gate insulating film to expose a peripheral region, and forming an electrode ohmically connected with the exposed portion of the peripheral region. CONSTITUTION:A silicon film 2, a P<+> type layer 3 formed under the film 2, a gate oxide silicon film 4 and a polycrystalline silicon film 5 are formed on a silicon wafer 1. Polycrystalline silicon films 5a, 5b for gate electrode are formed, N<+> type layers 6, 7 for a source are formed, an impurity is diffused in the films 5a, 5b to form low resistances. After a PSG film 9 is formed on the entire surface, a contacting window is formed to form a drain electrode D, a source electrode S and a pad electrode C, a surface protective film 10 is then formed, selectively removed to expose the electrodes. A high density boron impurity 11 is ion implanted to a scribing region, an N<+> type layer 8 is inverted as a P<+> type layer 11a to reduce the resistance of the film 5b. Thus, a cost can be largely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION In a conventional MIS semiconductor device, for example, an N-channel silicon gate type MOSLSI, the substrate bias VB
The B terminal is taken out from the back side of the semiconductor substrate (pellet). Therefore, in mounting this type of MOSLSI, it is necessary to provide conductor wiring for substrate bias terminals in a ceramic cage, for example, a ceramic cage, which increases the cost of the van cage.

For this reason, in conventional MOSLSIs, attempts have been made to provide substrate bias terminals on the top surface of the substrate, as in bipolar semiconductor devices, but in order to manufacture them, it is necessary to add a photoetching process to the normal manufacturing process. Therefore, the cost of the work and the masks used for it are rather high, and it has not been put to practical use.

Therefore, an object of the present invention is to provide a method for manufacturing a low-cost MIS semiconductor device by providing a substrate bias terminal on the top surface of the substrate without adding a manufacturing process such as a photoetching process that increases costs. There's K things to do.

In order to achieve such an object, the present invention includes a step of forming a field insulating film except for an element formation region on the surface of a semiconductor substrate where an MI8 semiconductor element is to be formed and a peripheral region of the surface of the semiconductor substrate; a step of forming a gate insulating film in the element formation region and a peripheral region; a step of forming a gate [pole pattern] in the element formation region; and a step of forming another electrode pattern in the peripheral region; comprising the steps of: removing at least a portion of the other electrode pattern and the gate insulating film thereunder to expose a peripheral region; and forming an ohmically connected electrode in the exposed portion of the peripheral region. It is characterized by

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An N-channel silicon gate MO8) run lister according to an embodiment of the present invention and a method for manufacturing the same will be described in detail below in the order of steps with reference to the drawings.

(To) A silicon wafer (substrate) 1 as shown in FIG. 1, which has been subjected to various wafer treatments using well-known techniques, is prepared as a starting material. In the figure, 1 is a P-type silicon wafer, 2 is a field oxide silicon film with a selective oxidation structure formed by selectively thermally oxidizing the surface of the silicon wafer 1, and 3 is a channel stopper provided under the field silicon oxide film 2. The P-type layer 4 is a gate oxide silicon film, and 5 is a polycrystalline silicon film formed by a CVD method, each having a thickness of about 5000A.

A is a scribe area in the silicon wafer 1, and B is an element forming area.

0) Etch off unnecessary parts of the polycrystalline silicon film 5 by photo-etching or the like to form a multi-coupled silicon film 5a for the gate electrode and a polycrystalline silicon film 5b as an ohmic connection body for the substrate VBB terminal. do.

Next, using this polycrystalline silicon film 5a for the gate electrode as a mask, the gate silicon oxide film 4 is selectively etched by a self-alignment method, and then the N+ for the source is etched.
At the same time as forming the type layer 6 and the drain N+ type layer 7, impurities are diffused into the polycrystalline silicon film 5a+5b to make it a low resistance material. FIG. 2 shows a plan view thereof, and FIG. 3 shows a sectional view taken along the line AA' in FIG. As shown in the figure, the shape of the polycrystalline silicon film 5b as an ohmic connection body for the substrate bias VBB terminal is such that it is provided in a part of the scribe region 8 in the wafer 1 and a part on the field silicon oxide film 2, and On the silicon oxide film 2, a pad electrode is formed with a slightly wide area.

C) After forming a phosphosilicate glass (PSG) film 9 on the entire surface, a contact window is formed thereon. Next, a drain electrode, a source electrode S, and a substrate bias pad electrode C are formed using aluminum vacuum evaporation and photoetching techniques.

Next, a surface protective film such as a silicon oxide film is formed by a CVD method or the like, and this surface protective film 10 is selectively removed to expose the surface of the bonding pad electrode such as the band electrode C. In this case, the surface protective film 10 in the scribe region is also removed to expose the surface of the N+ type layer 8 and the surface of the polycrystalline silicon film 5b in that region. (Figure 4)
b) Silicon wafer 1 using surface protective film 10 as a mask
A high concentration of boron impurity 11 is ion-implanted into the scribe region to form an N+ type layer 8 in the scribe region.
is inverted to form a P+ type R111a, and the polycrystalline silicon film 5b is chemically formed into an extremely low resistance film (FIG. 5).
. This boron ion implantation makes the scribe area P
It has a +-type layer 11a, and good ohmic contact and connection with the substrate bias polycrystalline silicon film 5b can be made.

In another embodiment, as shown in FIG. 7, a structure is adopted in which impurity diffusion is prevented even when polysilicon is left around the pellet and source/drain diffusions 6 and 7 are formed, and a cross-sectional structure is shown in FIG. Only the scribe area is removed after the diffusion is completed. An interlayer insulating film 2 is deposited by a CVD method or the like, and an aluminum layer is deposited by a vacuum evaporation method or the like, and then directly connected to the substrate as shown in FIG. 9C.

The aluminum layer and the P-type laminate form an ohmic connection, making it possible to extract the substrate potential from the top surface of the chip.

(a) Scratch and divide the scribe region of the silicon wafer 1 to obtain N-channel silicon gate type MOS transistors according to the present invention (FIG. 6).
.

In addition to the embodiments of the present invention described above, the gate electrode material may be made of an infusible metal (refractory metal) such as molybdenum or tungsten, or aluminum, and the gate insulating film material may be made of nitride, alumina, etc. M.I.
The present invention can be applied to various types of MIS semiconductor devices such as S transistors, MISICs, and LSIs, and methods for manufacturing the same.

N-channel silicon gate type MO8) according to the present invention
MIS semiconductor devices such as runlisters and their manufacturing methods use a manufacturing process in which a MIS element, which is a main element, is formed on a semiconductor substrate, and a substrate bias VBB terminal (bad electrode) can be taken out from the top surface of the substrate. Therefore, in the mounting of the MIS semiconductor device according to the present invention,
Substrate bias V for packages such as ceramic packages
Since there is no need to provide conductor wiring for the BB terminal and an inexpensive package can be used, the cost can be significantly reduced.

[Brief explanation of drawings]

1 and 3 to 6 are cross-sectional views of a semiconductor device showing an N-channel silicon gate type MOS transistor and its manufacturing method, which is an embodiment of the present invention, and FIG. 2 is a plan view of FIG. 3. , FIG. 7 is a plan view of a semiconductor device according to another embodiment of the present invention, and FIGS. 8 and 9 are sectional views of a semiconductor device according to other embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Pi silicon wafer (substrate), 2... Field silicon oxide film, 3... P-shaped layer for channel stopper, 4, 4a... Gate silicon oxide film,
5... Polycrystalline silicon film, 5a... Gate electrode, 5
b... Polycrystalline silicon film for substrate bias VBB terminal,
6... Source, 7... Drain, 8... N-type layer, 9... Insulating film, 10... Surface protective film, 11...
Boron impurity, 11a...P medium layer, C...substrate bias VBB pad electrode, D...drain electrode, S
...Source electrode. Agent: Patent Attorney Katsuo Ogawa, 1st
Figure 2 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7. 〆Figure 8 Section 9

Claims (1)

[Claims] 1. A step of forming a field insulating film except for the element formation region on the surface of the semiconductor substrate where the MIS semiconductor element is to be formed and the peripheral region of the semiconductor substrate surface, and forming a gate insulating film in the element formation region and the peripheral region. forming a film; forming a gate electrode pattern in the element formation region and forming another electrode pattern in the peripheral region; A method for manufacturing an MIS semiconductor device, comprising the steps of: removing the gate insulating film to expose a peripheral region; and forming an ohmically connected electrode in the exposed portion of the peripheral region.