JPH0318034A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a restriction in a process design by removing a silicon nitride film except an electrode by dry etching at the time of forming a sidewall. CONSTITUTION:After a silicide 4 is deposited, a silicon nitride film 5 is grown on its upper layer, and then an electrode is patterned. A silicon nitride film 6 is again deposited on the patterned electrode, a silicon dioxide film 7 is thereafter deposited by a CVD method, and a sidewall is formed by an anisotropic dry etching. The sidewall of silicon dioxide is formed on the sidewall of the electrode by the dry etching, the film 5 deposited initially remains on the electrode at the same time, and the silicon nitride film except the electrode is all removed. Thus, a restriction in a process for omitting a heat treatment can be eliminated, and the degree of freedoms in a process design can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a high melting point metal or silicide as electrodes and wiring.

Conventional Technology In the era of ultra-large scale integrated circuits (VLSI), element dimensions have been reduced to submicron casings, and at the same time as semiconductor circuits have become more highly integrated, the speed of semiconductor circuits has also increased. In order to achieve higher speeds, in addition to reducing element dimensions, high-melting point metals or silicides with low resistance are increasingly used as electrode or wiring materials.

FIG. 2 shows a case where silicide is used for the gate electrode of a MOS type transistor. As shown in the figure, silicide generally has a two-layer structure with polycrystalline silicon. This is to prevent high melting point metals and metals contained in silicide from diffusing into the semiconductor substrate 1 and silicon dioxide film 2 and adversely affecting the electrical characteristics of the device. It becomes. Figure a shows a cross-sectional view of an electrode pattern formed by photolithography and dry etching processes after depositing polycrystalline silicon and crystalide films. The conventional process is shown below.

After forming the electrodes as shown in FIG. 2a, ions are implanted into the semiconductor substrate on both sides of the electrodes to form source/drain regions 8. After ion implantation, a silicon dioxide film 7 is deposited by CVN method (FIG. 2b).

Next, the silicon dioxide film is etched using anisotropic dry etching. At this time, as shown in Figure C, a silicon dioxide film remains on the sidewalls of the gate electrode.

This residue is generally called a sidewall, and after forming the sidewall, ions are implanted again to form the source/drain region 9.

The above structure is called an LDD structure, and the source and gate electrode
Used when the length between drains is about 1 μm or less,
It is now the most common.

Normally, in the case of an n-ch MOs transistor, the source and drain 8 are ! J/(P) ion implantation, and later implantation region 9 is formed by arsenic (▲S) ion implantation.

After forming the source/drain regions, ions are activated by heat treatment at approximately 900°C, and the gate electrode and source/drain regions are further oxidized in an oxidizing atmosphere at the same temperature to grow the silicon dioxide film 10. areas are completely isolated from each other. Thereafter, as shown in FIG. 4D, an insulating film 11 is formed by the CVD method, and further upper layer wiring is formed.

Problems to be Solved by the Invention The problems will be explained by taking silicide as an example. A problem with silicide is abnormal oxidation at high temperatures. If silicide is heat treated at 500°C or higher after vapor deposition, the diameter will be 0.
Aggregates (grains) of particles of about 1 to 0.2 μm are formed, but if heat treatment is performed again with the surface exposed in this state, metal tungsten, etc., which will crumble in a certain amount of time, will form oxides and abnormalities will occur. causes oxidation. Furthermore, the metal components contained during high-temperature heat treatment diffuse into semiconductor substrates, etc.
Problems in electrical characteristics such as defects and micro leaks caused by defects are also likely to occur.

In order to avoid these problems, methods have been taken to omit heat treatment, but in reality, some heat treatment is required to stabilize the characteristics of the device, and there are many constraints on process design. It's going to happen.

Means for Solving the Problems The present invention solves the above problems. for example,
As shown in FIG. 1 of the embodiment, after silicide is deposited, a silicon nitride film is grown on top of the silicide, and then electrodes are patterned (FIG. 1a).

Next, a silicon nitride film is deposited again on the patterned electrode, and then a silicon dioxide film is deposited by CVD as in the conventional method.
The sidewalls are formed by anisotropic dry etching (FIG. 1C).

As shown in the figure, as a result of this dry etching, sidewalls of silicon dioxide are formed on the sidewalls of the Ti, and at the same time, the silicon nitride film that was initially deposited remains on the top of the electrode, causing the electrode to deteriorate. All of the silicon nitride film other than the portion is removed.

According to the above means, since the silicon nitride film prevents oxygen from permeating, it is possible to suppress abnormal oxidation of the silicide in a high-temperature oxidizing atmosphere, and at the same time, prevent the diffusion of the metal contained therein. Furthermore, as shown in FIG. 1C, since the silicon nitride film other than the electrode portions is removed by dry etching during sidewall formation, subsequent processes can proceed in the same manner as before.

EXAMPLE Hereinafter, an example of the present invention will be described according to the example shown in FIG. As shown in Figure B, a silicon dioxide film of 250 layers 2, a polycrystalline silicon layer of 2000 layers 3, a tungsten silicide layer of 2500 layers 4, and a silicon nitride film 1 are formed on a semiconductor substrate 1.
The gate electrode of the certain long film is shaped by a photolithography and dry etching process. Note that the silicon nitride film No. 6 is grown to some extent by plasma CVN method at 600°C or less.

Next, phosphorus ions are implanted using an ion implantation method to form source/drain regions 8. Thereafter, the entire surface is coated with a silicon nitride film of 400 mm 6 and a silicon dioxide film of 3000 mm 7 by the CVD method (FIG. b).

Then, as shown in Figure C, the entire surface is etched by anisotropic dry etching. At this time, the source/drain region 9
The silicon nitride film on top of is also removed by dry etching. Etching is stopped when the source/drain region 9 is exposed. Then, a silicon dioxide film is formed as a sidewall on the side wall of the electrode, and the silicon nitride film 6 on the upper part of the electrode is removed by dry etching, but the silicon nitride film 6 that was initially grown remains. state.

Thereafter, arsenic is implanted into the source/drain region 9 by ion implantation, followed by heat treatment at 900° C. and oxidation as in the conventional example, thereby forming an interlayer insulating film for insulation from the upper layer metal wiring.

Effects of the Invention According to the present invention, even if high-melting point metals or silicides are used for electrodes and wiring, abnormal oxidation due to the contained metals during high-temperature heat treatment can be prevented, and the adverse effects on electrical characteristics due to diffusion of the metals can be prevented. It also prevents Further, there is no need for process constraints such as omitting the current heat treatment, and the degree of freedom in process design increases.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the manufacturing process of a conventional example. 1... Semiconductor substrate, 2... Silicon dioxide film, 3... Polycrystalline silicon, 4... Silicide, 5.6... Silicon nitride film, 7...
...Silicon dioxide film, 8... Phosphorous implantation region,
9...Arsenic implantation region.

Claims (1)

[Claims] A step of vapor depositing a high melting point metal or silicide film on one main surface of a substrate semiconductor, a step of vapor depositing a silicon nitride film on the film, and photolithography and dry etching of the silicon nitride film and the high melting point metal or silicide film. a step of etching using a method to form a pattern, a step of depositing a silicon nitride film on the pattern, a step of depositing a silicon dioxide film on the silicon nitride film, and etching the silicon dioxide film by an anisotropic dry etching method. A method of manufacturing a semiconductor device, comprising the steps of etching a silicon nitride film.