JPH02186625A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To satisfactorily prevent any Si nodule in aluminum electrode wiring layer from occurring by a method wherein a polycrystalline silicon doped with As is removed to make an electrode window in one conductivity type base region; the polycrystalline silicon is left as if encircling the electrode window; and an aluminum electrode wiring is formed to be brought into contact with the polycrystalline silicon. CONSTITUTION:A polycrystalline silicon layer 29 in thickness exceeding 80nm is formed on the whole surface of a silicon epitaxial layer 23 in electrode windows 27, 28 as well as an insulating layer 26; As ion is implanted before heat treatment; and then an emitter region 31 is formed. A resist layer 34 with an opening is formed on a electrode formation part while the polycrystalline silicon layer 29 is etched and then the insulating layer 26 is selectively etched to make a base electrode window 22. After removing the resist layer 34, an aluminum layer 33 is formed on the whole surface. Finally, the aluminum layer 33 is etched away to form respective patterns of an emitter electrode 33A, a base electrode 33B, a collector electrode 33C and an aluminum wiring.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device, more specifically, a method for manufacturing a semiconductor device using aluminum (
Regarding the improvement of electrode wiring structures including wiring (including Al and A72 alloy), a method for sufficiently preventing reactions (dissolution and precipitation of 34) between polycrystalline silicon layers and aluminum wiring on the wiring and substrate surfaces. In addition, the purpose is to provide a method for manufacturing a semiconductor device that simplifies the process of forming a polycrystalline silicon layer. An insulating layer is formed to cover the electrode formation portion of the one conductivity type region, and an insulating layer is formed on the entire surface of the substrate to a thickness of 8.
Forming a polycrystalline silicon layer of 0r+m or more, doping As on the entire surface of the polycrystalline silicon layer and heat-treating it to form an opposite conductivity type region on the surface of the one conductivity type region, and forming an electrode forming part in the one conductivity type region. After removing the polycrystalline silicon layer and the insulating layer to form an electrode window in the one conductivity type region, an electrode wiring layer containing aluminum is formed on the entire surface of the substrate-1. A one-conductivity-type system having a crystalline silicon layer partially removed to have an electrode wiring in an opposite-conductivity-type region consisting of the electrode wiring layer and a polycrystalline silicon layer, and a polycrystalline silicon layer surrounding an electrode window in the one-conductivity-type region. The method of manufacturing a semiconductor device is characterized in that the electrode wiring is formed in the area.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in an electrode wiring structure including aluminum (including Aβ and A1 alloy) wiring.

[Conventional technology]

In recent years, with the increasing integration and miniaturization of semiconductor devices, aluminum electrode wiring has also become smaller, and measures such as reducing contact resistance and preventing the occurrence of alloy spikes (especially emitter hair shot in Java junction structures) have become necessary. is now needed.

Therefore, the aluminum electrode wiring of the emitter, which contacts the silicon substrate surface through the electrode window of the insulating layer, is not brought into direct contact with the surface of the silicon substrate, but is sandwiched between polycrystalline silicon layers. At this time, the polycrystalline silicon layer exists not only within the electrode window but also under the entire aluminum wiring (that is, between the insulating layer and the aluminum wiring). This polycrystalline silicon layer is dissolved into the aluminum wiring by various heating processes in the multilayering process, and becomes Si nodules (Si precipitation).
This results in an increase in wiring resistance and a decrease in migration resistance.

In order to prevent this S1 failure in the aluminum wiring part, in the conventional semiconductor device manufacturing method, the third
As shown in Figure 3 (■3), the polycrystalline silicon layer l should be applied only to the electrode window of the insulating film 2 and its vicinity, and should not be exposed under the other aluminum oxide films and wiring 10. It has been removed.

3(A) and 3(B) are examples of a bipolar I-Lancistor, in which a silicon epitaxial layer 3B is formed on a silicon substrate 3Δ, and the relationship between the substrate 3A and the epitaxial layer 3B is A buried layer 4 is formed in between, and a collector contact region 5, a base region 6 and an emitter region 7 are formed in this epitaxial layer 3B. There is a SiO□ insulating layer 2 on the second side of the silicon epitaxial layer 3B, and an electrode window (contact hole H1,
12 and 13 are formed, and a polycrystalline silicon layer 1 is formed on the insulating layer 2'2 in and around the emitter electrode window 11 and the collector electrode window 13. The aluminum electrode wiring 10 includes an emitter electrode 10A, a collector electrode 10B, and a base electrode 10C, which are formed at the same time.

In the semiconductor devices shown in FIG. 3 (Δ) and FIG. 3 (B),
The polycrystalline silicon layer 1 is present only in the electrode window and its vicinity, but if the area of the polycrystalline silicon layer 1 is not set appropriately by taking into consideration the area of the aluminum electrode wiring layer 10, the aluminum electrode wiring In the subsequent heating process, the layer 10 is heated to form silicon (Si) not only from the polycrystalline silicon layer 1 but also from the epitaxial layer 3B, which is also a silicon substrate.
) may cause junction damage. Polycrystalline IJ:
The design of the I-in layer and its area is subject to various constraints.

In addition, in FIGS. 3(8) and 3(B), silicon is sucked up from the epitaxial layer 3B into the aluminum oxide layer 10 of the base electrode 10c, increasing the contact resistance of the base electrode and reducing the migration resistance. This results in a decrease in

Therefore, a polycrystalline silicon layer is formed in the base electrode window as well as in the emitter and collector electrode windows, and BF2'' ions are implanted as l) type impurities into the polycrystalline silicon layer in the base electrode window. A method has been considered (Japanese Patent Laid-Open No. 63-77138).

[Problems to be Solved by the Invention] However, this method of implanting BF2'' ions cannot sufficiently prevent the reaction between the polycrystalline silicon layer and the aluminum layer in the portion where the BF,' ions are implanted, and S
This causes dissolution and precipitation of t.

The purpose of the present invention is to propose a method for sufficiently preventing the reaction between the polycrystalline silicon layer and the aluminum electrode wiring (dissolution and precipitation of St), and also preventing the reaction between the semiconductor substrate, aluminum oxide J, and the electrode wiring. Another object of the present invention is to provide a method for manufacturing a semiconductor device that simplifies the step of forming a polycrystalline silicon layer.

[Failure to solve the problem]

The above-mentioned object is to form an insulating layer on a semiconductor substrate having a region of one conductivity type on its surface, provided with a window for an electrode of an opposite conductivity type region, and covering an electrode formation part of the region of one conductivity type; A polycrystalline silicon layer with a thickness of 80 nm or more is formed on the entire surface of the substrate, and the entire surface of the polycrystalline silicon layer is doped with As and heat treated to form an opposite conductivity type region on the surface of the one conductivity type region. After removing the polycrystalline silicon layer and the insulating layer in the electrode formation part of the mold region to form an electrode window in the one conductivity type region,
An electrode wiring layer containing aluminum is formed on the entire surface of the substrate, and the electrode wiring layer and the polycrystalline silicon layer are partially removed to form an electrode wiring layer and a polycrystalline silicon layer in opposite conductivity type regions. This is achieved by a method of manufacturing a semiconductor device characterized by forming an electrode wiring of one conductivity type region having a polycrystalline silicon layer surrounding an electrode window of the one conductivity type region.

[Function] According to the present invention, by doping a polycrystalline silicon layer with a predetermined thickness with As impurities and without heat treatment (850 to 1150°C), the dale size of polycrystalline silicon can be increased and the grain size can be increased. It is possible to increase the strength of bonding at boundaries (grain boundaries), and the aluminum electrode wiring layer and polycrystalline silicon that are in contact do not react even during heating during the multilayering process, preventing the generation of Si nodules. Can be done.

Furthermore, this As impurity-doped polycrystalline silicon is removed to form an electrode window in the base region of one conductivity type, but polycrystalline silicon is left surrounding the electrode window and is in contact with the polycrystalline silicon. Since the aluminum electrode wiring is formed using the aluminum electrode wiring, it is possible to suppress the suction of silicon from the semiconductor substrate by supplying silicon from the polycrystalline silicon, and it is possible to prevent a reaction between the semiconductor substrate and the aluminum electrode wiring.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail by way of embodiments with reference to the accompanying drawings.

FIGS. 1A to 1E are schematic cross-sectional views of a semiconductor device illustrating steps according to a method of manufacturing a semiconductor device according to the present invention. Although this semiconductor device is an NPN type bipolar transistor, the present invention can also be applied to PNP type bipolar transistors and N-channel MO3FETs.

To manufacture an NPN bipolar transistor, first, as shown in FIG.
After doping impurities that will become the buried layer 22, an N-silicon epitaxial layer 23 is formed on the silicon substrate.

N+ collector contact region 2 in epitaxial layer 23
4 and a P-heave region 25 are formed. Then, a 5i02 insulating layer 26 is formed on the entire surface, and the insulating layer is selectively etched to open predetermined emitter electrode windows 27 and collector electrode windows 28 to expose the epitaxial layer 23.

Next, as shown in FIG. 1B, polycrystalline silicon is deposited on the entire surface of the silicon epitaxial layer 23 and insulating layer 26 in the electrode windows 27 and 28 to a thickness of 80 nm by vapor phase growth.
A polycrystalline silicon layer 29 having a thickness of m or more is formed. As ions are applied to this polycrystalline silicon layer 29 at a dose of 1015 to 10
Ion implantation is performed at 16 cm −2 . Then, heat treatment (for example, 30 minutes at 1000"c) is performed to diffuse As in the polycrystalline silicon layer 29 into the base region 25 of the epitaxial layer 25 to form the emitter region 31, and at the same time, The drain of polycrystalline silicon is increased. Note that it is also possible to use As thermal diffusion instead of As ion implantation and heat treatment.

As shown in FIG. 1(C), a resist layer 34 with an opening is formed in the base electrode forming part by lithography technology, and using this as a mask, the polycrystalline silicon layer 29 is etched, and then the insulating layer 26 is etched by j'. A base electrode window 32 is opened by etching.

Next, as shown in FIG. 1(D), after removing the resist layer 32, an aluminum layer (A7! or an alloy such as 1-3i, 8E-3i-Cu) 33 is coated on the entire surface to a thickness of to form.

Next, the aluminum layer 33 is etched using a resist layer patterned by a known lithography technique as a mask to form emitter electrode 33A, base pole 33B, collector electrode 33C, aluminum oxide 1, and wiring patterns. Subsequently, the underlying polycrystalline silicon layer 29 is patterned in the same manner as shown in FIG. 1(E). This patterning is usually done by forming a resist pattern through resist coating, exposure and phenomenon, and using this as a mask by RIE.
This is done by selectively etching the aluminum layer and then the polycrystalline silicon layer using a (reactive ion etching) method or the like. In this way, the aluminum wiring layer 3
An electrode wiring structure is obtained in which the polycrystalline silicon layer 29 exists under all of the electrodes 3A, 33B, and 33C.

The polycrystalline silicon layer 29 forms a base electrode 33B provided so as to surround the space electrode window 32, and the polycrystalline silicon layer 29 with a large diameter forms the base electrode 33B.
The aluminum of B is supplied to the portion of the substrate surface that contacts the silicon to prevent silicon from precipitating in the aluminum layer of the base electrode 33B.

Thereafter, when a glabellar insulating layer, a second wiring layer, etc. are formed in order to make the wiring multilayered, heating is performed at 400 to 150°C. When the number of 81-nosinol precipitated in the aluminum layer was investigated, it was found that there was almost no 81 nosinol.

The following experiment was conducted regarding the generation of S1 nocière.

A polycrystalline silicon layer (thickness: 50 nm, 80 nm, and 1100 nm, respectively) was formed on a silicon wafer (1) by the CVD method, and As ions were implanted at a dose of 5×10 15 cm −2 and an energy of 60 keV. After the implantation, heat treatment was performed at 900° C. for 130 minutes in a nitrogen atmosphere. As a comparative example, such ion implantation and heat treatment were not performed. Next, an aluminum (containing 2% Cu) layer was formed to a thickness of 1 μm on the polycrystalline silicon layer by sputtering.

In order to promote melt penetration and precipitation of polycrystalline silicon into the aluminum layer, heat treatment at 450°C for 30 minutes was repeated four times. Then, the number of silicon crystals (Si nodules) deposited in the aluminum layer was investigated, and the results shown in FIG. 2 were obtained. As can be seen from Fig. 2, the number of Si nodules is large when ions are not implanted, but the number decreases when As ions are implanted, and the thickness of the polycrystalline silicon layer is reduced to 80 nm.
If the difference is seven, Si nodules will not be generated.

For reference, in FIG. 2, the number of Si nodules generated in the case of BFz" ion implantation is indicated by △.

In this case, 6 OF2 ions are introduced into the polycrystalline silicon layer.
Ion implantation was performed at a dose of 5 XIO"cm-2 at an energy of 0 keV, and heat treatment was performed at 1000'CX for 30 minutes in a nitrogen atmosphere. Then, as described above, an aluminum layer was formed and the heat treatment was repeated. The number of Si precipitates was investigated.
It can be seen that nodule generation is prevented.

[Effects of the Invention] As explained above, according to the present invention, the polycrystalline silicon layer is not limited to the electrode window and its vicinity (therefore, the extra patterning process is unnecessary), and the alumina 1, The generation of Si 2 nodules in the electrode wiring layer can be sufficiently prevented, and furthermore, the generation of Si 2 nodules in the aluminum electrode wiring layer at the contact 1 between the silicon and aluminum electrode wiring layers of the semiconductor substrate can be prevented.

[Brief explanation of the drawing]

1 (Δ) to (F,) are schematic cross-sectional views of a semiconductor device for explaining the steps in the method of manufacturing a semiconductor device according to the present invention, and FIG. FIG. 3(A) is a partial plan view of a conventional semiconductor device, and FIG. 3(B) is a graph showing the relationship between the number and the thickness of a polycrystalline silicon layer. FIG. 1 is a schematic cross-sectional view of a semiconductor device. 21... Silicon substrate, 23... Silicon epitaxial layer, 26... Si
O□Insulating layer, 29... Polycrystalline silicon layer, 33A
, 33B, 33C...aluminum electrode (wiring layer).

Claims (1)

[Scope of Claims] An insulating layer is formed on a semiconductor substrate on which a region of one conductivity type is formed, an insulating layer is provided with a window for an electrode of an opposite conductivity type region, and covers an electrode formation portion of the one conductivity type region, forming a polycrystalline silicon layer with a thickness of 80 nm or more over the entire surface of the substrate, doping the entire surface of the polycrystalline silicon layer with As and heat-treating it to form an opposite conductivity type region on the surface of the one conductivity type region; After forming an electrode window in the one conductivity type region by removing the polycrystalline silicon layer and the insulating layer in the electrode formation portion of the conductivity type region, forming an electrode wiring layer containing aluminum on the entire surface of the substrate; The electrode wiring layer and the polycrystalline silicon layer are partially removed to form a polycrystalline silicon layer surrounding the electrode wiring in the opposite conductivity type region consisting of the electrode wiring layer and the polycrystalline silicon layer and the electrode window in the one conductivity type region. 1. A method of manufacturing a semiconductor device, comprising forming an electrode wiring in a region of one conductivity type.