JPH0897212A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a manufacturing method of a semiconductor device wherein wiring can be formed as a thin film, the warp of a wafer can be reduced, and the formation of fine wiring can be realized with high yield. CONSTITUTION: After an interlayer insulating film 103 is formed on a P-type semiconductor substrate 101 on which various kinds of elements are formed, a contact hole 104 for electric connection with an N-type diffusion layer 102 is formed. After a titanium nitride film 105 as a barrier layer is deposited by a sputtering method, a tungsten film 106 is deposited by a CVD method. Since the CVD film of W contains considerable tensile stress, W ions are implanted in order to reduce the stress. As the result, the warp of a 6-inch wafer is reduced from about 120μm to about 40μm. After the W film 106 and the TiN film 105 are patterned, and a W wiring 108 is formed by etching, a semiconductor chip is completed by a conventional technique. Since the warp of a wafer in the course of patterning of the W wiring is relieved, flatness of the wafer is ensured, and a low resistance wiring can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a metal wiring with low stress is formed.

[0002]

2. Description of the Related Art With the rapid development of the semiconductor industry in recent years, demands for high speed and miniaturization of semiconductor devices are increasing. As an effective means for coping with speeding up and miniaturization in a semiconductor device, it has been general to use a refractory metal having a low resistance value as a gate electrode or a wiring material. Tungsten and tungsten silicide are most widely used as the refractory metal having a low resistance value.

Next, a conventional method for forming metal wiring will be described with reference to the drawings. 3A to 3C are cross-sectional views in order of the steps of the conventional method for forming a tungsten wiring.

As shown in FIG. 3A, various elements (not shown) are formed on a p-type semiconductor substrate 301, an interlayer insulating film 303 is formed, and n-type diffusion is performed between the various elements. A contact hole 304 is formed for connection through the layer 302. Next, as shown in FIG. 3B, a titanium nitride film 305 is deposited by a sputtering method in order to improve the adhesion with the barrier metal and tungsten. Next, the tungsten film 306 is deposited by a sputtering method, a CVD method, or the like. Next, as shown in FIG. 3C, patterning is performed by a normal lithography technique and etching is performed to form a tungsten wiring 308.

Generally, a refractory metal typified by tungsten has a strong tensile stress, and this characteristic becomes more remarkable when it is formed as a deposited film and subjected to heat treatment or the like. This is due to vacancies and thermal stress in the film (due to the different expansion coefficients of the semiconductor substrate and the tungsten film), both of which are due to the low density of the tungsten source in the tungsten film. .

The metal wiring manufactured by the above-mentioned conventional forming method has poor adhesion to the base due to the strong tensile stress of the refractory metal, and film peeling may occur.
Further, even if it does not peel off, the warp of the wafer may be increased. When the amount of warp of the wafer is large, in the patterning process for forming the wiring, for example, in the exposure process using a stepper, focus shift occurs due to an increase in height difference, and it becomes difficult to form a wiring having a desired size. .

As a method for solving the above problems, a method for relaxing the stress of the refractory metal is considered, and the following two are proposed as known examples. One is Japanese Patent Laid-Open No. 2-2
A method of ion-implanting N ⁺ ions into a tungsten polycide film as proposed in Japanese Patent No. 50319, and another method for a tungsten polycide film as proposed in Japanese Patent Laid-Open No. 4-305933. This is a method of implanting impurity ions such as phosphorus. In any of these cases, the ion implantation is performed to make the deposited film amorphous so that the stress is reduced and the amount of warpage is low.

[0008]

When the film peeling occurs due to the stress of the metal wiring, not only the wiring cannot be formed as described above, but also the peeled film of the normally formed wiring becomes dust. It causes a short circuit between them. Therefore, there is a problem that the yield is significantly reduced.

Further, when the warp of the wafer increases, it becomes difficult to form a wiring having a desired size, so that there is a problem that miniaturization is significantly hindered.

In order to solve these problems, stress relaxation methods for metal wiring have been proposed. In the conventional stress relaxation methods for refractory metal wiring, however, different elements are ion-implanted on the refractory metal. Therefore, the resistance value of the metal wiring increases. For this reason, in order to obtain a desired low-resistance wiring, it is necessary to increase the wiring film thickness, which makes it difficult to flatten in the subsequent process, and there is a problem that miniaturization is also significantly hindered.

The present invention has been made in view of the problems of the prior art as described above, and it is possible to reduce the amount of warp of the wafer and to form fine wiring while thinning the wiring. It is an object of the present invention to realize a method for manufacturing a semiconductor device, which can perform the above-mentioned steps with high yield.

[0012]

According to a method of manufacturing a semiconductor device of the present invention, a metal wiring film is deposited on a semiconductor substrate.
And a second step of forming a metal wiring by patterning the metal wiring film deposited in the first step.
The method for manufacturing a semiconductor device, which comprises the step of including a third step of implanting metal ions of the same metal element as the metal wiring film between the first step and the second step. Characterize.

The metal element in this case may be tungsten.

[0014]

By implanting ions into the metal wiring film deposited in the first step, the holes in the metal wiring film are filled and the stress is reduced. The ions implanted at this time are
Since the metal element is the same as that of the wiring film, the resistance value of the metal wiring film does not increase.

[0015]

Embodiments of the present invention will now be described with reference to the drawings. 1A to 1D are sectional views sequentially showing steps of a first embodiment according to the method of manufacturing a semiconductor device of the present invention.

As shown in FIG. 1A, after various elements are formed on the p-type semiconductor substrate 101, the interlayer insulating film 10 is formed.
3 is a cross-sectional view after the formation of No. 3 and the formation of the contact hole 104 for electrically connecting to the n-type diffusion layer 102. FIG. Next, as shown in FIG. 1B, the titanium nitride film 105 is formed.
Is deposited by the sputtering method at 500 liters. This film is used as a barrier metal. Next, the tungsten film 106
Is deposited by the CVD method at 3000 Å. The tungsten film 106 deposited by the CVD method generally has a tensile stress of about 1 × 10 ¹⁰ dyn / cm ² though it depends on the conditions. Therefore, the amount of warp of the wafer generated is 6 inch wafer. Is about 120 μm.

Next, in order to reduce the stress of the tungsten film 106, the tungsten ion implantation shown by the arrow 107 is performed at a accelerating energy of 70 keV, for example, 1 × 1.
It is carried out under the condition of an implantation amount of 0 ¹⁶ cm ^-2 . When the ion implantation is performed under these conditions, the stress is relaxed to about 3 × 10 ⁹ dyn / cm ^{2 in} this embodiment, depending on the quality of the tungsten film, and as a result, the wafer warp amount is also about 40 μm.
Decreased to.

Next, similar to the conventional example shown in FIG. 3C, the tungsten film 106 and the titanium nitride film 105 are patterned and etched by a normal lithography technique, as shown in FIG. 1C. The tungsten wiring 108 is formed. After that, the semiconductor chip is completed by using the same technique as the conventional technique. Since the amount of warp of the wafer is reduced in the patterning process of the tungsten wiring 108, the flatness of the wafer can be secured by vacuum suction of the wafer on the stage even with the conventional stepper, and the pattern of about 0.35 μm can be obtained. Can be formed with good controllability. Also, tungsten wiring 1
The resistance value of 08 is almost the same as that of the same type of tungsten ion-implanted.
The desired low resistance wiring could be obtained even with a thin film of about 000Å.

Next, as a second embodiment of the present invention, a case where the method according to the present invention is applied to form a tungsten polycide gate electrode of a MOS transistor will be described. 2A to 2D are cross-sectional views sequentially showing steps of the second embodiment of the present invention.

As shown in FIG. 2A, the p-type semiconductor substrate 1
A LOCOS isolation region 209 is formed thereover by a usual method. Next, as shown in FIG. 2B, the gate oxide film 210
Is thermally oxidized to form 200Å. Next, a polycrystalline silicon film 211 is deposited by 2000 Å by the LPCVD method, and high-concentration phosphorus doping is performed by the usual phosphorus diffusion method.
Next, the tungsten silicide film 12 is sputtered to form 2
Form 500Å. Next, the tungsten silicide film 21
Acceleration energy of tungsten from the surface on 70k
Ion implantation is performed under the conditions of eV and an implantation dose of 1 × 10 ¹⁶ cm ^-2 . Next, as shown in FIG. 3C, the polycrystalline silicon film 211 is formed by the usual lithography technique and etching technique.
Then, the tungsten silicide film 212 is patterned. After that, a source / drain region 213, an interlayer insulating film 203, an aluminum wiring 214, a surface protective film 215, etc. are formed by the conventional technique as shown in FIG. 3C to form a semiconductor device as shown in FIG. 2D. To complete.

According to the manufacturing method as described above, the arrow 20
By performing the tungsten ion implantation shown by 7, the stress of the tungsten silicide film 212 is relaxed, the warp amount of the 6-inch wafer is reduced from about 100 μm to about 40 μm, and the gate electrode width of about 0.5 μm is reduced. It became possible to form.

In this embodiment, the application example to the tungsten film and the tungsten polycide film is described, but it goes without saying that the application can be applied to all other metal films.

[0023]

Since the present invention is configured as described above, it has the following effects.

By ion-implanting the stress of the metal wiring with the same kind of element, the resistance value can be relaxed without increasing the resistance value. Therefore, the wiring can be thinned and the amount of warp of the wafer can be reduced. There is an effect that various wiring can be formed.

Further, since the stress relaxation can prevent the film peeling of the metal wiring, it is possible to prevent the reduction of the yield.

[Brief description of drawings]

1A to 1C are sectional views in order of the processes, according to an embodiment of the present invention.

FIG. 2 is a sectional view in order of steps of a second embodiment of the present invention.

3A to 3C are sectional views in order of the processes, for illustrating the conventional technique.

[Explanation of symbols]

 101, 201 p-type semiconductor substrate 102 n-type diffusion layer 103, 203 interlayer insulating film 104 contact hole 105 titanium nitride film 106 tungsten film 107, 207 tungsten ion implantation 108 tungsten wiring 209 LOCOS isolation region 210 gate oxide film 211 polycrystalline silicon film 212 Tungsten silicide film 213 Source / drain regions 214 Aluminum wiring 215 Surface protection film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/768 H01L 21/90 C

Claims (2)

[Claims] 1. A first step of depositing a metal wiring film on a semiconductor substrate, and a second step of patterning the metal wiring film deposited by the first step to form a metal wiring. A method of manufacturing a semiconductor device, comprising a third step of implanting metal ions of the same metal element as that of the metal wiring film between the first step and the second step. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal element is tungsten.