JPS6032974B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention] ○｝Field of application of the invention The present invention relates to a method for manufacturing a semiconductor device.

'2} Conventional technology The degree of integration of semiconductor integrated circuits is increasing year by year, and the width of interconnections is becoming narrower and narrower.

As conventional wiring methods, in addition to using a diffusion layer in a semiconductor substrate, polycrystalline Si or metal films, which are separated from the semiconductor body by an insulating film such as a silicon oxide film, are often used. However, as described above, as the width of the wiring becomes smaller, breakage (cracks) in the metal wiring may occur, which may cause defects. In order to prevent this, LO, which is a selective oxidation method of Si using Si3N4, has been used.
COS (ISOPLANAR) and a glass flow method (utilizing the flow of the PSG film due to high superheating treatment) using a PSG film containing a high concentration of P205 have been used.
However, the former LOCOS alone is insufficient in terms of preventing cross sections, and the latter glass flow method
The scope of application is limited because it contains a high concentration of P and requires heat treatment at a high temperature (1000° C. or higher). For example, since it contains a high concentration of P, it has hygroscopic properties, and P24 in the PSG film reacts with P20 in the atmosphere, resulting in the reaction of P24 in the PSG film.
This causes corrosion of the mountain. Therefore, improvements to the package, passivation film, etc. have been required. Furthermore, since heat treatment at high temperatures is involved, it is difficult to accurately control the depth of the diffusion layer. Alternatively, there is a problem that a shallow diffusion layer cannot be formed.
Therefore, it is disadvantageous for highly integrated LSIs having short channel MOS-FETs as constituent units, and cannot be used for bipolar LSIs that require strict control of the thickness of the diffusion layer. For example, a PSG film with a P205 concentration of 1 skin ol, which is considered to be at the upper limit in terms of hygroscopicity, required heat treatment at least at 100,000 in dry N2 for about 3 minutes. At this heat treatment time, the diffusion layer formed by P becomes approximately 1 meter deep, although it depends on the concentration. or,
Even the diffusion layer formed by a ship with a small diffusion coefficient is 0.1
It becomes about 5m deep. {3} Purpose of the Invention The present invention aims to solve the problems described in detail above by performing planarization technology using the glass flow method using an insulating film such as a PSG film at a low temperature of 1000 qo or less. This is the purpose.

'4) General description of the invention In order to prevent metal wiring from breaking, it has been common practice to heat-treat a silicon oxide film containing impurities, such as a PSG film, at high temperatures. Well-known examples include phosphorus, rigidity, arsenic, lead, zinc, arsenic sulfide, and halides.

However, with only these impurities, there are few things that can be flattened by heat treatment at a low temperature of 1000 ohms or less. The present invention aims to lower the softening temperature by further including other impurities in the glass (Si02) containing these impurities.

Although the above-mentioned elements are well known as substances that lower the softening point, many of them are considered to be undesirable in terms of characteristics when constituting a semiconductor device. Incidentally, the study focused on the fact that Snake belongs to Group 4 and does not form a donor or acceptor level even if it enters Si. As a result, it is difficult to reduce the softening point to 1000q0 or less if the element contained in Sj02 is only 戊 or only the above-mentioned impurities except lead, but by containing Ge and at least one of the above-mentioned impurities, the Si02 film , 10000
It was found that it has a softening point of 0 or less. That is, the present invention is characterized in that the above object is achieved by depositing Si02 containing at least one of Ge and other impurities and then performing glass flow. These increase the latitude in manufacturing semiconductor devices and provide various possibilities. (5) Example First, Fig. 1 and Fig. 2 show the effect of smoothing the grain after heat treatment in 1000 oodryN2 for 20 minutes using the conventional method and an example of the present invention (G-dove PSC). This shows the effectiveness of the method according to the present invention compared to the conventional method.

Figures 3 and 4 are shown to clarify the effects at low temperatures, and show the effects of heat treatment in 850qodryN2 for 20 minutes for the conventional method and the method according to the present invention (Q-doped PSG). This is what is shown. With the subordinate method, there is almost no deformation of the grain, but with the present invention,
It can be seen that the twill portion was deformed smoothly, which was more effective than the 20 minute heat treatment in Loop Dry N2 in the case of the conventional method. Figure 5 shows a short channel F with a double peak gate length of m.
This figure shows an example in which the present invention is applied to a MOS type integrated circuit based on ET.

After forming a predetermined Si02 film 12 for element isolation and a gate Si02 film 13 on a P-type Sill with a resistivity of 100, source and drain diffusion layers 15 were formed using a self-alignment method of a polycrystalline Sj gate 14.

After that, P20517 mol% to Si02, Snake 0
N2 is used as a base, and Si is
A Si02 film 16 doped with W and P was formed by mixing H4 gas, PH3 gas, and QH4 gas with O2 gas and using a vapor phase growth method at a wafer temperature of 480 oo. After that, heat treatment was performed in dry N2 at 85,000°C for 10 minutes to gently deform the edge of the Si02 film 16, and then the source, drain, and gate were formed by photolithography using a predetermined photomask. A contact hole for electrical connection is formed, and further, 85
After heat treatment was performed for 5 minutes to gently deform the shoulder of the contact hole, N wiring 17 was formed.
In the above steps, even when P was used as an impurity for forming source and drain diffusion layers, it was possible to form a diffusion depth xi of 0.3 mm.

In addition, in other manufacturing steps, the process step of 8500010 minutes heat treatment → contact hole photo-etch → 850° C. 5 minutes heat treatment was changed to contact hole photo-etch → 850q010 minutes heat treatment, but there was no particular problem. In addition, the processing accuracy of the contact hole is Sj doped with Q and P.
Since the etching rate of the 02 film was slower than that of the P-doped Sj02 film, it was improved compared to the conventional case not containing Ge.

Further, the results obtained by using W-doped Satoshi G instead of snake-doped PSG were also good, and there were no particular problems. Here, S
Although the application to the i-gate MOS process was explained,
The present invention is not limited to this embodiment, but can be applied to any material that is not adversely affected by heat treatment of about 800 qo, and has a wider range of applications than conventional flattening treatment (glass flow).

FIG. 6 is an example in which the present technology is applied to isolation between elements of a MOS type integrated circuit.

Approximately 15 m thick of nitride film 22 (not limited to nitride film, all normal insulating films can be applied) on the surface of P-type Si 21 with a resistivity of 100.
The nitride film was formed and then photoetched to leave only a predetermined portion and remove the nitride film from other portions.

Furthermore, using this as a mask, the Sj substrate was selectively etched to a depth of about 1 mm. After this, approximately 10 m of Si02 film 23 is formed on the Si surface after oxidation and etching removal.
was formed. After this, for Si02, B2Q 7m
A Si02 film 24 doped with & and P was formed in a thickness of 1.5 m by the same method as in the previous example so that the Ce02 ratio was hol% (FIG. 1). After this, dryN2 middle school 1
Heat treatment at 000oC for 30 minutes to sufficiently fluidize Si0
After forming two films 24' (FIG. 2B), the entire surface was uniformly etched to form a buried layer 24'' of the snake-doped BSG film (FIG. 2C). After forming this buried layer 24'', normal processes were performed. A MOS type integrated circuit was manufactured. According to this method, isolation between elements can be formed using a more flat insulating film.
In addition, when heat-treating the moderately doped spots G in this example, B
By appropriately selecting the concentration of B, heat treatment temperature, base oxide film thickness, etc., a buried layer can be formed and at the same time B can be infiltrated into the Sj.
It is also possible to perform diffusion, and the ion implantation process into the field part and further the ion implantation process into the channel region can be omitted.

In addition, in the above embodiment, Si02 as well as Ce
Although P and B are exemplified as other impurities to be included in the 2. In addition, impurity elements such as As, Pb, and Zn, impurities such as phosphorus sulfide and halides, and the above-mentioned impurities are also included.
A similar effect was obtained even when more than one species was contained in Si02.

■Summary As explained above, according to the present invention, low temperature (10,000
0 or less) becomes possible, and it becomes possible to use it not only in MOS type integrated circuits but also in bipolar type integrated circuits.

Furthermore, reliability (corrosion of mountains), which has traditionally been a problem with glass flow, can also be improved because the concentration of other impurities such as P can be reduced.

[Brief explanation of the drawing]

Figures 1 and 2 are basic cross-sectional views showing the effects of the conventional method and the present invention in a glass flow of 1000q○, and Figures 3 and 4 are cross-sectional views of the upper and lower glass flows in a glass flow of 850°C. Similar cross-sectional views, FIGS. 5 and 6, show MOS-
It is an explanatory view when the present invention is applied to FET manufacturing. Ta'zu Tsutomu no zu Figure 3 Many elephants Evening wind Taku

Claims (1)

[Claims] 1. A step of providing a nitride film on a semiconductor substrate. A step of forming the nitride film into a desired shape by photo-etching. A step of etching the semiconductor substrate to a depth of about 1 μm using the nitride film as a mask. After the above etching, approximately 1
Step of forming 00nm silicon oxide film, B_2O
A step of forming a silicon oxide film containing about 7 mol% of _5 and about 20 mol% of GeO_2 to a thickness of about 1.5 μm by vapor phase growth. Heat treatment is performed at approximately 1000°C to planarize the silicon oxide film containing the impurities, and the entire surface is etched.
A method for manufacturing a semiconductor device, comprising: removing the silicon oxide film containing impurities until the nitride film is exposed.