GB2044533A - A semiconductor device and method of manufacturing same - Google Patents

A semiconductor device and method of manufacturing same Download PDF

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Publication number
GB2044533A
GB2044533A GB8007004A GB8007004A GB2044533A GB 2044533 A GB2044533 A GB 2044533A GB 8007004 A GB8007004 A GB 8007004A GB 8007004 A GB8007004 A GB 8007004A GB 2044533 A GB2044533 A GB 2044533A
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layer
phosphosilicate glass
integrated circuit
glass layer
over
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RCA Corp
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RCA Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition

Abstract

The semiconductor device includes a layer (30) which is impervious to steam and oxygen e.g. silicon nitride (Si3N4) beneath a phosphosilicate glass (PSG) layer (32). The presence of the nitride layer during the step of 'flowing' and any step of "reflowing" the glass prevents oxidation of underlying silicon regions thus enabling these steps to be carried out in an atmosphere containing steam, which in turn permits use of a PSG layer containing less than 7% phosphorous by weight to give improved reliability in devices where aluminium tracks (34) run over the glass, or permits the use of lower temperatures in the process. <IMAGE>

Description

SPECIFICATION A semiconductor device and method of manufacturing same The present invention relates to a composite semiconductor device and to the method of manufacturing such a device.
The use of a PSG layer, which is flowed over the surface of a semiconductor substrate during the manufacture of semiconductor devices, both before and after contact openings to the underlying doped semiconductor regions have been formed, has been known for several years in the semiconductor industry.
Such doped, contoured, glass layers are commonly known as "reflow layers" or "reflow glasses" because of the processes used in forming such layers and after such layers have been formed. In general, the reflow glasses heretofore used have been doped with from 7-10% phosphorus, by weight. Such glasses are generally deposited onto the surface of the substrate by chemical vapor deposition and flowed over the surface of the substrate in a furnace heated to between about 1 050 C and 1075"C into which phosphorus oxychloride (POC13) vapor is injected. During the flow step, the glass flows and sags into voids on the substrate to smooth the surface contour and round abrupt surface topologies.
As a result of the exposure to the POCi3, the outer layer of glass is generally very rich in phosphorus content. Hdretofore, the phosphorus rich outer layer has generally been removed by an etching step or by placing the substrate in boiling water.
Following the flow step, a photoresist layer is generally applied over the surface of the glass. The photoresist layer is then defined, and the glass is etched to form the contact openings resulting in steep walls having sharp edges at their top surface. In order to eliminate the sharp edges, a second flow step or 'reflow step" is performed to smooth the sharp edges and round the steep walls in order that any metal which is deposited on the surface of the substrate will overlie smooth contours rather than sharp edges. The reflow step is usually performed in a nonoxidizing atmosphere, such as nitrogen, at temperatures between about 1050"C and 1100"C for a time between about 1 and 10 minutes. Higher temperatures and/or longer times are required to adequately flow PSG layers having a lower phosphorus content.
It is suspected that certain types of aluminum corrosion, which result in long term reliability problems in integrated circuit devices having aluminum metallization, are caused by phosphoric acid formed by dissolved phosphorus oxide in condensed water vapor. Accordingly, it is desirable to reduce the phosphorus doping concentration in the PSG films to below 7%. Heretofore, however, any reduction in the phosphorus doping concentration to below 7% did not provide adequate topological contouring because the PSG layer or "film" would not adequately flow.
It has been known, though, that PSG films become more fluid in the presence of water vapor. However, it has not heretofore been possible to use steam to aid in reflowing the PSG because the contact surfaces are exposed during the reflow step, and steam would cause extensive reoxidation of the silicon substrate exposed through the contact openings.
In addition, any water vapor which permeated the doped glass or which reaches the silicon dioxide-silicon interface in the region of a MOS channel or field region could generate interface states which would be difficult to anneal out of the device. Accordingly, a method of making use of PSG films in which the percent of phosphorus, by weight, is less than 7%, has been desired.
The present invention relates to a method of providing PSG films having less than 7% phosphorus, by weight. Alternatively, the method can be employed in flowing PSG layers having more than 7% phosphorus, but with the flow being accomplished at lower temperatures. In accordance with the present invention, a silicon nitride layer is deposited over the surface of the semiconductor substrate prior to the deposition of the PSG film.
The silicon nitride layer presents an impervious barrier to steam and prevents the oxidation of underlying semiconductor areas. Accordingly, a PSG film having a phosphorus content of less than 7%, by weight, can be applied over the surface of the silicon nitride layer and can be flowed with the aid of steam without allowing water vapor to penetrate to the silicon-silicon dioxide interface. Thus, the formation of adverse surface states and oxidation of the exposed silicon is prevented.
In addition to the advantages enumerated above, experimental results have shown that an additional synergistic advantage of providing a silicon nitride film beneath the PSG film relates to the fact that PSG films tend to have defects which lead to shorts between the aluminum metallization over them and the underlying substrate. The silicon nitride film underlying the PSG film prevents such shorts from occurring.
Another synergistic advantage which has been observed is that steam leaches the outer surface of the PSG film reducing the phosphous content thereby further reducing the possibility of a corrosion problem.
In the Drawing: Figure 1 is a cross-sectional view of an integrated circuit device constructed in accordance with the present invention; Figures 2-5 are cross-sectional views illustrating the manner of manufacturing the integrated circuit device of Fig. 1.
Referring now to Fig. 1, a portion of an integrated circuit structure 10 is shown. The portion 10 comprises a metal oxide semiconductor (MOS) insulated gate field effect trans istor (IGFET) 12 manufactured in accordance with the present invention. The IGFET 12 comprises a body of semiconductor material 14, which is N- silicon in the preferred embodiment of the invention. Formed within the body 14 is a P + source 16 and a P + drain 18 each of which extend to a surface 20 of the body 14. A channel insulator 22 is formed on the surface 20 and extends between the source 16 and the drain 18. In the preferred embodiment of the invention, the channel insulator 22 is comprised of silicon dioxide and which is hereinafter called the channel oxide 22.However, materials other than silicon dioxide or composites, such as a silicon nitride and silicon dioxide composite may be used as the channel insulator. The channel oxide 22 overlies the channel region 24 which extends from the source 16 to the drain 18. Other oxide regions 26 overlie the surface 20 in the "field region" of the device 12.
As used herein, the term "field region" means the area of the integrated circuit 10 outside of the area wherein an IGFET 12 is formed, and the term "active region" means the area of the integrated circuit 10 in which an IFGET 12 is formed. The term "active region" is also meant to include the contact regions for any non-MOS device incorporated on the integrated circuit.
Overlying the channel oxide 22 is a metal gate 28, which is comprised of aluminum in the preferred embodiment of the invention, but which may comprise other metals or metallization systems, such as "trimetal", i.e.
titanium, platinum and gold. Overlying the field oxide 26 is a composite layer comprising a layer of silicon nitride 30 with a layer of phosphosilicate glass (PSG) 32 formed thereon.
Metallic interconnects 34, which are comprised of aluminum in the preferred embodiment of the invention, overlie the PSG layer 32. The PSG layer 32 has smoothly contoured edges 36 as compared to the sharp edges 38 of the underlying silicon nitride layer 30. Accordingly, the metallic interconnects 34 are applied over the smoothly contoured topologies of the PSG layer 32 rather than the abrupt steps of the silicon nitride layer 30. Finally, a thick protective oxide layer 40, which may be about 80008. thick, and which has bond pad openings 42 formed therein, covers the surface of the integrated circuit 10.
Figs. 2-5 illustrate the preferred embodiment of the method of manufacturing the present invention. For convenience, the crosssections in Figs. 2-5 show only the configuration in the plane of the cross-section.
In the preferred embodiment of the invention, the process begins with a semiconductor body 14 of (100) silicon having N- conductivity type in which a P + source 16 and a P + drain 18 are formed by any conventional manner well known in the semiconductor art.
For example, an oxide may be thermally grown on the surface 20 of the body 14 which oxide may then have a layer of photoresist applied thereon. The photoresist may then be defined and developed and used as an etch mask to remove exposed portions of the oxide layer from the surface 20. The oxide layer may then be used as a diffusion mask in a conventional diffusion process. Thereafter, the oxide can be stripped and a new layer of oxide 26 can be thermally grown on the surface 20 in order to obtain the structure shown in Fig. 2.
With reference now to Fig. 3, contact openings 21, 23 are defined and formed in the oxide layer 26 over the source 16 and drain 18, respectively. The formation of the contact openings 21, 23 separates the portion of the oxide layer 26 between the source 16 and the drain 18 from the remaining portions of the oxide layer 26. Accordingly, hereafter the portion of the oxide layer 26 between the source 16 and drain 18 will be referred to as the channel oxide 22 and the remaining portions of the oxide layer 26 will be referred to as the field oxide.
Next, the silicon nitride (Si3N4) layer 30 is deposited over the surface of the partially formed structure 10. The silicon nitride layer 30 may be deposited in any desired manner, such as by the reaction of silane and ammonia which takes place at about 800 C. The reaction is continued until the silicon nitride layer 30 has a thickness of about 600A. The silicon nitride layer 30 provides an impervious barrier on the surface of the integrated circuit 10 which prevents oxidation of the source and drain regions 16, 18, which were exposed when the contact openings 21, 23 were formed. As will be seen, those portions of the silicon nitride layer 30 which overlie the field regions of the integrated circuit 10 will not be removed in order that the integrated circuit 10 is provided with a hermetic seal over its surface. The process thus provides an integrated circuit which has long term reliability.
Those portions of the silicon nitride layer 30 which overlie active regions of the integrated circuit 10 will be removed in the course of processing in order that the channel insulator 22 will be comprised solely of a single layer of silicon dioxide. A composite silicon dioxidesilicon nitride channel insulator is generally not desirable unless one is making a memory device such as a metal nitride oxide semiconductor (MNOS) device, because the silicon nitride-silicon dioxide composite in the channel region tends to store charge which makes the device unreliable over long time periods. Of course, when one is intential!y manufacturing an MNOS device means are provided for adding and removing such additional charges at the silicon nitride-silicon dioxide interface.
Following the deposition of the silicon nitride layer 30, a PSG layer 32 having a phosphorus concentration between about 5% and 7% by weight is deposited on the surface of the silicon nitride layer 30 at a temperature of about 400 C. The PSG layer 32 is preferably deposited by the reaction which takes place between silane and phosphine. Following the deposition of the PSG layer 32, openings 33 as shown in Fig. 4 are formed in the PSG layer 32 over active regions of the integrated circuit device 10.
The openings 33 are preferably formed in the PSG layer 32 by etching the PSG layer 32 using buffered hydrofluoric acid after the openings 33 are defined using a conventional photolithographic step. The hydrofluoric acid etch will essentially stop when the silicon nitride layer 30 is reached.
Following the etch of the PSG layer 32, the structure will include sharp edges where the openings 33 have been formed throughout the PSG layer 32. In order to remove the sharp edges from the PSG layer 32 and to improve the topology of the surface of the integrated circuit structure 10, the PSG layer 32 is heated to about 1050 C for about 15 minutes in an atmosphere containing steam.
During this step, the PSG layer 32 "flows" resulting in the smoothly contoured edges 36 (shown in Fig. 5) to which metal may be applied. It is only possible to use less than 7% phosphorus in the PSG layer 32 and still achieve adequate "flow" with relatively short time exposures at 1050 C because of the presence of the steam in the atmosphere.
It is only possible to use steam in the atmosphere because of the prsence of the impervious silicon nitride layer 30 which prevents the thermal oxidation of the source and drain regions 16, 18 exposed through the contact openings 21, 23. Furthermore, the existing channel oxide 22 is protected from additional oxidation by the silicon nitride layer 30. Thus, the present invention provides a process by which a steam atmosphere may be used to flow a PSG layer 32 which contains an adequate amount of phosphorus for flow and getter purposes but which does not contain so much phosphorus that long term reliability problems such as "black metal" problems will be created. An additional advantage of the steam flow of the PSG layer 32 is that impurities on the upper surface of the layer 32 are leached out during the steam aided flow.
Following the steam aided flow step, the furnace is flushed with nitrogen for about 5 minutes after which the body 14 is pulled into a so-called "white elephant", a tube at the end of the furnace, in which the body 14 is cooled in a nitrogen atmosphere.
Following the removal of the body 14 from the furnace, the portions of the silicon nitride layer 30 lying within the opening 33 are removed by placing the body 14 into an etch solution comprising a mixture of phosphoric acid (H3PO4) into which there is mixed 10% or less sulfuric acid (H2SO4), which mixture is heated to about 106 C for a time sufficient to extend the contact openings 33 through to the surface 20 and to the gate oxide 22.
Next, an optional anneal may be performed in forming gas, a mixture of hydrogen and nitrogen, at about 740 C for 1#6 hours. Following the forming gas anneal, the body 14 may be dipped into a buffered hydrofluoric acid to remove any oxide which may have formed on the surface 20.
Next, a layer of metal 34, such as aluminum, is evaporated over the surface of the device 12 to obtain the structure shown in Fig. 5. Using a photolithographic process, the metal layer 34 is defined to form interconnects which connect the various IGFETs on the integrated circuit 10. Then, the protective oxide layer 40, having a thickness of about 10,000 , is formed over the surface of the entire integrated circuit 10, and bond pad openings 42 are defined and formed in the protective oxide layer 40 by a photolithographic process. The method of forming the passivating oxide (Si3N4) and of the bond pad openings are well known in the art and are not shown in the figures.
While the preferred embodiment of the invention has been described with reference to the method of manufacturing an aluminum gate MOS integrated circuit 10, it should be recognized that alterations to the preferred embodiment may be accomplished without departing from the spirit or scope of the invention. For example, the invention may be employed with NMOS, CMOS, or bipoloar technologies.
While the present invention has been discussed with regard to the advantages which it provides in allowing a PSG layer with reduced phosphorus content to be flowed, it would be obvious to those skilled in the art that while the presence of steam acts to reduce the phosphorus content required to flow a PSG layer at a given temperature, it also acts to lower the temperature at which PSG layer with a given phosphorus content will flow.
Accordingly, the present invention is also useful in the manufacture of radiation hardened integrated circuits in which the temperature at which the integrated circuits are manufactured is kept as low as possible. Accordingly, radiation hardened integrated circuits can have a flowed PSG layer which is flowed at a temper- ature less than 1000 C by providing the PSG layer with a sufficient amount of phosphorus to enable it to flow at a lower temperature in the presence of steam. For example, a PSG layer containing 110% phosphorus by weight can be flowed at about 950 C. While the 10% phosphorus content is higher than the content heretofore discussed, the invention provides a flowed PSG layer at the low temperature required for the processing of radio: tion hardened integrated circuits. Also, PSG layers can be provided on bipolar integrated circuits where they can be flowed at relatively low temperatures to avoid undesired lateral diffusions.

Claims (9)

1. A method of producing an integrated circuit device of the type comprising a substrate of semiconductor material having semiconductor devices with active regions and field regions formed therein, comprising the steps of covering said substrate with an insulating layer, forming contact openings through said insulating layer, applying an impervious layer over said insulating layer, applying a phosphosilicate glass layer over said impervious layer, removing the portions of said phosphosilicate glass layer which extend over active regions of said devices, heating said phosphosilicate glass layer in the presence of steam at a temperature sufficient to cause the edges of said phosphosilicate glass layer to become rounded, removing the portions of said impervious layer which extend over active regions of said devices, and applying a metal layer over the surface of said phosphosilicate glass layer, whereby said metal layer will extend through said openings to make electrical contact to underlying portions of the semiconductor material in said active regions of said devices.
2. A method as claimed in claim 1, in which said phosphosilicate glass layer contains more than about 7% phosphorus by weight and said step of heating is conducted at less than about 1000 C.
3. A method as claimed in claim 1, wherein said phosphosilicate glass layer contains less than about 7% phosphorus by weight and said step of heating takes place at a temperature greater than about 950 C.
4. A method as claimed in claim 1, 2 or 3, wherein the step of applying an impervious layer comprises the deposition of silicon nitride.
5. An integrated circuit device of the type comprising a body of semiconductor material having active regions and field regions formed therein, comprising an impervious layer formed over the surface of the field regions of said integrated circuit device, a phosphosilicate glass layer formed over said impervious layer in said field regions and over said semi conductor devices in the active regions of the integrated circuit, openings which extend through said phosphosilicate glass layer and through said impervious layer to the underly ing semiconductor devices in the active regions of said integrated circuit, the upper edges of said openings in said phosphosilicate glass layer being rounded, and a metal layer overlying said phosphosilicate glass layer, said metal layer extending over said rounded edges through said openings to electrically contact the active regions which underlie any portion of said openings.
6. A device as claimed in claim 5, wherein said impervious layer is comprised of silicon nitride.
7. A device as claimed in claim 5, wherein said phosphosilicate glass layer contains less than 7% phosphorus by weight.
8. A method of producing an integrated circuit device as claimed in claim 1, substantially as described by way of example herein.
9. An integrated circuit device substantially as hereinbefore described with reference to the accompanying drawings.
GB8007004A 1979-03-05 1980-02-29 Semiconductor device and method of manufactguring same Expired GB2044533B (en)

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DE (1) DE3007500A1 (en)
FR (1) FR2451103A1 (en)
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IT (1) IT1140645B (en)
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EP0068846A1 (en) * 1981-06-26 1983-01-05 Fujitsu Limited Forming a pattern of metal elements on a substrate
EP0081226A2 (en) * 1981-12-08 1983-06-15 Matsushita Electronics Corporation Method of making semiconductor device
US4443493A (en) * 1980-04-28 1984-04-17 Fairchild Camera And Instrument Corp. Laser induced flow glass materials
US4542037A (en) * 1980-04-28 1985-09-17 Fairchild Camera And Instrument Corporation Laser induced flow of glass bonded materials
EP0200372A2 (en) * 1985-04-02 1986-11-05 THORN EMI North America Inc. Self-aligned contact window formation in an integrated circuit

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Publication number Priority date Publication date Assignee Title
DE3130666A1 (en) * 1981-08-03 1983-02-17 Siemens AG, 1000 Berlin und 8000 München Method for fabricating integrated MOS field effect transistors having a phosphosilicate glass layer as an intermediary oxide layer
DE3131050A1 (en) * 1981-08-05 1983-02-24 Siemens AG, 1000 Berlin und 8000 München Process for fabricating integrated MOS field effect transistors, employing a surface layer consisting of phosphosilicate glass on the intermediary oxide between polysilicon plane and metal conductor track plane
DE3133516A1 (en) * 1981-08-25 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Process for rounding the intermediary oxide between the polysilicon plane and metal conductor track plane when fabricating integrated n-type channel MOS field-effect transistors
JPH088246A (en) * 1994-06-21 1996-01-12 Nippon Motorola Ltd Method for forming metal wiring of semiconductor device

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US3627598A (en) * 1970-02-05 1971-12-14 Fairchild Camera Instr Co Nitride passivation of mesa transistors by phosphovapox lifting
US3917495A (en) * 1970-06-01 1975-11-04 Gen Electric Method of making improved planar devices including oxide-nitride composite layer
US3943621A (en) * 1974-03-25 1976-03-16 General Electric Company Semiconductor device and method of manufacture therefor
US4005240A (en) * 1975-03-10 1977-01-25 Aeronutronic Ford Corporation Germanium device passivation
US4273805A (en) * 1978-06-19 1981-06-16 Rca Corporation Passivating composite for a semiconductor device comprising a silicon nitride (Si1 3N4) layer and phosphosilicate glass (PSG) layer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4443493A (en) * 1980-04-28 1984-04-17 Fairchild Camera And Instrument Corp. Laser induced flow glass materials
US4542037A (en) * 1980-04-28 1985-09-17 Fairchild Camera And Instrument Corporation Laser induced flow of glass bonded materials
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Also Published As

Publication number Publication date
IT8020023A1 (en) 1981-08-19
IT1140645B (en) 1986-10-01
YU61180A (en) 1983-02-28
JPS55121669A (en) 1980-09-18
NL8001310A (en) 1980-09-09
IT8020023A0 (en) 1980-02-19
FR2451103A1 (en) 1980-10-03
GB2044533B (en) 1983-12-14
DE3007500A1 (en) 1980-09-18

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