DE3131050A1 - Process for fabricating integrated MOS field effect transistors, employing a surface layer consisting of phosphosilicate glass on the intermediary oxide between polysilicon plane and metal conductor track plane - Google Patents

Abstract

The invention relates to a process for fabricating integrated MOS field effect transistors, which involves rounding the edges and borders on the surface steps or in the contact hole zones (6) of the intermediary oxide (3) between the polysilicon plane (2) and the metal conductor track plane with the aid of a surface layer (4) consisting of phosphosilicate glass by planarisation of this layer (4), before the metal conductor track plane is generated. In the process, planarisation of the layer (3) having a phosphorus content </= 6% by weight and the layer (4) is carried out at </= 900 DEG C in conjunction with densification of the intermediary oxide (3), the surface layer (4) is removed without changing the surface topology, and only then is the photoresist technique (7) for opening the contact holes (6) carried out. The process is used in the fabrication of complementary MOS field effect transistor circuits (CMOS-FETs). <IMAGE>

Description

Process for producing integrated MOS field effect

transistors using one made of phosphosilicate glass Surface layer on the intermediate oxide between the polysilicon level and the Netall conductor track level.

The present patent application relates to a method of manufacturing of integrated MOS field effect transistors, in particular of complementary MOS field effect transistor circuits (CMOS-FETs), in which the edges and edges on the surface steps or in the Contact hole areas of the intermediate oxide between the polysilicon level and the metal interconnect level with the help of a, at least partially consisting of phosphosilicate glass, on the Surface layer applied between oxide layer by allowing this to flow Layer must be rounded off before the metal conductor track level is created.

When manufacturing integrated semiconductor circuits on silicon substrates structural steps arise on the semiconductor surface, e.g. B. by polysilicon tracks, Over which aluminum conductor tracks are to be routed in a later process step. Polysilicon and aluminum conductor lines are separated from each other by an insulating layer (intermediate oxide) separated. At the structural levels, aluminum conductor tracks can be reduced in cross-section or even be interrupted entirely.

To avoid constrictions or tears in the aluminum conductor tracks, a phosphosilicate glass with z. B. 8 mole% P205 at e.g. B. 4500C deposited, which then at z. 3. 10000C in a phosphorus oxychloride atmosphere is made to flow (so-called Reflow process). This will be Sharp-edged structural steps rounded or cavities filled with phosphosilicate glass.

There are some major problems associated with the reflow process: 1. In a subsequent photolithography step, there may be adhesion problems on the Phosphosilicate glass layer come.

2. In the presence of Moisture forms a phosphoric acid, which corrodes the aluminum conductor tracks can lead.

3. Due to the temperature load during the reflow process (1000 ° C) you can the electrical properties of the integrated circuits are considerably disadvantageous change.

In order to avoid some of these problems, DE-OS 3 007 500 a method of the type mentioned is proposed in which the reflow process of phosphosilicate glass layers with phosphorus concentrations of z. B.

10% by weight (that is approx. 11 mol-OÄ P205) in a steam atmosphere at z. B. 9500C- is carried out. Phosphosilicate glass layers flow in this atmosphere easily and at the same time phosphorus is depleted on the surface. To an undesirable Oxidizing exposed single-crystal silicon areas (contact hole areas) to is avoided in the process known from DE-OS 3 007 500 as a water vapor barrier a silicon nitride layer is used under the phosphosilicate glass layer.

The object on which the invention is based consists in the Manufacture of integrated MOS field effect transistor circuits in which the advantage the phosphosilicate glass layer for a favorable edge covering of the intermediate oxide is used in the area of the contact holes, but at which temperatures of greater 9000 c and too high a phosphorus content can be avoided and when for opening the contact holes a reliable photoresist technique can be carried out.

According to the invention, this object is achieved by the following process steps solved with the passivation of the integrated MOS field effect transistor circuits: a) the flowing of the on the intermediate oxide layer with a concentration of phosphorus of C 6 wt.% applied phosphorus silicate glass layer is at temperatures in Carried out in the range of c 9000C, with the intermediate oxide compacted at the same time becomes, b) the phosphosilicate glass layer becomes without changing the surface topology removed from the intermediate oxide layer, c) only then is the photoresist technology for the opening of the contact holes to the polysilicon tracks and the active transistor areas carried out and d) generated the metal conductor track level.

It is within the scope of the inventive concept that in modification of the The process steps just listed are applied to the phosphosilicate glass layer freed intermediate oxide layer a layer consisting of SiO2, preferably in one Layer thickness of 100 nm, is deposited at temperatures # 5000C. This lets aluminum corrosion, which has already been reduced due to the lower phosphorus content decrease even further.

In addition, the adhesion of the photoresist, in particular at a later exposure to a plasma etching process.

The reason for the good flow at relatively low temperatures and phosphorus concentrations is the summary of the compaction of the-applied Intermediate oxide layer and the reflow process even before the photoresist technology Opening the contact hole areas. It also ensures that the low Temperature of 900 ° C during the reflow process, vertical and lateral diffusion depths and implantation profiles are not influenced.

In a further development of the inventive concept, it is also provided that removing the phosphosilicate glass layer without changing the surface topology by treatment in an etching mixture consisting of fluorides and phosphates of Make ammonium salts.

The phosphorus concentration in the deposited intermediate oxide layer can be selected as desired, from 0 wt.% up to 6 wt.%. It is advisable adjust the phosphorus concentration in the intermediate oxide to 4 wt. To achieve a sufficient Ensure the reliability of the components (use of voltage stability).

The following is based on an exemplary embodiment and the figures 1 to 5, which show the process steps essential to the invention in sectional images, the invention described in more detail.

Figure 1: After the production of the intended for the integrated circuit Transistor structures (not shown) in the silicon substrate 1 and the polysilicon tracks 2 becomes the intermediate oxide 3 by thermal decomposition of one of silane and hydrogen phosphide exist- the gas atmosphere at a pressure of 2.6.10 # 3N / m2 (0.2 Torr) at 4300C in a thickness of 600 nm with a content of phosphorus of 4% by weight upset.

This oxide (3) has transitions and wrinkles that are too high after deposition for safe aluminum metallization. Therefore a reflow process is carried out, wherein, as can be seen from Figure 2, the surface of, the substrate 1 and the Intermediate oxide 3 covering polysilicon track 2 by deposition of phosphorus pentoxide (P205) from phosphorus oxychloride (POCl3) at 9000C (80 min) with a highly doped Phosphosilicate glass layer 4 is covered.

Immediately afterwards there is a compression of the intermediate oxide at 9000C 3 carried out in a nitrogen atmosphere (20 min), with the overhangs at the same time and folds in the region (4) of the intermediate oxide layer 3 close to the surface of about 100 nm are eliminated by the phosphor glass layer (4) (see Figure 2).

The uppermost area (4) of the intermediate oxide 3 with the high phosphorus content is then peeled off to ensure good adhesion of the photoresist to be applied later is guaranteed and corrosion of the aluminum conductor track level is avoided. In this detachment of the layer 4, it is important that what is obtained by the flowing Surface profile is retained. A low selectivity of 2 between the Phosphosilicate glass layer 4 and the intermediate oxide 3 underneath it is obtained if an ammonium ions, fluorine ions and phosphate ions (ammonium dihydro genpho sphat) containing mixture is used. The arrangement is created after the etching according to Figure 3, from which a very good edge coverage with a coverage angle rv 90 and a coverage ratio of d00 ~ 65.

In order to improve the photoresist adhesion even further, the in Figure 3 shown arrangement an undoped another SiO2 layer 5 in a layer thickness of z. B.

100 nm at 4300C by thermal decomposition of silane in an oxygen atmosphere applied at 2.6.10 3 NIm2 (0.2 Torr). The result is that shown in FIG Arrangement.

The further course of the process for opening the contact holes 6 happens as can be seen from FIG. 5, in a known manner by means of a photo mask technique (7) by means of plasma etching. Overhangs in the contact hole etching are avoided, that densification of the undoped SiO2 layer 5 is dispensed with.

The method according to the teaching of the invention is particularly suitable for the production of complementary integrated MOS field effect transistors (CMOS), because avoided by the reflow process carried out before the contact hole etching becomes that p + regions (S / D of the p-channel transistors) are depleted of boron.

7 claims 5 figures

Claims (7)

Patent applications. Process for the production of integrated MOS field effect transistors, in particular of complementary MOS field effect transistor circuits (CMOS-FETs), in which the edges and rims on the surface steps or in the contact hole areas of the intermediate oxide between the polysilicon level and the metal interconnect level with the help of a, at least partially consisting of phosphosilicate glass, on the Surface layer applied between oxide layer by allowing this to flow Layer are rounded off before the metal conductor track plane is generated, d a d u r c h e k e n n -z e i c h n e t that a flowing of the on the intermediate oxide layer (3) Phosphosilicate glass layer applied with a phosphorus concentration of 6% total (4) is carried out at temperatures in the range of # 9000C, with simultaneous the intermediate oxide (3) is compressed, b) the phosphosilicate glass layer (4) without Change in the surface topology of the intermediate oxide layer (3) is removed, c) only then the photoresist technology (7) for the opening of the contact holes (6) to the Polysilicon tracks and the alrtiven transistor areas (1) is carried out and d) the metal conductor track level is generated. 2. The method according to claim 1, d a d u r c h g e -k e n n z e i c h n e t that in the modification of the method before method step c) to that of The intermediate oxide layer (3) freed from the phosphor glass layer (4) consists of SiO2 Layer (5) is deposited at temperatures c 5000C. 3. The method according to claim 2, d a d u r c h g e -k e n n z e i c h n e t that the layer thickness of the additionally applied SiO2 layer (5) is approx. 100 nm is set. 4. The method according to claim 1 to 3, d a d u r c h g e k e n n z e i c h n e t that the generation of the. Phosphosilicate glass layer (4) by covering the surface (3) with Phosphorus pentoxide (P205) is made from phosphorus oxychloride (P0Cl3) at 9000C. 5. The method according to claim 1 to 4, d a d u r c h g e k e n n z e i c h n e t that the flow process for the Phosphorsilik'atglasschicht (4) and the Compression process for the intermediate oxide (3) in a nitrogen or argon atmosphere performed at 9000C. 6. The method according to claim 1 to 5, d a d u r c h g e k e n n z e i c h n e t that the phosphosilicate glass layer (4) by treatment in an ammonium (NH4 +) -, fluorine (F-) - and phosphate (P04) -ions containing etching mixture removed will. 7. The method according to claim 1 to 6, d a d u r c h g e k e n n z e i c h n e t that the intermediate oxide (3) with a phosphorus concentration in the range from 0 to 6% by weight through thermal decomposition of silane (SiH4) and hydrogen phosphide (PH3) is deposited at a pressure of 2.6.10-3N / m2 (0.2 Torr) at 430 ° C.