JPS5826177B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5826177B2 JPS5826177B2 JP54081126A JP8112679A JPS5826177B2 JP S5826177 B2 JPS5826177 B2 JP S5826177B2 JP 54081126 A JP54081126 A JP 54081126A JP 8112679 A JP8112679 A JP 8112679A JP S5826177 B2 JPS5826177 B2 JP S5826177B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- silicon layer
- semiconductor device
- impurities
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 37
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 56
- 238000009792 diffusion process Methods 0.000 description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 Phosphorus ions Chemical class 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、高比抵抗の抵抗体を有する半導体装置の製造
方法に係り、特に半導体基体内に形成された高濃度に不
純物を拡散された多結晶シリコン層に接触された高比抵
抗の多結晶シリコン層からなる抵抗体を有する半導体装
置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a resistor having a high specific resistance, and particularly relates to a method for manufacturing a semiconductor device having a resistor having a high resistivity, and particularly relates to a method for manufacturing a semiconductor device having a resistor having a high specific resistance, and in particular a semiconductor device that is in contact with a polycrystalline silicon layer formed in a semiconductor substrate and doped with impurities at a high concentration. The present invention relates to a method of manufacturing a semiconductor device having a resistor made of a polycrystalline silicon layer with high specific resistance.
従来、インバータ回路や基準電位発生回路等は、例えば
、駆動ＭＯ８（Ｍｅｔａｌ ０ｘｉｄｅ Ｓｅｍ１ｃ
−ｏｎｄｕｃｔｏｒ））ランジスタにＭＯＳ）ランジス
タからなる負荷素子、或いは、高比抵抗の拡散層で形成
された負荷抵抗素子を接触して構成されたものが用いら
れている。Conventionally, inverter circuits, reference potential generation circuits, etc.
A load element consisting of a -inductor) transistor and a MOS) transistor, or a load resistance element formed of a high resistivity diffusion layer is used.
しかしながら、負荷素子としてＭＯＳ）ランジスタを用
いて第１図に示す如き、いわゆるＥ／Ｄインバータ回路
を形成したものでは、ＭＯＳ）ランジスタの相互コンダ
クタンスが比較的大きいため、ＭＯＳ集積回路の低消費
電力化の為に相互コンダクタンスを下げようとすると、
負荷素子として使用するＭＯＳトランジスタのチャネル
長が長くなり、高密度化を図ることができない欠点があ
った。However, in the case where a so-called E/D inverter circuit as shown in Fig. 1 is formed using a MOS transistor as a load element, the mutual conductance of the MOS transistor is relatively large, so the power consumption of the MOS integrated circuit can be reduced. If you try to lower the mutual conductance for
This has the drawback that the channel length of the MOS transistor used as the load element becomes long, making it impossible to achieve high density.
この問題を解消するために、例えば、第２図及び第３図
に示す如く、フィールド酸化膜１の形成された半導体基
体２にその主面からソース拡散領域３及びドレイン拡散
領域４を形成し、この両拡散領域３，４間の露出表面に
ゲート酸化膜５を介してポリシリコンなどからなるゲー
ト電極６を形成すると共に、両拡散領域３，４に配線金
属７を取付けたいわゆる駆動ＭＯ８）ランジスタを形成
し、更に、フィールド酸化膜１の表面に負荷抵抗素子の
機能を果すポリシリコンからなる高比抵抗の低濃度層９
を形成し、マスク層（例えば、気相成長法で形成された
抵温酸化膜を写真蝕刻法でパターニングしたもの）１１
により熱拡散後高抵抗部分９ａと低抵抗部分９６に分離
し、更に、電極取出部を除いて保護層１０を形成すると
共に、この電極取出部とドレイン拡散領域４とを金属配
線で接続した第４図に示す如き、インバータ回路が考え
出されている。In order to solve this problem, for example, as shown in FIGS. 2 and 3, a source diffusion region 3 and a drain diffusion region 4 are formed from the main surface of a semiconductor substrate 2 on which a field oxide film 1 is formed, A gate electrode 6 made of polysilicon or the like is formed on the exposed surface between the two diffusion regions 3 and 4 via a gate oxide film 5, and a wiring metal 7 is attached to both the diffusion regions 3 and 4 to form a so-called drive MO transistor. Furthermore, on the surface of the field oxide film 1, a high resistivity low concentration layer 9 made of polysilicon that functions as a load resistance element is formed.
A mask layer (for example, a low-temperature oxide film formed by vapor phase growth and patterned by photolithography) 11
After thermal diffusion, the high-resistance portion 9a and the low-resistance portion 96 are separated, and a protective layer 10 is formed except for the electrode extraction portion, and the electrode extraction portion and the drain diffusion region 4 are connected by metal wiring. An inverter circuit as shown in FIG. 4 has been devised.
このように高比抵抗の低濃度層９からなる負荷抵抗体を
有する半導体装置で構成されたインバータ回路は、負荷
素子としてＭＯＳトランジスタを用いたものに比べて遥
かに小型化されたが、完全に高密度化が達成されたわけ
ではなかった。In this way, an inverter circuit configured with a semiconductor device having a load resistor consisting of a low concentration layer 9 with high specific resistance is much smaller than one using a MOS transistor as a load element, but it is completely Densification was not achieved.
その理由は、例えば、低濃度高比抵抗の多結晶シリコン
からなる低濃度層９を高濃度部（低抵抗部）９ｂと低濃
度部（高比抵抗部）９ａが分離し、この低濃度部９ａの
長さを定めるためにマスク層１１を形成後、熱拡散法に
よる不純物拡散を行う際に、熱拡散によってマスク層１
１に覆われた部分に不純物が拡散して低濃度部９ａの高
比抵抗が失われるため、この不純物の拡散層（約１０μ
報度）だけを予め考慮に入れてマスク層１１の長さつま
り低濃度層９の長さを長くしておく必要があるからであ
る。The reason for this is, for example, that the low concentration layer 9 made of polycrystalline silicon with low concentration and high specific resistance is separated into a high concentration area (low resistance area) 9b and a low concentration area (high specific resistance area) 9a, and this low concentration area After forming the mask layer 11 to determine the length of the mask layer 9a, when performing impurity diffusion by thermal diffusion, the mask layer 11 is
The impurity is diffused into the portion covered with 1 and the high resistivity of the low concentration portion 9a is lost.
This is because it is necessary to increase the length of the mask layer 11, that is, the length of the low concentration layer 9, by taking into consideration only the amount of energy (intensity) in advance.
また、このようにして製造されたインバータ回路等では
、負荷抵抗体の抵抗値のばらつきが大きい等の欠点があ
った。Furthermore, inverter circuits and the like manufactured in this manner have drawbacks such as large variations in the resistance values of the load resistors.
本発明は、かかる点に鑑み種々の研究を行った結果、高
比抵抗の低濃度層の少なくとも一端部を駆動トランジス
タのすでに形成された拡散層に接続する高濃度に不純物
を拡散された多結晶シリコン層に直接接触することによ
り高密度化及び電気特性の向上を図った半導体装置の製
造方法を提供し従来の欠点を解消するものである。As a result of various studies conducted in view of the above points, the present invention provides a polycrystalline material in which impurities are diffused in a high concentration to connect at least one end of a low concentration layer with high resistivity to an already formed diffusion layer of a drive transistor. The present invention provides a method for manufacturing a semiconductor device that achieves higher density and improved electrical characteristics by directly contacting a silicon layer, thereby eliminating the drawbacks of the conventional method.
以下、本発明の実施例を図面を参照して詳細に説明する
。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第５図Ｅ及び第６図は、本発明方法にて製造される半導
体装置の一実施例を示すものである。FIGS. 5E and 6 show an embodiment of a semiconductor device manufactured by the method of the present invention.
この半導体装置は、フィールド酸化膜２０の形成された
半導体基体２１に、その主面から延在するソース拡散領
域（例えば、ソース拡散領域の濃度が１０１９〜１０２
１個／ｄ程度）２２及びドレイン拡散領域（例えば、ド
レイン拡散領域の濃度が１０１９〜１０２１個／ｃｒＡ
程度）２３を形成すると共に、この両拡散領域２２，２
３間の露出表面にゲート酸化層２４を介して高濃度に不
純物を拡散された多結晶シリコン層のゲート電極２５ａ
を形成し、且つ、フィールド酸化膜２０の表面に一端部
がドレイン拡散領域２３に直接接触された高濃度に不純
物を拡散された多結晶シリコン層２５ｂを形成し更にこ
れらと少くともその一端が前記高濃度に不純物を拡散さ
れた多結晶シリコン層２５ｂに直接接触された低濃度層
（例えば低濃度層の濃度が５Ｘ １０１７個／１）２６
をシリコン酸化層２７を介して設け、ゲート電極（例え
ば後述する多結晶シリコンからなる低濃度層２６を第２
多結晶シリコン層とした場合に、第１多結晶シリコン層
となるこのゲート電極の濃度１０１９〜１０２１個／Ｃ
ｒ１ｌ）２５及び低濃度層２６の表面に配線金属２８の
取出し部を除いてシリコン酸化膜２９を被着し、更にそ
の表面に保護膜３０を形成したものである。This semiconductor device has a source diffusion region (for example, a concentration of 1019 to 102
1 piece/d) 22 and the drain diffusion region (for example, the concentration of the drain diffusion region is 1019 to 1021 pieces/crA)
degree) 23, and both diffusion regions 22, 2
A gate electrode 25a of a polycrystalline silicon layer in which impurities are diffused at a high concentration through a gate oxide layer 24 on the exposed surface between 3 and 3.
A highly doped polycrystalline silicon layer 25b having one end directly in contact with the drain diffusion region 23 is formed on the surface of the field oxide film 20, and furthermore, at least one end thereof is in contact with the drain diffusion region 23. A low concentration layer (for example, the concentration of the low concentration layer is 5X 1017 pieces/1) 26 that is in direct contact with the polycrystalline silicon layer 25b into which impurities are diffused at a high concentration.
is provided via a silicon oxide layer 27, and a gate electrode (for example, a low concentration layer 26 made of polycrystalline silicon, which will be described later) is provided as a second layer.
In the case of a polycrystalline silicon layer, the concentration of this gate electrode, which becomes the first polycrystalline silicon layer, is 1019 to 1021 particles/C.
A silicon oxide film 29 is deposited on the surfaces of the r1l) 25 and the low concentration layer 26 except for the lead-out portion of the wiring metal 28, and a protective film 30 is further formed on the surface.
このように低濃度層２６の一端部を駆動ＭＯＳトランジ
スタのドレイン拡散領域２３に接続された高濃度に不純
物を拡散された多結晶シリコン層に直接接触して得られ
た半導体装置３１はインバータ回路を構成し、例えば第
５図Ａ乃至Ｅに示す如き工程に従って製造することがで
きる。In this way, the semiconductor device 31 obtained by directly contacting one end of the low concentration layer 26 with the polycrystalline silicon layer in which impurities are diffused at a high concentration and connected to the drain diffusion region 23 of the drive MOS transistor has an inverter circuit. It can be constructed and manufactured according to the steps shown in FIGS. 5A to 5E, for example.
まず、第５図Ａに示す如く、例えば、基板比抵抗２０Ω
・はのＰ型半導体基体２１の主面に、高温酸化により酸
化膜２１ａを形成し、更にこの酸化膜２１ａの表面に、
例えば、気相成長法により形成された窒化シリコン膜を
写真蝕刻法によって所望形状に形成されたレジスト２１
ｂをマスクにして、所望パターンの窒化シリコン膜２１
ｃを形成する。First, as shown in FIG. 5A, for example, the substrate specific resistance is 20Ω.
・An oxide film 21a is formed on the main surface of the P-type semiconductor substrate 21 by high temperature oxidation, and further, on the surface of this oxide film 21a,
For example, a resist 21 is formed by photo-etching a silicon nitride film formed by vapor phase growth into a desired shape.
Using b as a mask, silicon nitride film 21 is formed into a desired pattern.
form c.
次いで、このレジス）２１ｂを載置した窒化シリコン膜
２１ｃをマスクにして加速電圧１２０ ｋＶ、注入量２
Ｘ １０１３／ｃｒ？ｔの条件でボロン■のイオン注
入を行って半導体基体２１の反転防止を施した後、高温
酸化により厚さ約１μのフィールド酸化膜２０を形成す
ると共に、窒化シリコン膜２１ｃ及びその直下の酸化膜
２１ａを除去してから高温酸化により４００〜１０００
λ程度のゲート酸化膜２４を形成する。Next, using the silicon nitride film 21c on which the resist 21b is placed as a mask, an acceleration voltage of 120 kV and an implantation amount of 2 are applied.
X 1013/cr? After boron ion implantation is performed under the conditions of t to prevent the semiconductor substrate 21 from being inverted, a field oxide film 20 with a thickness of approximately 1 μm is formed by high temperature oxidation, and the silicon nitride film 21c and the oxide film immediately below it are 400-1000 by high temperature oxidation after removing 21a.
A gate oxide film 24 having a thickness of approximately λ is formed.
そして、このゲート酸化膜２４の形成された半導体基体
２１の表面に加速電圧５０ ｋＶ、注入量３Ｘ１０”／
−程度の条件でボロン■の注入を行いしきい値電圧を設
定した後、例えば、気相成長された多結晶シリコン層を
写真蝕刻法を用いて所望パターンのゲート電極２５ａ及
び配線２５ｂを形成する。Then, the surface of the semiconductor substrate 21 on which the gate oxide film 24 was formed was subjected to an acceleration voltage of 50 kV and an implantation amount of 3×10”/
After implanting boron (2) under the conditions of - and setting the threshold voltage, for example, a gate electrode 25a and wiring 25b of a desired pattern are formed on the vapor-phase grown polycrystalline silicon layer using photolithography. .
次いで、このゲート電極２５ａをマスクにしてリン拡散
または砒素拡散を施してソース拡散領域２２及びドレイ
ン拡散２３を形成する。Next, using this gate electrode 25a as a mask, phosphorus diffusion or arsenic diffusion is performed to form a source diffusion region 22 and a drain diffusion 23.
この時２５ｂはよく知られている多結晶シリコンと基板
シリコンとのべリードコンタクト技術（直接接触技術）
によりドレイン拡散層２３に接続されている。At this time, 25b is a well-known buried contact technology (direct contact technology) between polycrystalline silicon and substrate silicon.
It is connected to the drain diffusion layer 23 by.
更にその表面に気相成長によりシリコン酸化膜２７を形
成して第５図Ｂに示す如き駆動ＭＯＳトランジスタを得
る。Furthermore, a silicon oxide film 27 is formed on the surface by vapor phase growth to obtain a driving MOS transistor as shown in FIG. 5B.
次にこの駆動ＭＯ８）ランジスタのシリコン酸化膜２７
に第５図Ｃに示す如く高濃度に不純物を拡散された多結
晶シリコン層２５ｂに通じるコンタクトホール２７ａを
写真蝕刻法を用いて形成する。Next, this drive MO8) silicon oxide film 27 of transistor
Next, as shown in FIG. 5C, a contact hole 27a communicating with the polycrystalline silicon layer 25b into which impurities are diffused at a high concentration is formed by photolithography.
そして、コンタクトホール２７ａの形成された半導体基
体２１の表面に不純物を含まない高抵抗体の層を気相成
長法等により形成すると共に、例えば、加速電圧５０ｋ
Ｖ、注入量Ｉ Ｘ １０１３〜１×１ｏ”／＝の条件で
リンイオンの注入を施し、所定の高比抵抗を備えた高比
抵抗体（１０１１〜１０６Ω／口）を得る。Then, a layer of a high resistance material containing no impurities is formed on the surface of the semiconductor substrate 21 in which the contact hole 27a is formed by vapor phase epitaxy or the like, and at an accelerating voltage of 50 k, for example.
Phosphorus ions are implanted under the conditions of V, implantation amount I x 10 13 to 1×1 o”/=, and a high resistivity body (10 11 to 10 6 Ω/hole) having a predetermined high specific resistance is obtained.
更に、このようにして所定の抵抗値が設定された低濃度
層２６を第５図師に示す如く、写真蝕刻法によりパター
ニングした後、気相成長法によりシリコン酸化膜２９を
成長させる。Further, the low concentration layer 26 having a predetermined resistance value thus set is patterned by photolithography as shown in FIG. 5, and then a silicon oxide film 29 is grown by vapor phase growth.
そして、このシリコン酸化膜２９に再び安定化処理を施
して半導体素子の安定化を図った後、その表面に厚さ約
５００ＯＡのリンケイ酸化ガラス（Ｐ−８−Ｇ） か
らなる保護膜３０を被着すると共に、この保護膜３０に
写真蝕刻法によって低濃度層２６及びソース拡散領域２
２等に通じるコンタクトホールを形成して、アルミニウ
ムなどからなる配線金属２８を形成し、第５図（υに示
す如き半導体装置３１を得る。After stabilizing the silicon oxide film 29 again to stabilize the semiconductor element, a protective film 30 made of phosphorus silicate glass (P-8-G) with a thickness of about 500 OA is coated on its surface. At the same time, a low concentration layer 26 and a source diffusion region 2 are formed on this protective film 30 by photolithography.
A contact hole communicating with the semiconductor device 2 and the like is formed, and a wiring metal 28 made of aluminum or the like is formed to obtain a semiconductor device 31 as shown in FIG. 5 (υ).
このようにして得られた半導体装置３１では、低濃度層
２６の一端部を１駆動ＭＯＳトランジスタのドレイン拡
散領域２３に接続された高濃度に不純物を拡散された多
結晶シリコン層２５ｂに直接接触するので低濃度層２６
と高濃度に不純物を拡散された多結晶シリコン層２５ｂ
のコンタクトは、以後の例えば、シリコン酸化膜２９等
の焼成工程による高濃度に不純物を拡散された多結晶シ
リコン層２６ｂから低濃度層２６への不純物拡散で実現
され、製造工程を簡略化して生産性を向上させることが
できる。In the semiconductor device 31 thus obtained, one end of the low concentration layer 26 is brought into direct contact with the polycrystalline silicon layer 25b in which impurities are diffused at a high concentration and connected to the drain diffusion region 23 of the 1-drive MOS transistor. So the low concentration layer 26
A polycrystalline silicon layer 25b in which impurities are diffused at a high concentration.
The contact is realized, for example, by diffusing impurities from the polycrystalline silicon layer 26b into the low concentration layer 26, which has been diffused with impurities at a high concentration during the baking process of the silicon oxide film 29, etc., thereby simplifying the manufacturing process and making production possible. can improve sex.
また、低濃度層２６の一端部が、すでに形成された高濃
度に不純を拡散された多結晶シリコン層２５ｂに直接接
触されるので、第３図で示す如き、高抵抗部分９ａと低
抵抗部分９ｂの分離工程を不要とし、高密度化を妨げる
原因となる不純物の拡散を防止して所定の抵抗値を有す
る低濃度層２６を形成することができ、半導体装置３１
の設計精度を高めて高密度化を図ることができると共に
、電気特性の向上を図ることができる。Furthermore, since one end of the low concentration layer 26 is directly contacted with the already formed polycrystalline silicon layer 25b into which impurities are diffused to a high concentration, a high resistance portion 9a and a low resistance portion are formed as shown in FIG. The separation step 9b is not required, and the low concentration layer 26 having a predetermined resistance value can be formed by preventing the diffusion of impurities that would impede high density, and the semiconductor device 31
It is possible to increase the design accuracy and achieve higher density, and also to improve the electrical characteristics.
尚、上記実施例では、駆動ＭＯＳトランジスタを用いた
インバータ回路に本発明を適用したものについて説明し
たが、本発明はこの他にも、例えば、基準電位発生回路
等の高比抵抗体を有する回路等を構成する半導体装置に
も適用することができるものである。In the above embodiment, the present invention was applied to an inverter circuit using a drive MOS transistor, but the present invention is also applicable to a circuit having a high specific resistance, such as a reference potential generation circuit. The present invention can also be applied to semiconductor devices constituting the above.
また、上記実施例では、低濃度層２６の一端部を、駆動
ＭＯ８）ランジスタのドレイン拡散領域２３につながる
高濃度に不純物を拡散された多結晶シリコン層に接触し
たものについて説゛明したが、この他にも低濃度層２６
の一端部又は両端部を半導体集積回路の例えば、ソース
拡散領域２２につながる高濃度に不純物を拡散された多
結晶シリコン層やゲート電極を形成する高濃度に不純物
を拡散された多結晶シリコン層など何れの高濃度に不純
物を拡散された多結晶シリコン層に接触したものでも良
い。Furthermore, in the above embodiment, one end of the lightly doped layer 26 is in contact with the polycrystalline silicon layer into which impurities are diffused at a high concentration and which is connected to the drain diffusion region 23 of the transistor (drive MO8). In addition to this, the low concentration layer 26
One end or both ends of the semiconductor integrated circuit may be formed by, for example, a polycrystalline silicon layer in which impurities are diffused at a high concentration that connects to the source diffusion region 22, a polycrystalline silicon layer in which impurities are diffused in a high concentration and forms a gate electrode, etc. It may be in contact with any polycrystalline silicon layer into which impurities are diffused at a high concentration.
また、上記実施例では低濃度層２６がフィールド酸化膜
２０の上方にシリコン酸化膜２７を介して形成されたも
のについて説明したが、本発明は、この他にも例えば、
ゲート電極２５ａの上方に位置する低濃度層２６を設け
たもの等を包含するものである。Further, in the above embodiment, the low concentration layer 26 is formed above the field oxide film 20 with the silicon oxide film 27 interposed therebetween, but the present invention is also applicable to other methods, for example,
This includes a structure in which a low concentration layer 26 is provided above the gate electrode 25a.
以上説明した如く、本発明に係る半導体装置の製造方法
では、高抵抗部分と低抵抗部分の分離を行って、高比抵
抗の抵抗体を得るための拡散工程を不要とすることによ
りマスク操作を除去して、作業性の向上を図ると共に製
造コストの低減化を図ることができる等顕著な効果を有
するものである。As explained above, in the method for manufacturing a semiconductor device according to the present invention, the high resistance part and the low resistance part are separated, and the mask operation is simplified by eliminating the need for a diffusion process to obtain a high resistivity resistor. This has remarkable effects such as being able to improve workability and reduce manufacturing costs by removing it.
第１図は、ＭＯＳトランジスタを負荷素子として用いた
Ｅ／Ｄインバータ回路を示す回路図、第２図は、従来の
インバータ回路を構成する半導体装置を示す断面図、第
３図は、第２図に示す半導体装置をその主面から見た状
態を示す説明図、第４図は、高比抵抗の抵抗体を用いた
インバータ回路を示す回路図、第５図Ａ乃至同図Ｅは、
本発明に係る半導体装置の製造工程を示し、同図Ａは、
半導体基体にボロンを注入している状態を示す断面図、
同図Ｂは、同図Ａに示す半導体基体を用いて得られた駆
動ＭＯ８）ランジスタを示す断面図、同図Ｃは、同図Ｂ
に示す駆動ＭＯ８）ランジスタにドレイン拡散領域につ
ながった高濃度に不純物を拡散された多結晶シリコン層
にコンタクトホールを穿設したものを示す断面図、同図
りは、同図Ｃに示す半導体基体の表面に高濃度層及びシ
リコン酸化膜を形成したものを示す断面図、同図Ｅは、
同図りに示す半導体基体の表面にシリコン酸化膜、保護
膜、及び配線金属を設けた本発明に係る半導体装置の一
実施例を示す断面図、第６図は、第５図Ｅに示す半導体
装置をその主面から見た状態を示す説明図である。
２．２１・・・・・・半導体基体、４，２３・・・・・
・ドレイン拡散領域、７，２８・・・・・・配線金属、
２７，２９・・・・・・シリコン酸化膜、９，２６・・
・・・・低濃度層、１１・・・・・・マスク層、３１・
・・・・・半導体装置。FIG. 1 is a circuit diagram showing an E/D inverter circuit using MOS transistors as load elements, FIG. 2 is a cross-sectional view showing a semiconductor device constituting a conventional inverter circuit, and FIG. FIG. 4 is a circuit diagram showing an inverter circuit using a high resistivity resistor, and FIGS. 5A to 5E are
The manufacturing process of the semiconductor device according to the present invention is shown in FIG.
A cross-sectional view showing a state in which boron is implanted into a semiconductor substrate,
Figure B is a cross-sectional view showing a driving MO8) transistor obtained using the semiconductor substrate shown in Figure A, and Figure C is a cross-sectional view of
A cross-sectional view showing a drive MO8) in which a contact hole is formed in a polycrystalline silicon layer in which impurities are diffused at a high concentration and connected to a drain diffusion region of a transistor. A cross-sectional view showing a structure with a high concentration layer and a silicon oxide film formed on the surface, FIG.
FIG. 6 is a cross-sectional view showing an embodiment of the semiconductor device according to the present invention in which a silicon oxide film, a protective film, and a wiring metal are provided on the surface of a semiconductor substrate, and FIG. 6 is a cross-sectional view of the semiconductor device shown in FIG. 5E. FIG. 2 is an explanatory diagram showing the state seen from the main surface. 2.21... Semiconductor substrate, 4,23...
・Drain diffusion region, 7, 28... Wiring metal,
27, 29... Silicon oxide film, 9, 26...
...Low concentration layer, 11...Mask layer, 31.
...Semiconductor device.
Claims (1)
て高濃度に不純物を有する第１多結晶シリコン層を前記
半導体基体の主面に形成した後に、反対導電型不純物を
導入して前記所定領域を反対導電型の不純物領域に変換
する工程と、前記第一多結晶シリコン層の不純物濃度よ
り少ない不純物濃度を有し該第１多結晶シリコン層に接
続する第２多結晶シリコン層からなる抵抗体を前記主面
に絶縁層を介して形成する工程と、前記第１多結晶シリ
コン層に熱処理を施して前記第２多結晶シリコン層への
不純物拡散を行う工程とを具備することを特徴とする半
導体装置の製造方法。1. After forming a first polycrystalline silicon layer having a high concentration of impurities on the main surface of the semiconductor substrate in direct contact with a part of a predetermined region of a semiconductor substrate of one conductivity type, impurities of the opposite conductivity type are introduced to a step of converting a predetermined region into an impurity region of the opposite conductivity type; and a second polycrystalline silicon layer having an impurity concentration lower than the impurity concentration of the first polycrystalline silicon layer and connected to the first polycrystalline silicon layer. It is characterized by comprising the steps of forming a resistor on the main surface via an insulating layer, and performing heat treatment on the first polycrystalline silicon layer to diffuse impurities into the second polycrystalline silicon layer. A method for manufacturing a semiconductor device.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54081126A JPS5826177B2 (en) | 1979-06-27 | 1979-06-27 | Manufacturing method of semiconductor device |
| US06/545,002 US4475964A (en) | 1979-02-20 | 1983-10-24 | Method of manufacturing a semiconductor device |
| US06/665,081 US4558343A (en) | 1979-02-20 | 1984-10-26 | Semiconductor device having a high resistivity layer in direct contact with a polycrystalline silicon layer of high impurity concentration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54081126A JPS5826177B2 (en) | 1979-06-27 | 1979-06-27 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS566464A JPS566464A (en) | 1981-01-23 |
| JPS5826177B2 true JPS5826177B2 (en) | 1983-06-01 |
Family
ID=13737691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54081126A Expired JPS5826177B2 (en) | 1979-02-20 | 1979-06-27 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5826177B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0195084U (en) * | 1987-12-16 | 1989-06-22 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4898838A (en) * | 1985-10-16 | 1990-02-06 | Texas Instruments Incorporated | Method for fabricating a poly emitter logic array |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5024230A (en) * | 1973-02-16 | 1975-03-15 | ||
| JPS50134389A (en) * | 1974-04-10 | 1975-10-24 |
-
1979
- 1979-06-27 JP JP54081126A patent/JPS5826177B2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5024230A (en) * | 1973-02-16 | 1975-03-15 | ||
| JPS50134389A (en) * | 1974-04-10 | 1975-10-24 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0195084U (en) * | 1987-12-16 | 1989-06-22 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS566464A (en) | 1981-01-23 |
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