JPS61206219A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a shallow N-type doped layer and a P-type layer having the practically same junction depth by a method wherein impurities are introduced into a silicide film only by performing an ion implantation. CONSTITUTION:A tungsten silicide film 18 is selectively formed on the surface only of a silicon substrate 12, and boron 20 is implanted into the silicide film 18 located on an N-type substrate using a photoresist film 19 as a mask. A photoresist film 12 is formed only on the part other than a P-well diffusion film 14, and arsenic 22 is implanted. Subsequently, after the photoresist film 21 is removed, a PSG film 23 is formed, the boron and arsenic implanted into the silicide film 18 are diffused on the silicon substrate, and a P-type diffusion film 24 and an N-type diffusion film 25 are formed. The respective diffusion films under the tungsten silicide film 18 have a high surface density, and also their junction depth is almost equal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, the present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device, in which heavily doped n-type and p-type layers under a silicide film are made to have substantially equal junction depths. The present invention relates to a method of manufacturing a semiconductor device suitable for.

[Background of the invention]

A conventional method for forming a diffusion layer under a silicide film is as described in Japanese Patent Application Laid-Open No. 88868/1983.

There is a method of diffusing impurities through a high melting point metal silicide film to form a diffusion layer on the silicon substrate under the silicide film, or a method of ionizing impurities at the high melting point metal film/silicon substrate interface as described in JP-A-59-99774. A method has been proposed in which a high melting point metal silicide film and a diffusion layer are formed on the silicon substrate at the same time by heat treatment after implantation.

However, in these methods, consideration has not been given to making the doped layer under the silicide film shallow and to making the junction depth of the n-type diffusion layer and the p-type doped layer the same. According to these methods, when forming an n-type doped layer and a p-type doped layer with the same junction depth on the same substrate, an impurity with a small diffusion coefficient in the silicon substrate (for example, arsenic as an n-type impurity) is used to form a predetermined doped layer. After forming the first doped layer with a depth of
This must be done by forming a second doped layer with boron as a p-type impurity.

Therefore, a first impurity introduction step and a first doping step for forming a first doped layer, a second impurity introduction step and a second diffusion step for forming a second doped layer, and so on. , a two-step impurity introduction process and a diffusion process are required. Furthermore, in order to obtain the same junction depth, there are many combinations of conditions for the first and second impurity introduction steps and conditions for the first and second diffusion steps, making it extremely difficult to set the conditions. .

In addition, in order to achieve a shallow junction depth of about 0.2 μm, annealing for about 30 minutes using a conventional electric furnace cannot raise the temperature at which the diffusion layer formed by arsenic and boron is formed.
For example, annealing for about 30 minutes.

The above temperature is limited to 1000°C or less. Furthermore, due to the difference in the diffusion coefficients of arsenic and boron in silicon, the temperatures to obtain the same junction depth differ by about 50°C. For example, arsenic may be diffused in the first diffusion layer at a predetermined temperature. After forming the second evaporation layer by performing boron diffusion at a temperature approximately 50° C. lower than the arsenic diffusion temperature, a diffusion layer having the same junction depth of approximately 0.2 μm can be obtained.

The concentration of electrically active impurities strongly depends on the processing temperature;
For example, the higher the processing temperature, the higher the concentration, and the lower the processing temperature, the lower the concentration. For this reason, since the second diffusion temperature is lower than the first diffusion temperature, the active arsenic concentration in the first diffusion layer formed by arsenic diffusion at a relatively high temperature decreases during the second diffusion step. Moreover, the active boron concentration is also kept low.

As described above, according to the conventional method, it is difficult to form a shallow junction of about 0.2 μm with a high active impurity concentration, and the concentration is determined by the processing temperature for forming the second diffusion layer. The solid solubility of impurities is limited, and as a result, the resistance of each diffusion layer cannot be made sufficiently low.

[Purpose of the invention]

An object of the present invention is to solve the problems of the conventional method, such as the large number of steps and the difficulty in setting conditions. An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a shallow n-type doped layer and a p-type layer having substantially the same junction depth (or low resistance).

[Summary of the invention]

The present invention is based on the novel finding that the above object can be achieved by satisfying the following sufficient conditions. That is, the first condition is that impurities are introduced only into the silicide film 4 by ion implantation, as shown in FIGS. 1(a) and 1(b). The reason is that the implanted impurities 6 and 8 are in the silicon substrate 1 under the silicide film 4.
The purpose is to prevent the formation of defects in the silicon substrate due to the implanted impurities, the increase in the depth of the implanted impurity distribution due to the channeling phenomenon, and the deterioration of controllability when the implanted impurities reach this level. That is, when ions are directly implanted into a silicon substrate, it becomes extremely difficult to form a high-quality junction with a sufficiently shallow junction depth.

The second condition is that an amount of impurity greater than the solid solubility is introduced into the silicide film. The reason is as follows. In order to form a silicide electrode with low contact resistance, it is desirable to increase the concentration of electrically active impurities directly under the silicide film as high as possible, as shown in Figure 2. This is because the above amount of impurities is required. That is, a high concentration of n-type or p-type
In order to form a type diffusion layer, it is necessary to make the diffusion of impurities into the silicon substrate during heat treatment limited by the solid solubility of the silicon substrate. In other words, the amount of impurities introduced into the silicide film must be greater than the solid solubility of the impurities in the silicide so that the excess impurities that exceed the solid solubility in the silicide film diffuse into the silicon substrate side in large quantities. If the amount of impurity introduced does not satisfy the above requirements, a high active impurity concentration cannot be expected because the active impurity concentration directly under the silicide film is determined by the impurity segregation coefficient between the silicide film and the silicon substrate. -1° Furthermore, the third condition is that, after introducing impurities into the silicide film 4, the surface of the silicide film 4 is covered with a film 9 in which impurities diffuse slowly. The reason for this is to prevent impurities 6 and 8 from evaporating from the surface of the silicide film, where impurity diffusion is extremely rapid, and to avoid invalidating the restriction on the amount of impurities introduced in the second condition. 0 For example, as shown in Figure 3, when the above film is not present, the active impurity concentration is extremely lower than when the above film is present, so the diffusion treatment must be performed by forming the above film on the silicide film surface. There is.

Finally, the fourth condition is that impurity diffusion from the silicide film to the silicon substrate be performed at high temperature and in a short time.

The reason for this is that by setting the diffusion temperature to a high temperature of 1,000 to 1,200°C and the diffusion time to a short period of about 5 to 60 seconds, each of the diffusion The active impurity concentration of layer 10.11 is 1 to 3×'o"j3-"
In addition, each diffusion layer 10.11
This is because the junction depth can be arbitrarily selected within a range of about 0.2 μm or less. In other words, by setting the active impurity concentration to the above level, the contact resistance of the silicide electrode can be lowered, so as shown in Figure 2, the resistance of the source and drain regions can be kept stable and low. I can do it. Furthermore, as shown in Fig. 4, in a MOS transistor having a gate length of about 1 μm, when the gate is processed with an accuracy of 10% (with respect to the gate length, the gate processing variation JL is =0.1
In order to suppress the threshold voltage fluctuation due to variation in gate length to 0.2 V or less, it is necessary to reduce the junction depth to about 0.2 μm or less. Depending on the conditions, this requirement can be easily achieved.

Further, as the n-type impurity, phosphorus can also be used in the present invention instead of arsenic.

[Embodiments of the invention]

Hereinafter, as an embodiment of the present invention, bond formation of CMO3 will be explained with reference to FIGS. 5 to 7.

A field oxide film 1 is formed on an n-type silicon substrate 12 with a substrate concentration of I x 10"cs-" by the usual LOCO3 method.
3, a p-well diffusion layer 14 with a concentration of I x 10"(1m-") is formed, and a gate oxide film 15 is
After forming a tungsten film as a gate electrode material, a gate electrode 16 was formed by a normal photoetching process (a).

Next, the gate electrode 16 is covered with a silicon oxide film 17 (b
), a 0.1 nm thick tungsten silicide film 18 was selectively formed only on the silicon substrate surface (Q).

Next, using a normal photoetching process, a 1 μm thick photoresist film 19 is formed only on the p-well diffusion layer 14, and using this photoresist film 19 as a mask, implant energy is applied to the silicide film 18 on the n-type substrate. = 2
20 boron implants were performed under the conditions of 5 k e V and implant amount = I x 10'/d (d).

Next, after removing the photoresist film 19, p
A photoresist film 21 with a thickness of 1 μm was formed only on the part other than on the well diffusion layer 14, and the implantation energy was 140 k.
Arsenic 23 implantation was performed under the conditions of e V and implantation amount = I x 10''/cd (e).

After that, after removing the photoresist film 21, 0.5
A μm-thick PSG (phosphorus glass) film 23 is formed, and by heat treatment at a heat treatment temperature of 1150° C. and a heat treatment time of 20 seconds, boron and arsenic implanted into the silicide film 18 are diffused into the silicon substrate. After forming the type diffusion layer 24 and the n-type diffusion layer 25 (f), the depth distribution of carriers in the n-type diffusion layer 24 and the n-type diffusion layer 25 is shown in FIG. 3. Each of the lower diffusion layers has a high surface concentration of I x 10"am-3.

Further, the junction depth is approximately equal to about 0.2 μm.

The layer resistances of the p-type and n-type diffusion layers at this time are as low as 80Ω/hole and 40Ω/hole, respectively.

According to this embodiment, diffusion layers of different conductivity types having the same junction depth can be formed in a single diffusion process.

Making the junction depth of each diffusion layer the same?

For manufacturing CMOS transistors, there is an advantage that the effective gate lengths can be made equal. In addition, it is possible to easily form a diffusion layer with an arbitrary junction depth depending on the diffusion conditions.
For example, as shown in FIG. 4, the bonding depth can be easily determined by determining the heat treatment temperature. Furthermore, since each diffusion layer has a high electrically active impurity concentration, the contact resistance between the silicide film and the diffusion layer can be reduced.

In addition, the heat treatment conditions described in this example are sufficient conditions to densify the PSG film, and the
SG film) can be used as a passivation film.

Furthermore, according to this embodiment, since the electrically active impurity concentration of the diffusion layer under the silicide film can be made higher than IXIO"as-', the resistance of the source and drain regions is low.
Moreover, the resistance has a stable value independent of variations in the impurity concentration. moreover.

Junction depth can be controlled to be shallow within 20 nm (see Figure 4)
In addition, since the n and p diffusion layers can have the same junction depth, the characteristics of each element can be made stable with very little variation.

[Effects of the Invention] According to the present invention, when manufacturing a semiconductor device having diffusion layers of different conductivity types, a single diffusion step can be used to form both P-type and n-type diffusion layers. Since diffusion layers with the same junction depth can be formed, the number of steps is reduced and it is also easier to set the heat treatment conditions for diffusion. Furthermore, under the heat treatment conditions of the present invention, the concentration of electrically active impurities in the diffusion layer can be increased to about 2 to 5 times higher than that of the conventional method, so the total resistance of each silicide film diffusion layer can be lowered compared to the conventional method. It can be lowered to about 1/2 to 1/3 compared to .

[Brief explanation of the drawing]

Fig. 1 is a process diagram showing the outline of the present invention, Fig. 2 is a WSi,
A diagram showing the relationship between the active impurity concentration at the silicide/Si substrate interface and the total resistance of the source/drain region. Figure 3 is a depth distribution diagram of the active impurity concentration, and Figure 4 is the relationship between the junction depth and threshold voltage. Figure 5 is a diagram showing the relationship between fluctuations, Figure 5 is a process diagram for manufacturing a C0M5 transistor using the present invention, Figure 6 is a depth distribution diagram of electrically active impurity concentration, Figure 7 is heat treatment temperature and diffusion. It is a relationship diagram with the junction depth of a layer. 1.12... N-type silicon substrate, 2.14... P-well diffusion layer, 3, 13, 15, 17... Silicon oxide film, 4.18... Tungsten silicide film, 5°7
．． 19.21...Resist film, 6.20...Boron ion, 8,22...Arsenic ion, 9...Coating, 1
0°24...p-type diffusion layer, 11, 25...n-type diffusion layer, 16...gate electrode, 23...PSG film, 26
...Carrier distribution in the P-type diffusion layer, 27...Carrier distribution in the n-type diffusion layer.

Claims (1)

[Claims] 1. Arsenic or phosphorus and boron are added to the silicide film on the regions where the high concentration n-type diffusion layer and the high concentration p-type diffusion layer are to be formed so that the implanted impurity concentration in the silicide film is higher than the solid solubility. a step of implanting ions, a step of forming a film on the silicide film in which the diffusion coefficient of arsenic or phosphorus and boron is smaller than that of the silicide film, and a heat treatment temperature of 1000 to 1200°C and a heat treatment time of 5 to 60 seconds. 1. A method for manufacturing a semiconductor device, comprising the step of performing heat treatment in the range of .