JPH0526343B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for manufacturing a MOS FET.
In particular, highly integrated LSIs consisting of complementary MOS/FETs
It is an object of the present invention to provide a semiconductor device which can cope with higher density of elements by annealing impurity diffusion layers which become source and drain regions at a low temperature for a short time, and further has less leakage current due to crystal defects. Conventionally, in the manufacture of LSIs consisting of silicon gate complementary MOS/FETs, the source/drain regions of P-type MOS/FETs are coated with a high concentration (1.0×10 ¹⁵ cm ^-2
11 B ions are implanted into the source and drain regions of n-type MOS/FETs at a high concentration (1.0×10 ¹⁵ cm ^-2
75 As ions are implanted, and the ion-implanted layer is annealed at high temperature for a long time (for example, 100° C. for 30 minutes). However, although ^11B and ^75As are 100% activated by high-temperature and long-term annealing, ^{the 11B} implanted and diffused layer spreads laterally and in the depth direction, and the junction depth decreases.
It became larger than 0.5 μm, causing source/drain punch-through and preventing miniaturization of P-type MOS/FET. In addition, in ^{the 75} As ion-implanted layer, the mass of implanted ions is larger than that of Si in the silicon substrate.
Crystal defects are caused by ion collision during implantation, resulting in a large leakage current at the n-type junction, and high-temperature annealing is absolutely necessary to recover the defects and reduce the leakage current. Therefore, conventional complementary MOS/FET manufacturing methods cannot be used to manufacture LSIs that cannot be miniaturized and have less leakage current due to defects. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a complementary MOS/FET which eliminates such conventional drawbacks, causes less leakage current due to defects, and allows miniaturization. In order to achieve the above object, the present invention provides P-type
BF ₂ is used in the source and drain regions of MOS/FET.
By implanting ions of 1×10 ¹⁵ cm ^-2 or more, n-type MOS・
^31P ions are added to the source and drain regions of the FET.
The ion-implanted layer is implanted at a rate of ×10 ¹⁵ cm ^-2 or more, and the ion-implanted layer is annealed at a low temperature of 900°C or less by a short heat treatment lasting less than 1 minute. Hereinafter, it will be explained in detail using examples. Table 2
is a flow chart of conventional complementary MOS/FET manufacturing. After forming the well field film, gate film, and Polysi gate electrode, P-type MOS
¹¹ B ions are implanted into the source/drain region of the FET, and ⁷⁵ As is implanted into the source/drain of the N-type MOS/FET.
After ion implantation, high temperature and long-term heat treatment using a diffusion furnace was performed to recover and activate the crystals of the ion implanted layer. In the conventional manufacturing method, as shown in Figure 1, high-temperature heat treatment of 900℃ or higher is required to activate ¹¹ B ions, and the large mass number of ⁷⁵ As causes significant damage to the silicon substrate surface. In order to reduce leakage current in diffusion bonding, high-temperature and long-term heat treatment annealing was required.
However, conventional high-temperature, long-term heat treatment (e.g. 1000℃)
30 minutes), the boron diffusion length increases, the diffusion junction depth and lateral spread increase, and the punch-through between the source and drain increases the P-type MOS/FET.
This limits the downsizing of the . Table 1 is a flow chart of complementary MOS/FET manufacturing according to the present invention. After forming the well field film, gate film, and PolySi gate electrode,
BF ₂ in the source and drain regions of P-type MOS/FET
By implanting ions of 1×10 ¹⁵ cm ^-2 or more, N-type MOS
1x ^31P ions in the source/drain region of the FET
10 ¹⁵ After injection, halogen lamp, graphite
A low-temperature, short-time heat treatment is performed using a heater or the like to recover and activate the crystals of the ion-implanted layer. In the present invention, the reason why BF ₂ is implanted at 1×10 ¹⁵ cm ⁻² or more is necessary to make the implanted layer amorphous. The same reason also applies to injecting 1×10 ¹⁵ cm ^-2 or more of ³¹ P. Crystal recovery of the ion-implanted layer amorphized by BF ₂ or ³¹ P is
This is possible with heat treatment at 700°C or higher, and as shown in Figure 1, BF ₂ or ³¹ P ions can be activated 100% by heat treatment at 800°C or higher. The correlation between annealing temperature and sheet resistance in FIG. 1 is when the ion implantation amount is 1.0×10 ¹⁵ cm ⁻² and the annealing time is 10 seconds. Therefore, the ion-implanted layer made amorphous by BF ₂ or ³¹ P ion implantation can be annealed by heat treatment at a low temperature of 900° C. or lower and for a short time of less than 1 minute. Heat treatment at a temperature below 900°C within 1 minute does not cause boron diffusion redistribution. Moreover, n-type, P
Since the mass number of type ions is not significantly different from that of Si, leakage current in diffusion bonding is small due to low-temperature, short-time heat treatment. Therefore, according to the present invention, by ion-implanting boron difluoride instead of boron, which has a small ionic radius, the silicon crystal structure of the ion-implanted layer is disturbed, that is, the silicon crystal structure is made amorphous, so that the silicon crystal structure can be ion-implanted at low temperatures for a short period of time. P-type annealing is possible, and diffusion redistribution of the diffusion layer can be suppressed.
This has the effect of making it possible to downsize the MOS/FET. Furthermore, the mass number of BF ₂ and P and the substrate material Si
Since there is not much difference between the mass number of
Even when annealing is performed at a low temperature of 900° C. or less for a short time, for example, one minute or less, the leakage current of the diffusion bond can be suppressed to a low level, and a highly reliable semiconductor device can be provided.

[Table] Manufacturing flow chart

【table】

[Table] Flow chart

[Brief explanation of the drawing]

FIG. 1: A diagram showing the correlation between the sheet resistance of the diffusion layer and the annealing temperature obtained by short-time annealing using a halogen lamp.

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor device having a complementary MOS/FET, a part of the P-type MOS/FET formation region which is a component of the complementary MOS/FET is
By implanting BF ₂ ions of 1×10 ¹⁵ cm ^-2 or more, the P-type
The step of forming a BF ₂ ion implantation layer that will become the source region and drain region of the MOS/FET, the complementary type
N-type MOS/FET, a component of MOS/FET
a step of implanting ^31P ions of 1×10 ¹⁵ cm ^-2 or more into a part of the formation region to form a P ion implantation layer that will become the source region and drain region of the N-type MOS/FET, the BF ₂ ion implantation layer; and a step of subjecting the P ion-implanted layer to short-time heat treatment annealing at a temperature of 900° C. or lower.