KR100212010B1 - Method for fabricating transistor of semiconductor device - Google Patents
Method for fabricating transistor of semiconductor device Download PDFInfo
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- KR100212010B1 KR100212010B1 KR1019950029989A KR19950029989A KR100212010B1 KR 100212010 B1 KR100212010 B1 KR 100212010B1 KR 1019950029989 A KR1019950029989 A KR 1019950029989A KR 19950029989 A KR19950029989 A KR 19950029989A KR 100212010 B1 KR100212010 B1 KR 100212010B1
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 229910052731 fluorine Inorganic materials 0.000 claims description 18
- 239000011737 fluorine Substances 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 13
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- 125000001153 fluoro group Chemical group F* 0.000 claims description 7
- 150000002222 fluorine compounds Chemical class 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 2
- 229940126062 Compound A Drugs 0.000 claims 1
- NLDMNSXOCDLTTB-UHFFFAOYSA-N Heterophylliin A Natural products O1C2COC(=O)C3=CC(O)=C(O)C(O)=C3C3=C(O)C(O)=C(O)C=C3C(=O)OC2C(OC(=O)C=2C=C(O)C(O)=C(O)C=2)C(O)C1OC(=O)C1=CC(O)=C(O)C(O)=C1 NLDMNSXOCDLTTB-UHFFFAOYSA-N 0.000 claims 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 13
- 238000002513 implantation Methods 0.000 description 10
- -1 boron ions Chemical class 0.000 description 9
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000010884 ion-beam technique Methods 0.000 description 5
- 230000005465 channeling Effects 0.000 description 4
- 150000001793 charged compounds Chemical class 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, P형 MOS 트랜지스터의 펀치-쓰루우 문제를 개선하기 위하여 실리콘 기판에 GeF3 +이온을 주입하여 표면 부위를 비정질화시킨 후 저에너지로11B+이온을 주입하여 접합 영역을 형성하므로써 소자의 전기적 특성이 향상될 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. In order to improve the punch-through problem of a P-type MOS transistor, GeF 3 + ions are implanted into a silicon substrate to amorphousize a surface portion thereof, and 11 B + ions with low energy. The present invention relates to a method for fabricating a transistor of a semiconductor device in which the electrical properties of the device can be improved by forming a junction region by injecting.
Description
제1(a)도 및 제1(b)도는 종래 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining a transistor manufacturing method of a conventional semiconductor device.
제2(a)도 내지 제2(c)도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1및11 : 실리콘 기판 2및12 : N-웰1 and 11: silicon substrate 2 and 12: N-well
3및13 : 게이트 산화막 4및14 : 폴리실리콘층3 and 13: gate oxide film 4 and 14 polysilicon layer
4및14A : 게이트 전극 5및15 : 산화막 스페이서4 and 14A: gate electrode 5 and 15: oxide spacer
6및16 : 접합 영역 16A : 비정질층6 and 16: junction region 16A: amorphous layer
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 실리콘 기판에 GeF3 +이온을 주입하여 실리콘 기판의 표면에 비정질층을 한 후11B+이온을 주입하고 열처리 공정을 실시하여 접합 영역을 형성하는 동시에 GeF3 +이온의 불소성분에 의해 불소 화합물의 생성을 극소화시키므로써 소자의 전기적 특성을 향상시킬 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, and in particular, implants GeF 3 + ions into a silicon substrate to form an amorphous layer on the surface of the silicon substrate, and then implants 11 B + ions and performs a heat treatment to form a junction region. at the same time one of the transistor manufacturing method of the semiconductor element to improve the electrical characteristics of the device to write because minimizing the generation of a fluorine compound by a fluorine component of GeF 3 + ions.
일반적으로 반도체 소자가 고집적화됨에 따라 트랜지스터의 크기도 감소된다. 트랜지스터의 크기 감소는 채널 길이(Channel Length)의 감소를 가져온다. 그런데 트랜지스터의 채널 길이가 짧을 경우, 트랜지스터의 동작시 소오스 및 드레인 접합(Source/Drain Junction)의 공핍 영역(Depletion Region)이 서로 만나면서 두 접합 영역 사이에 갑자기 많은 전류가 흐르는 현상이 발생된다. 이를 펀치-쓰루우(Punch-Through)라 한다. 이와 같은 펀치-쓰루우 현상은 소자의 고집적화에 따라 더욱 심하게 발생된다. 특히 N형 및 P형 MOS 트랜지스터로 구성되는 CMOS 트랜지스터에서 P형 MOS 트랜지스터의 경우 펀치-쓰루우 문제는 실제적으로 심각하게 나타난다. 이를 개선하기 위해서는 P형 MOS 트랜지스터의 접합 깊이(Junction Depth)를 얕게 형성하는 것이 필요하다. 그러면 종래 P형 MOS 트랜지스터의 제조 방법을 제1(a)도 및 제1(b)도를 통해 설명하면 다음과 같다.In general, as semiconductor devices become more integrated, the size of transistors also decreases. The decrease in the size of the transistor results in a decrease in the channel length. However, when the channel length of the transistor is short, when the transistor operates, depletion regions of the source and drain junctions (Source / Drain Junction) meet each other, suddenly a large current flows between the two junction regions. This is called Punch-Through. This punch-through phenomenon is more severely generated by high integration of the device. Especially in the case of P-type MOS transistors in CMOS transistors consisting of N-type and P-type MOS transistors, the punch-through problem is actually serious. In order to improve this, it is necessary to form a shallow junction depth of the P-type MOS transistor. A method of manufacturing a conventional P-type MOS transistor will now be described with reference to FIGS. 1 (a) and 1 (b).
종래의 P형 MOS 트랜지스터의 제조 방법은 제1(a)도에 도시된 바와 같이 N-웰(2)이 형성된 실리콘 기판(1)상에 게이트 산화막(3) 및 폴리실리콘층(4)을 순차적으로 형성한 후 패터닝하여 게이트 전극(4A)을 형성한다. 게이트 전극(4A)의 양측벽에 산화막 스페이서(5)를 형성한 후 노출된 실리콘 기판(1)에 P형의 불순물 이온을 주입하고 열처리하여 제1(b)도와 같이 접합 영역(6)을 형성한다. 여기서 P형 불순물 이온으로는49BF2 +이온이 일반적으로 널리 사용된다.49BF2 +이온을 사용할 경우,49BF2 +분자 이온이 실리콘 기판(1) 내부로 주입되는 과정에서 붕소(B)와 불소(F) 이온으로 각각 유리되는데, 붕소(B)와 불소(F)이온은 각각의 다른 이온주입 깊이(Rp; Projected Range)를 갖게 된다. 붕소(B) 이온의 주입 깊이는 하기의 식 1과 같으며, 불소(F) 이온의 주입 깊이는 사기의 식 2와 같다.In the conventional method of manufacturing the P-type MOS transistor, as shown in FIG. 1 (a), the gate oxide film 3 and the polysilicon layer 4 are sequentially formed on the silicon substrate 1 on which the N-well 2 is formed. After forming, the gate electrode 4A is formed by patterning. After forming oxide spacers 5 on both sidewalls of the gate electrode 4A, P-type impurity ions are implanted into the exposed silicon substrate 1 and heat-treated to form a junction region 6 as shown in FIG. 1 (b). do. Here, the P-type impurity ion is 49 BF 2 + ions are widely used. When 49 BF 2 + ions are used, 49 BF 2 + molecular ions are released into boron (B) and fluorine (F) ions during the implantation into the silicon substrate 1, respectively. Ions have different ion implantation depths (R p ; projected range). The implantation depth of boron (B) ions is as shown in Equation 1 below, and the implantation depth of fluorine (F) ions is as in Equation 2 in Sor.
그러므로 예를 들어 40KeV의 BF2 +이온을 주입할 경우 약 9KeV의 BF+이온을 주입한 것과 동일한 주입 깊이를 얻을 수 있다. 따라서 저에너지를 이용하는 경우 이온 빔의 추출이 어려운 붕소 이온 대신 비교적 이온 빔 전류가 많이 생성되는 BF2 +이온을 사용하므로써 원하는 주입 깊이를 얻을 수 있다. 또한 BF2 +이온을 사용하면 동일한 주입 깊이를 갖는 붕소 이온을 사용하는 경우보다 채널링(Channeling)이 적게 발생되는 잇점이 있다.Thus, for example, the BF + ions of about 9KeV can achieve the same implantation depth as the injection when the injection of BF 2 + ions of 40KeV. Therefore, it is possible to obtain a desired injection depth by the use of the case of using the low energy is difficult to extract the ion beam of boron ions instead of the ion beam relatively BF 2 + ion current is generated much. In addition, the use of BF 2 + ions has the advantage of less channeling than when using boron ions having the same implantation depth.
상기 BF2 +이온을 주입한 후에는 주입된 이온들의 전기적 활성화를 위해 열처리를 실시한다. 그러나 열처리 후 실리콘 기판 내부에는 불소 잔류물들이 남게 되고, 상기 불소 잔류물들은 금속층과의 접촉이 이루어지는 콘택홀(Contact Hole)내의 실리콘 기판의 표면에서 불소 거품(Fluorine Bubble)을 형성하여 접촉 저항(Contact Resistance)을 증가시키며, 접합 영역내에서 불화 석출물(Fluorine Precipitate)을 형성하여 전도도를 저하시킨다.After implanting the BF 2 + ions, heat treatment is performed for electrical activation of the implanted ions. However, after heat treatment, fluorine residues remain in the silicon substrate, and the fluorine residues form a fluorine bubble at the surface of the silicon substrate in the contact hole where the metal layer contacts with the contact resistance. ) And decreases conductivity by forming Fluorine Precipitate in the junction region.
근래에 들어 서브 마이크론(Sub Micron)의 채널 길이를 갖는 P형 MOS 트랜지스터의 제조 공정에서 붕소 이온 주입시 발생되는 채널링을 감소시키기 위하여, 먼저 실리콘 기판에 실리콘(Si), 게르마늄(Ge), 불소(F) 및 비소(As) 이온을 주입하여 표면을 비정질화시킨 후 저에너지를 이용하여 붕소(11B+) 또는 BF2 +분자 이온을 주입하는 방법이 제안되었다. 그러나 이방법을 이용할 경우 몇가지 단점이 발생되었다. 첫째, 상기 실리콘(Si), 게르마늄(Ge) 또는 불소(F+) 이온을 종래의 이온 주입기를 이용하여 주입하는 경우 빔 전류가 적게 발생되어 생산성이 저하된다. 둘째, 상기 실리콘(Si) 및 게르마늄(Ge) 이온을 주입하여 표면을 비정질화시킨 후 저에너지를 이용하여 붕소 이온을 주입하는 경우 열처리후에 잔류되는 결정 결함으로 인하여 접합 영역에서 누설 전류가 발생된다. 셋째, 상기 실리콘(Si) 및 게르마늄(Ge) 이온을 주입하여 표면을 비정질화시킨 후 BF2 +분자 이온을 주입하는 경우 BF2 +이온만 주입하는 경우보다 비정질층이 더 깊게 형성된다. 또한 실리콘 내부에 공동형 결함 및 침입형 결함이 많이 생성되어 열처리 초기 확산 속도를 더 증가시키므로 접합 깊이가 증가되며, BF2 +이온을 주입하는 경우에 생성되는 불소 잔류물이 그대로 잔류된다. 넷째, 비소(As+) 이온을 주입하여 표면을 비정질화시키는 경우 접합 영역의 전기 전도도가 저하되고, 상기 접합 영역에서 전자의 농도가 높아져 역전압 인가시 누설 전류의 발생이 증가되기 때문에 소자의 제조에 적용하기 어렵다. 다섯째, 상기 실리콘(Si), 게르마늄(Ge) 또는 불소(F+) 이온과 같은 질량이 작은 이온을 사용하는 경우 질량이 무거운 이온을 사용할 경우보다 이온 주입 깊이가 더 깊게 형성되어 격자 손상층이 더 깊게 형성된다. 그러므로 BF2 +와 같이 질량이 무거운 이온을 사용하는 경우보다 열처리후에 격자 손상층이 공핍층 가까이 형성되어 전류의 손실이 100 내지 1000배 가량 많이 발생된다. 특히 서브 쿼터 마이크론(Sub Quarter Micron)화 되는 집적 회로의 제조 공정에서는 접합 영역을 얕게 형성하기 위해 열처리 시간을 짧게 실시하기 때문에 이온 주입시에 형성된 격자 손상이 완전히 제거되지 않는다. 그러므로 잔류되는 격자 손상으로 인한 전류의 손실은 더욱 증가된다.Recently, in order to reduce the channeling generated during the implantation of boron ions in the manufacturing process of a P-type MOS transistor having a submicron channel length, first, silicon (Si), germanium (Ge), and fluorine ( A method of implanting boron ( 11 B + ) or BF 2 + molecular ions using low energy after amorphizing the surface by injecting F) and arsenic (As) ions has been proposed. However, there are some disadvantages when using this method. First, when the silicon (Si), germanium (Ge) or fluorine (F + ) ions are implanted using a conventional ion implanter, less beam current is generated and productivity is lowered. Second, when silicon (Si) and germanium (Ge) ions are implanted and the surface is amorphized, and boron ions are implanted using low energy, leakage current is generated in the junction region due to crystal defects remaining after the heat treatment. Third, after the amorphizing the surface by implanting the silicon (Si) and germanium (Ge) ions when implanting BF 2 + molecular ion BF 2 + ions is only formed in the deeper layer than in the case of amorphous injection. In addition, because the generated many cavity-type defects and interstitial defects within the silicon further increase the initial rate of diffusion heat treatment and increases the junction depth, the fluorine residues generated when implanting BF 2 + ions is still remaining. Fourth, in the case of implanting arsenic (As + ) ions to amorphous the surface, the electrical conductivity of the junction region is lowered, the concentration of electrons in the junction region is increased, the leakage current increases when the reverse voltage is applied to the manufacturing of the device Difficult to apply Fifth, in the case of using small ions such as silicon (Si), germanium (Ge), or fluorine (F + ) ions, the ion implantation depth is deeper than in the case of using heavier mass ions, resulting in more lattice damage layer. Deeply formed; Therefore, the damage to the lattice layer is formed close to the depletion layer after the heat treatment than the case of the mass using a heavy ion such as BF 2 + a loss of the current is generated a lot of about 100 to 1000 times. In particular, in the manufacturing process of an integrated circuit that becomes a sub quarter micron, the lattice damage formed at the time of ion implantation is not completely removed because the heat treatment time is shortened to form a shallow junction region. Therefore, the loss of current due to residual grid damage is further increased.
따라서, 본 발명은 실리콘 기판에 GeF3 +이온을 주입하여 표면을 비정질화시킨 후11B+이온을 주입하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는데 그 목적 이 있다.Accordingly, an object of the present invention is to provide a method for fabricating a transistor of a semiconductor device which can solve the above disadvantages by implanting GeF 3 + ions into a silicon substrate and then implanting 11 B + ions.
상술한 목적을 달성하기 위한 본 발명은 N-웰이 형성된 실리콘 기판 상부에 게이트 산화막 및 폴리실리콘층을 순차적으로 형성한 후 패터닝하여 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 양측벽에 산화막 스페이서를 형성한 후 노출된 실리콘 기판에 GeF3 +이온을 주입하여 상기 실리콘 기판의 표면 부위에 비정질층을 형성하는 단계와, 저에너지를 이용하여 상기 노출된 실리콘 기판에 붕소(11B+)이온을 주입하는 단계와, 열처리 공정을 실시하여 접합 영역을 형성하는 동시에 상기 GeF3 +이온에 함유된 불소 성분이 상기 실리콘 기판의 표면에서 실리콘 및 게르마늄 원소들과 반응하여 SixGe1-xF4성분의 가스를 방출시켜 불소 화합물의 생성을 극소화시키는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a gate electrode by sequentially forming a gate oxide film and a polysilicon layer on the silicon substrate on which the N-well is formed and patterned, and an oxide spacer on both side walls of the gate electrode Forming a amorphous layer on the surface of the silicon substrate by implanting GeF 3 + ions into the exposed silicon substrate and implanting boron ( 11 B + ) ions into the exposed silicon substrate using low energy ; steps and, by carrying out the heat-treating step at the same time of forming the bonding region of the GeF 3 + a fluorine component-containing ions react with the silicon and germanium element in the surface of the silicon substrate of Si x G e1-x F 4 components Releasing the gas to minimize the production of fluorine compounds.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2(a)도 내지 제2(c)도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
제2(a)도를 참조하면, N-웰(12)이 형성된 실리콘 기판(11)상에 게이트 산화막(13) 및 폴리실리콘층(14)을 순차적으로 형성한 후 패터닝하여 게이트 전극(14A)을 형성한다. 게이트 전극(14A)의 양측벽에 산화막 스페이서(15)를 형성한 후 노출된 실리콘 기판(11)에 5.0E13 내지 1.0E15 이온/정도로 질량이 무거운 이온을 20 내지 150KeV의 에너지로 주입하여 실리콘 기판(11)의 표면 부위에 비정질층(16A)을 종래보다 얕게 형성한다.Referring to FIG. 2A, the gate oxide layer 13 and the polysilicon layer 14 are sequentially formed on the silicon substrate 11 on which the N-well 12 is formed, and then patterned to form the gate electrode 14A. To form. After forming oxide film spacers 15 on both side walls of the gate electrode 14A, 5.0E13 to 1.0E15 ions / A heavy mass of ions is implanted at an energy of 20 to 150 KeV to form the amorphous layer 16A on the surface portion of the silicon substrate 11 to be shallower than before.
제2(b)도는 노출된 실리콘 기판(11)에 5.0E14 내지 5.0E15 이온/㎠의 붕소(11B+) 이온을 1 내지 20KeV의 저에너지로 주입하는 상태의 단면도인데, 이때 비정질층(16A)에 의해 채널링의 발생이 감소된다.FIG. 2 (b) is a cross-sectional view of implanting 5.0E14 to 5.0E15 ions / cm 2 of boron ( 11 B + ) ions at a low energy of 1 to 20 KeV in the exposed silicon substrate 11, wherein the amorphous layer 16A This reduces the occurrence of channeling.
제2(c)도는 열처리를 실시하여 접합영역(16A)의 형성을 완료한 상태의 단면도인데, 열처리시 주입된 GeF3 +이온에 함유된 불소 성분이 실리콘 기판(11)의 표면에서 실리콘(Si) 및 게르마늄(Ge) 원소들과 반응하여 SixGe1-xF4성분의 가스로 방출된다. 그러므로 잔류되는 불소의 량은 BF2 +이온만을 주입한 경우보다 1/40 내지 1/2 정도로 적으며, 따라서 실리콘 기판의 표면에서 불소 화합물의 생성이 극소화되어 접합 영역과 금속층의 접촉 저항이 감소된다.FIG. 2 (c) is a cross-sectional view showing the completion of the formation of the junction region 16A by heat treatment, wherein fluorine component contained in the GeF 3 + ions implanted during the heat treatment is formed on the surface of the silicon substrate 11. ) And the germanium (Ge) elements are released into the gas of Si x G e1-x F 4 component. Therefore, the amount of residual fluoride which were less than about 1/40 to 1/2 if only one injection BF 2 + ions, and thus the generation of the fluorine compound on the surface of the silicon substrate minimizes the contact resistance of the junction regions and the metal layer is reduced .
본 발명에서 사용하는 GeF3 +분자 이온 빔은 GeF4가스를 이온화시켜 얻을 수 있다. 상기 GeF4가스를 이온화시켜 얻을 수 있는 이온의 종류는 Ge+, GeF+, GeF2 +, GeF3 +F+, 및 F2 +등이 있다. 상기 Ge+, GeF+, GeF2 +, GeF3 +F+, 및 F2 +등의 이온 빔 전류는 GeF3 +이온 빔 전류의 1/3 내지 1/5 정도이다. 그러므로 상기와 같이 GeF3 +이온을 사용하면 Ge+및 F+이온을 사용했을 경우보다 3배 이상의 생산성 향상을 기대할 수 있다. 상기 GeF3 +이온은 5.0E13 내지 1.0E15 이온/의 량으로 주입된다. 그러므로 실리콘 기판내에 주입되는 불소 원자의 수를 1.5E14 내지 1.0E15 이온/이내로 조절하는 것이 가능하다. 예를들어 약 3.0E15 이온/의 BF2 +이온을 실리콘 기판에 주입한 후 850℃의 온도에서 30분간 열처리하면 약 0.2㎛ 두께의 접합 영역이 형성되며, 이때 상기 접합 영역의 면저항은 170/? 이하가 된다. 또한 상기 실리콘 기판에 주입되는 불소 원자의 수는 6.0E15 이온/이다. 그러므로 GeF3 +이온을 사용하면 BF2 +이온을 사용하는 경우보다 약 1/40 내지 1/2 정도의 불소 원자가 실리콘 기판에 주입된다. 따라서 BF2 +이온을 주입한 후의 열처리시에 생성되는 불소 화합물로 인한 접촉 저항의 증가를 방지할 수 있다. 또한 본 발명에서는 질량이 130 정도인 GeF3 +이온을 사용하므로 Ge+및 F+을 사용하는 경우보다 비정질층 또는 격자 손상층의 깊이를 얕게 형성하기 용이하며, 열처리후에 발생되는 접합 손실을 극소화시킬 수 있다. 상기 GeF3 +이온 사용시 이온 주입 깊이는 게르마늄의 경우 하기의 식 3과 같은 에너지를 갖는 게르마늄 이온의 주입 깊이와 같으며, 불소 이온의 경우 하기의 식 4와 같은 에너지를 갖는 불소 이온의 주입 깊이와 같다.GeF 3 + molecular ion beam to be used in the present invention can be obtained by ionizing a GeF 4 gas. Types of ions that can be obtained by ionizing the GeF 4 gas include Ge + , GeF + , GeF 2 + , GeF 3 + F + , and F 2 + . The ion beam currents of Ge + , GeF + , GeF 2 + , GeF 3 + F + , and F 2 + are about 1/3 to 1/5 of the GeF 3 + ion beam current. Therefore, using GeF 3 + ions as described above can be expected to improve the productivity more than three times than when using Ge + and F + ions. The GeF 3 + ions are 5.0E13 to 1.0E15 ions / It is injected in a dose. Therefore, the number of fluorine atoms injected into the silicon substrate is 1.5E14 to 1.0E15 ions / It is possible to adjust within. For example about 3.0E15 ions / After implanting BF 2 + ions into the silicon substrate and heat treatment at a temperature of 850 ℃ for 30 minutes to form a junction region of about 0.2㎛ thickness, wherein the sheet resistance of the junction region is 170 /? It becomes as follows. In addition, the number of fluorine atoms injected into the silicon substrate is 6.0E15 ions / to be. Therefore, when using GeF 3 + ions, about 1/40 to 1/2 of fluorine atoms are injected into the silicon substrate than when using BF 2 + ions. Therefore, it is possible to prevent an increase in contact resistance caused by the fluorine compound generated at the time of the post-heat treatment by implanting BF 2 + ions. In addition, in the present invention, since the GeF 3 + ion having a mass of about 130 is used, it is easier to form a shallower depth of the amorphous layer or the lattice damage layer than the case of using Ge + and F + , and minimizes the bonding loss generated after the heat treatment. Can be. When the GeF 3 + ion is used, the ion implantation depth is the same as the implantation depth of germanium ions having energy as shown in Equation 3 below for germanium, and the implantation depth of fluorine ions having energy as shown in Equation 4 below as for fluorine ions. same.
그러므로 불소(F+)이온을 주입하여 실리콘 기판의 표면을 선비정질화시키는 경우에 나타나는 효과를 얻기 위해서 불소(F+) 이온 주입시보다 약 6.8배의 큰 에너지를 사용할 수 있기 때문에 빔 안정성 및 공정 안정성면에서 큰 잇점을 갖는다. 참고적으로 이온주입 에너지에 따른 게르마늄 및 불소 이온의 주입 깊이를 하기의 표 1에 도시하였다.Thus, beam stability and process stability, because the fluorine (F +) ions to be implanted by using a high energy of about 6.8 times than that of fluorine (F +) ion implantation in order to obtain the effect of the case-ray amorphous solidifying the surface of the silicon substrate It has great advantages in terms of aspects. For reference, the implantation depths of germanium and fluorine ions according to ion implantation energy are shown in Table 1 below.
상술한 바와 같이 본 발명에 의하면 실리콘 기판에 GeF 이온을 주입하여 표면을 비정질화시킨 후B 이온을 주입하므로써 첫째, BF 이온을 사용하는 경우보다 낮은 면저항과 더 얕은 접합 깊이를 갖는 접합 영역을 형성할 수 있고, 둘째, 표면의 비정질화에 의해 붕소 주입시 채널링이 방지될 수 있으며, 세째, Ge 및 F 이온을 사용했을 경우보다 3배 이상의 빔 전류를 얻을 수 있어 생산성 향상을 기대할 수 있다. 넷째, 주입되는 불소의 량을 감소시켜 후속 열처리시 생성되는 불소 화합물로 인한 접촉 저항의 증가를 방지할 수 있다. 다섯째, 높은 에너지 범위에서 공정을 진행할 수 있고, 공정을 조절하기 위해 사용할 수 있는 에너지 범위의 폭이 넓으며, 에너지 변화에 따른 주입 깊이의 변화폭이 적으므로 공정을 정밀하게 조절할 수 있다. 여섯째, 얇은 비정질층 또는 격자 손상층을 용이하게 형성할 수 있다. 이로 인해 열처리후에 잔류 결함이 남는 깊이를 얇게 조절할 수 있어 잔류 결함층과 공핍층간의 간격을 증가시킨다. 그러므로 누설 전류를 감소시킬 수 있다. 따라서 소자의 전기적 특성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, a GeF is formed on a silicon substrate. Amorphize the surface by implanting ions B First, by implanting ions, BF It is possible to form a junction region having a lower sheet resistance and a shallower junction depth than in the case of using ions, and secondly, channeling can be prevented during boron implantation by amorphization of the surface. Third, Ge And F 3 times more beam current can be obtained than when ions are used, and productivity can be expected to increase. Fourth, it is possible to reduce the amount of fluorine injected to prevent an increase in contact resistance due to the fluorine compound generated during the subsequent heat treatment. Fifth, the process can be carried out in a high energy range, a wide range of energy that can be used to control the process, and a small change in the injection depth according to the energy change can be precisely controlled. Sixth, a thin amorphous layer or lattice damage layer can be easily formed. As a result, the depth at which residual defects remain after heat treatment can be adjusted to be thin, thereby increasing the gap between the residual defect layer and the depletion layer. Therefore, leakage current can be reduced. Therefore, there is an excellent effect that the electrical properties of the device can be improved.
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