JPH02191341A - Manufacture of mos field effect transistor - Google Patents

Abstract

PURPOSE:To avoid a channeling phenomenon created by ion implantation for forming source/drain diffused layers by a method wherein an amorphous region is formed over almost the whole region where a MOS-FET is to be formed before a gate electrode is formed. CONSTITUTION:In an n-type well region 2, Si<+> ions are implanted into almost the whole region where a MOS-FET is to be formed, i.e. a whole region which is surrounded by a field oxide film 3 and includes the depletion layer of a p<+>-n junction formed in a later process to form an amorphous region 5. Then a gate electrode 6 is formed at a required position on a gate oxide film 4. Successively, B<+> or BF ions are implanted by using the gate electrode 6 as a mask to form P<+>-type source/drain diffused layers 7 in the amorphous region 5. As the implanted region is amorphous at that time, a shallow junction can be formed without creating channeling.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a MOS field effect transistor;
In particular, it relates to a method of manufacturing the source/drain diffusion layer.

(#i (Future technology)) In order to increase the degree of integration of VLSI, in MO3 field effect transistors (hereinafter referred to as MOS-FET), the junction depth of the source/drain diffusion region is reduced due to the miniaturization of the gate length. Normally, ion implantation is used to form the diffusion region, and n'
/As+ or P+, p+ when forming a p junction
When forming a /n junction, B or BF2 is implanted.

It is widely known that the channeling phenomenon that occurs during ion implantation poses an obstacle when forming shallow junctions. Channeling is a phenomenon in which charged particles such as ions, when not incident on a single crystal, penetrate deeply through gaps in the atomic arrangement. This phenomenon becomes noticeable with ions having a small number of particles, and even if ion implantation is performed at low energy to form a shallow junction, the junction depth will not become very shallow. Therefore, it is difficult to form a p+/n shallow junction using a light element such as B by a normal ion implantation method, and attempts have been made to overcome this problem.

Conventionally, this type of technology includes (A) J, Appl,
Phys, 60 [7] (1986-1,0) (US) P.

2422-2438, and (B) Extended Abstracts on the 20 (EXTended
Abstracts of the 20th)
(19881international) Conference on Solid State Devices and
Material, Tokyo (Conference on So
l id 5tate [) cvices and H
materials, Tokyo > (1988
) (Japanese) P, 105-108. In these documents (A> and (B)), in order to prevent the channeling phenomenon, after forming the gate electrode,
By injecting Si+ into the region where the source/drain diffusion layer is to be formed, the region is made amorphous, and then 1(
1"2 etc. is proposed.

However, as shown in the above-mentioned document (A), the p+/n junction formed in this way has a very large junction leakage current under reverse bias compared to that formed by the normal ion implantation method. Therefore, it may not be practical.

The reason for this is that defects generated at the boundary between the amorphous region and the crystalline region by Si'' implantation remain as secondary defects even after annealing after BF2 implantation. Since they exist in the n-depletion layer, carriers generated there cause junction leakage.

On the other hand, as shown in the above document (B), G, BF
When annealing was performed after 2+ implantation, the secondary defect area was 81
Junction leakage current can be reduced by setting conditions for ion implantation such that ions enter the layer. However, as shown in FIG. 2 described in Document (B), under such ion implantation conditions, channeling of B F 2 in the lateral direction (direction perpendicular to the ion implantation direction) cannot be suppressed. There is a possibility that the region 10 deviates from the amorphous region 11 and invades below the gate electrode 12, and the effective gate length of the MOS-FET becomes short. In order to prevent this 1-t, Document (B) proposes obliquely implanting St+ into the regions where the source/drain is to be formed.

(Problems to be Solved by the Invention) However, the method for manufacturing the MOS-FET having the above configuration has the following problems.

That is, in order to form a shallow junction, if a method is used in which Si+ ions are implanted after forming the gate electrode to form an amorphous region, then B or BF- ions are implanted. In the normal ion implantation method in which the implantation angle is fixed at about 7°, as described in
Forming an amorphous region deep enough to prevent lateral channeling causes an increase in junction leakage current. On the other hand, if the amorphous region is made shallow, the effective channel length will decrease due to channeling.

Further, in order to implant 81 from an oblique direction into each of the regions where the source and drain are to be formed as in the above-mentioned document (B), modification of the ion implantation device such as making it rotatable is required. Furthermore, the position of the secondary defect region is P throughout the entire junction.
There is also the problem that in order to make the ion implantation fall within M, complicated adjustment work is required for the ion implantation conditions.

The present invention solves the problems that the conventional technology had, such as the increase in junction leakage current and the need for complicated adjustment work and modification of the ion implantation equipment in order to reduce the junction leakage current. A method for manufacturing a MOS-FET is provided.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a step of forming a field oxide film for element isolation on an n-type layer of a semiconductor substrate, and a gate oxide film on the n-type layer. Before or after the formation of Sl, Ge, Sn, As, P
and Sb to form an amorphous region of a predetermined depth in almost the entire region of the n-type layer where the MOS-FET is to be formed surrounded by the field oxide film; a step of forming a gate electrode at a predetermined position on the gate oxide film after forming the active region and the gate oxide film; and a step of forming B' and BF using the gate electrode as a mask.
2+ ions and forming a source/drain diffusion layer in the amorphous region are sequentially performed.

The predetermined depth of the amorphous region is such that the distance between the interface of the amorphous region on the n-type layer side and the source/train diffusion layer is greater than the thickness of the depletion layer formed by the p+/n junction. It is effective to make it larger.

Further, after forming the amorphous region, the B+ and BF
It is preferable that the process temperature in the steps up to the completion of either ion implantation in step 2 is lower than 600°C.

(Function) According to the present invention, since the MOS-FET manufacturing method is configured as described above, the MOS-FET is
-The step of forming an amorphous region with a predetermined depth in almost the entire region where the FET is to be formed also makes the area under the gate electrode formed thereafter amorphous, and when ion implantation of B or BF2 is performed in the later step, the ion It serves to prevent channeling phenomena in the direction of injection and in the lateral direction perpendicular thereto. Further, it serves to keep secondary defects that cause junction leakage current as far away from the source/drain diffusion layer as possible, thereby preventing an increase in junction leakage current. Moreover, it eliminates the need for modification of the ion implantation apparatus and complicated adjustment of implantation conditions as in the past.

Furthermore, making the depth of the amorphous region deeper than the thickness of the depletion layer formed by the p/n junction works to more reliably and effectively reduce the junction leakage current.

After forming the amorphous region, the process temperature is set to 60°C, for example, until the end of B or BF2+ implantation.
By keeping the temperature below 0° C., recrystallization of the amorphous region can be suppressed and channeling phenomenon can be reliably prevented.

Therefore, the above problem can be solved.

(Example) Figures 1(a) to (d) show MOS-
It is a manufacturing process diagram of FET. The manufacturing method will be described below in accordance with the order of the figures.

(1) Process shown in FIG. 1(a) First, an n-type layer such as an n-type well 2 is formed on a p-type Si semiconductor substrate 1 by a normal manufacturing process, and then an element isolation layer is formed on the substrate 1. A field oxide film 3 is formed. Ion implantation for channel stop is performed under field oxide film 3, if necessary. The depth of the n-type well 2 is usually about 2 μm, and the ion concentration is I x 1017
It should be about cm'. Further, the film thickness of the field oxide film 3 is approximately 600 nm.

Next, a gate oxide film 4 having a thickness of about 20 nm is formed between the field oxide films 3, and ions are implanted for V1 control to adjust the threshold voltage of the MOS-FET.

(2) Step of FIG. 1(b) Next, the area where the MOS-FET is to be formed in the n-type well 2, that is, the p/n junction surrounded by the field oxide film 3 and to be formed in a later process, is Sl is implanted into the entire region including the depletion layer to form an amorphous region 5. Here,
The amorphous region 5 is formed in the entire region where the MOS-FET is to be formed because secondary defects generated at the interface between the amorphous region 5 and the crystal region are located outside the depletion layer of the p/n junction. This is to ensure that.

For example, set the ion concentration of p-type well 2 to 1×1017 cm
', the depletion layer width when the reverse bias voltage is IOV is estimated to be 0.33 μm, so the amorphous region 5 with a depth of about 0.3 to 0.5 μm is Just form it. Now, if we want to form an amorphous region 5 with a depth of 0.5 μm, we will set Sl to 1.5×1.
The dose was about 0.015cm'', and the implantation energy was 5.0cm.
Ion implantation may be performed three times at approximately 0 keV, 200 keV, and 400 keV. With this ion implantation,
Field oxidation M3 with a film thickness of 0.5 μm or more
The area becomes amorphous except under the area. In addition, field oxidation M3 due to the horizontal spread of implanted ions
Intrusion downward is also observed, and the amorphous region 5 is formed from the edge of the field oxidation M3 by about 0.3 to 0.4 μm inward.

(3) Step of FIG. 1(c) Next, a gate electrode 6 is formed on the gate oxide film 4 at a predetermined position. The gate electrode 6 is usually made of n polysilicon or p
Although it is formed using polysilicon, care must be taken regarding the process temperature at that time. J., Appl., Phys.
±9 [7] (1978-7>(US) P, 3906
According to
For example, when a (100) substrate is used, the amorphous region 5 will crystallize in about 10 minutes when the wafer is exposed to a process temperature of 600°C.

Therefore, when using n polysilicon as the gate electrode,
Unlike the usual process, it is preferable to use CVD using Si2H6 and PH3 at a film-forming temperature of about 500 to 530C. Also, if p+ polysilicon is used as the gate electrode, Si2H6 and B2He or Si2H
It is preferable to form p+ polysilicon or non-doped polysilicon by CVD using only 6 and at a similar temperature. The non-doped polysilicon can be converted into p-polysilicon at the same time in the later process of ion implantation for source and drain.

After growing nl or p+ polysilicon on the gate oxide JII 4, a gate electrode 6 as shown in the figure is formed by applying normal photolithography and etching to this.
is obtained.

Next, using the gate electrode 6 as a mask, B Manaha BF2
+ ion implantation is performed to form a source/drain diffusion layer 7 made of a P layer in the amorphous region 5. For example, if the junction depth is approximately 100 to 130 nm, approximately 30 nm
Ion implantation of BF2+ of about 2.times.10.sup.15 cm.sup.-2 is performed with implantation energy of keV. At this time, since the implanted region is amorphous, a shallow junction is formed without channeling.

(4) Step of FIG. 1(d) Next, recrystallization annealing is performed at a high temperature of about 600 to 700°C. Next, annealing is performed at 900 to 1000 DEG C. for about 10 seconds using, for example, a lamp heating type annealing device to activate the various implanted dopants, thereby obtaining the structure shown in the figure.

Thereafter, a glabella insulating film (not shown) is formed thereon, predetermined contact holes are formed, and then a wiring layer made of aluminum or the like is formed, and a protective film is further formed thereon. At that time, if heat treatment is performed at a higher temperature than the activation annealing temperature or at a similar temperature for a long time in these steps after activation annealing, the implantation energy of B+ or BF2 may be adjusted to the desired level in these heat treatments. It is necessary to make adjustments so that a bonding depth of .

MOS-F of FIG. 1(d) manufactured as above
In ET, the secondary defects 8 remaining at the amorphous-crystal interface are at a depth of about 0.5 μm, and even near the field oxidation m3 closest to the source/drain diffusion layer 7, the separation distance is 0. It is about .3 to 0°4 μm. On the other hand, even if a reverse bias voltage of about 10 V is applied to the source/drain diffusion layer 7, the thickness of the depletion layer extending outside the diffusion layer 7 is about 0.3 μm or less. Therefore,
Since it is not affected by the secondary defect 8, the junction leakage current shows a value in a normal p4/n junction.

Furthermore, since the region immediately below the gate electrode 6 is also made amorphous, the lateral channeling phenomenon that was a problem in the above-mentioned document (B) can also be prevented.

Therefore, the problem of shortening the effective gate length is also solved. It is considered that the secondary defect 8 may increase the leakage current at the n-p junction between the n-type well 2 and the substrate 1, but the position of the secondary defect is one step away from the junction interface between the well 2 and the substrate 1. Since the thickness is about .5 μm, no increase in leakage current actually occurs.

Note that the present invention is not limited to the illustrated embodiment, and can be modified in various ways, such as the following modifications.

(b) In Figures 1(a) to (d), 81 ions are implanted after forming the gate oxide film 4, but the gate oxide film 4 can be formed at a low temperature of 530 to 600°C. When using a process, Sl 2 may be ion-implanted before forming the gate oxide film 4.

(b) In the above embodiment, Si was used as the amorphous ion.
Although the case where Ge+ is used is shown, instead of this, Ge+, Sn
+ can also be used. Furthermore, if the concentration of the n-type well 2 is appropriately adjusted, similar results can be obtained even when n-type ions such as As, P+, Sb+, etc. are implanted.

(c) In the above embodiment, the Si semiconductor substrate 1 was (10
0) substrate is used, but a (111) substrate may also be used. If a (111) substrate is used, the recrystallization rate can be reduced to about 1/25 of that of a (100) substrate, so a sufficient process time can be taken even if the gate electrode 6 is formed at a temperature of 600°C.

(d) As the material of the gate electrode 6, high-melting point metals such as Mo and W, which are considered promising for future VLSI as low-resistance gate electrode materials, can also be used.

Use of these is suitable for the present invention because the process temperature can be lowered. However, in this case, PSG, BPSG, NS, etc. are used as an ion implantation mask on the high melting point metal.
It is necessary to form an insulating film such as G. In addition, the gate electrode 6
The present invention can be applied to the structure of so-called LDD ellipse.

(E) In the above embodiment, a p-channel MOS is used in the n-type well 2.
Although the case where a -FET is fabricated has been exemplified, the same effect can be obtained in the present invention even if an IVIO8-FET is formed directly on an n-type substrate.

(Effects of the Invention) As described in detail above, according to the present invention, an amorphous region is formed in almost the entire area of the MOS-FET formation area before forming the gate electrode. When forming source/drain diffusion layers, B+ or BF2+
Even if ion implantation is performed, there is no risk of channeling phenomenon occurring.

Therefore, a predetermined shallow junction can be easily and reliably formed.

Further, by allowing secondary defects that may cause junction leakage current to exist outside the depletion layer formed by the p+/n junction, a shallow junction with low junction leakage current can be easily realized.

Furthermore, when a (100) substrate is used as the Si semiconductor substrate, B1 or BF, +
For example, the process temperature until the end of ion implantation is 600℃.
By making it lower, reliable shallow junctions can be more effectively obtained.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) show the MO in the embodiment of the present invention.
FIG. 2 is a manufacturing process diagram showing a method for manufacturing a type 3 field effect transistor, and FIG. 2 is a partial cross-sectional view of the manufacturing process of a conventional MOS type field effect transistor. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... N-type well, 3... Field oxide film, 4... Gate oxide film, 5... ...Amorphous region, 6...
- Gate electrode, 7... Source/drain diffusion layer, 8... Secondary defect.

Claims (1)

[Claims] 1. A step of forming a field oxide film for element isolation on an n-type layer of a semiconductor substrate, and a step of forming a field oxide film for element isolation on the n-type layer before or after forming a gate oxide film on the n-type layer. +, Sn^+, As^+, P^
A step of ion-implanting either + or Sb^+ to form an amorphous region of a predetermined depth in almost the entire region of the n-type layer where a MOS field effect transistor is to be formed surrounded by the field oxide film. a step of forming a gate electrode at a predetermined position on the gate oxide film after forming the amorphous region and the gate oxide film; and ionizing either B^+ or BF_2^+ using the gate electrode as a mask. A method for manufacturing a MOS type field effect transistor, comprising sequentially performing the steps of: implanting the amorphous region, and forming a source/drain diffusion layer in the amorphous region. 2. The method for manufacturing a MOS field effect transistor according to claim 1, wherein the predetermined depth of the amorphous region is between the interface of the amorphous region on the n-type layer side and the source/drain diffusion layer. A method for manufacturing a MOS field effect transistor in which the distance between the p^+/n junction and the depletion layer is greater than the thickness of the depletion layer formed by the p^+/n junction.