JP3120428B2 - Method for manufacturing MOS type semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS type semiconductor device, and more particularly, to a method for manufacturing a MOS type semiconductor device having two types of depletion MOS transistors having different electrical characteristics. About.

[Conventional technology]

Conventionally, a depletion MOS transistor has been widely used as a load MOS transistor for the purpose of resistance, a memory cell transistor as a code of a read-only memory, and the like.

In particular, the electrical characteristics required for the load MOS transistor may vary depending on the application.

For example, there is a circuit configuration shown in FIG. 2 as an output buffer often used in the nMOS circuit technology.

Of these, as the depletion transistor, a shallow depletion transistor that cuts off (saturates) and a deep depletion transistor that does not cut off are selectively used within a power supply voltage range of about 5 V. Recently, reduction in power consumption during use of the device has been demanded, so that a shallow depletion transistor has become the mainstream of the depletion transistor in the output buffer unit.

On the other hand, in a vertically stacked read-only memory in which data is written by a depletion transistor, a deep depletion transistor that does not cut off is used in order to increase the memory cell on-current for the purpose of increasing the read speed.

For the above reasons, in the low power consumption type read-only memory, the electrical characteristics of the depletion transistor of the output buffer unit and the depletion transistor of the memory cell in which data is written are different.

Conventionally, in order to form a depletion transistor having different electric characteristics, separate ion implantations are performed by a photomask process divided into two steps.

 This will be briefly described with reference to FIG.

As shown in FIG. 3A, a field oxide film 102 and a gate oxide film 103 are selectively formed on a P-type semiconductor substrate 101. Thereafter, using the photoresist 106 as a mask, for example, ³¹ P ⁺ ions are applied to a region where a shallow depletion transistor is to be formed in the future at 50 keV by 1.0 × 10 ¹²
By implanting about cm ^-2 , a shallow N ^- type diffusion layer 108 is formed.

Next, as shown in FIG. 3 (b), a photoresist film 11 is used for writing data to the memory cell transistor.
2 as a mask, for example, 1.0 × 10 ¹³ to ³¹ P ⁺ ions at 100keV
Inject about ^-2 cm. Thereby, the deep N ⁻ type diffusion layer 107
To form a deep depletion transistor that does not cut off.

Next, as shown in FIG. 3 (c), after the polycrystalline silicon gate electrodes 104a,... Are selectively formed, for example, ⁷⁵ As ⁺ ions are implanted using the polycrystalline silicon gate electrodes 104a,. As a result, an N ⁺ type diffusion layer 105 is formed.

Finally, as shown in FIG. 3 (d), an interlayer insulating film 109 is formed on the entire surface of the semiconductor substrate, and the contact opening 1 is selectively formed.
After forming 10, an aluminum electrode 112 is formed and the process is completed.

[Problems to be solved by the invention]

In the conventional method of manufacturing a MOS type semiconductor device described above, the threshold voltage is controlled by performing channel doping through separate photomask processes to form a shallow depletion transistor in an output buffer portion and a deep depletion transistor in a memory cell. This complicates the manufacturing process.

In addition, the data writing step is in a step before the polycrystalline silicon gate electrode forming step, and the loss is large in terms of TAT (step preparation period).

[Means for solving the problem]

A method of manufacturing a MOS type semiconductor device according to the present invention includes the steps of: forming at least two types of MOS transistors having different thicknesses of a gate insulating film on a semiconductor substrate of one conductivity type;
Among the transistors, at least two types of MOS transistors having different thicknesses of the gate insulating film are selected, and the impurity of the other conductivity type is simultaneously introduced into the one conductivity type semiconductor substrate from immediately above each gate electrode to control the threshold value. And forming a depletion MOS transistor having different electrical characteristics, wherein the impurity introduction is performed with the impurity introduction peak being the most of at least two types of MOS transistors having different thicknesses of the selected gate insulating films. The impurity introduction energy is set so as to be located in the thick gate insulating film, wherein the thickest gate insulating film is
It is a field oxide film formed on the one conductivity type semiconductor substrate.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (c) are cross-sectional views of a semiconductor chip arranged in a process order for explaining one embodiment of the present invention.

First, as shown in FIG.
A field oxide film 2 and a gate oxide film 3 are selectively formed on (silicon). Next, after selectively forming the polysilicon gate electrodes 4a to 4c, each of the polysilicon gate electrodes is self-aligned with, for example, ⁷⁵
As ⁺ ions are implanted to form an N ⁺ type diffusion layer 5.

Next, as shown in FIG. 1 (b), in the memory cell portion, impurities are introduced into the depletion transistor region in the output buffer portion in the transistor region where data is written. The impurities pass through the polycrystalline silicon gate electrodes 4a and 4b and are introduced into the surface of the P-type semiconductor substrate 1. Here, since the memory cell transistor needs to be formed as a deep depletion transistor, for example, about ³¹ × 10 ¹³ cm ^{−2 of 31} P ⁺ ions are implanted at 500 keV. This implantation energy is governed by the thickness of the polycrystalline silicon gate electrode, and is an optimum condition for a thickness of about 300 nm. However, the thickness of the gate oxide film 3 is 30 nm
And Almost all of the implantation amount is introduced into the semiconductor substrate to form a relatively high concentration, deep N ⁻ -type diffusion layer 7. on the other hand,
In the output buffer section, a shallow depletion transistor is used.
The structure exists on the field oxide film 2a having a thickness of m.

Therefore, under the above-described impurity ion implantation conditions, effectively 1.1 is formed on the substrate surface of the shallow depletion transistor.
Impurities of about 0 × 10 ¹² cm ⁻² are introduced, and desired electrical characteristics are obtained.

Finally, as shown in FIG. 1 (c), an interlayer insulating film 9 is formed over the entire surface of the semiconductor substrate, a contact opening 10 is selectively formed, and then an aluminum electrode 11 is formed.

〔The invention's effect〕

As described above, in the present invention, two types of gate insulating films, a field insulating film having a large thickness and an insulating film having a relatively small thickness, are employed for a shallow depletion transistor and a deep depletion transistor, respectively. By doing so, the threshold of the shallow depletion transistor and the threshold of the deep depletion transistor can be controlled in a single ion implantation step, and thus the number of manufacturing steps can be reduced.

[Brief description of the drawings]

1 (a) to 1 (c) are cross-sectional views of a semiconductor chip arranged in the order of steps for explaining an embodiment of the present invention, FIG. 2 is a circuit diagram of an output buffer, and FIGS. 3 (a) to 3 ( 4D is a sectional view of the semiconductor chip arranged in the order of steps for explaining the conventional example. 1,101 P-type semiconductor substrate, 2,102 Field oxide film, 3,103 Gate oxide film, 4,104 Polycrystalline silicon gate electrode, 5,105 N ⁺ -type diffusion layer, 6,106 Photoresist film, 7,107 Deep N ^- type diffusion layer, 8,108… shallow N ^- type diffusion layer, 9,109… interlayer insulating film, 10,110…
Contact opening, 11,111 …… Aluminum electrode, 112
...... Photoresist mask.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8234-21/8238 H01L 27/08 H01L 27/088-27/092

Claims (2)

(57) [Claims] A step of forming at least two types of MOS transistors having different thicknesses of a gate insulating film on a semiconductor substrate of one conductivity type; The MOS transistors are selected and the threshold control is performed by simultaneously introducing impurities of the other conductivity type into the semiconductor substrate of the one conductivity type from immediately above the respective gate electrodes, thereby controlling the depletion MO having different electrical characteristics.
Forming an S transistor, wherein the impurity introduction is performed such that the impurity introduction peak is located in the thickest gate insulating film of at least two types of MOS transistors having different thicknesses of the selected gate insulating film. A method of manufacturing a MOS type semiconductor device, characterized in that an impurity introduction energy is set in the semiconductor device. 2. The method according to claim 1, wherein said thickest gate insulating film is a field oxide film formed on said one conductivity type semiconductor substrate.