JPS60110167A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the performance and the integration of a semiconductor device by forming a low density region only one of regions to become source and drain regions, thereby preventing the deterioration of the characteristics of an element. CONSTITUTION:The first gate oxide film 37, a floating gate electrode 38, the second gate oxide film 39 and a control gate electrode 40 are sequentially formed on a substrate 31. Then, with the electrode 40 as a mask As ions are implanted vertically directly from above, and with the electrode 40 as a mask As ions are implanted in high dosage. Subsequently, the impurity is activated by a heat treatment, an n type region 41 made of a low density diffused layer 41a near a channel region is formed on one side of the surface of the substrate 31, and an n<+> type region 42 made of a high density diffused layer is formed on the other side. Finally, electrodes 44, 45 are formed, and an EPROM cell is manufactured.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to an MO8 semiconductor device in which a low 711 degree region is formed in the vicinity of a channel region only in either the source region or the drain region. It pertains to the manufacturing method.

[Technical background of the invention and its problems]

In recent years, there has been remarkable progress in microfabrication technology for 1MO8 semiconductor devices, and efforts have been made to shorten the channel length, particularly from the viewpoint of improving switching speed.

High integration is being promoted.

However, as the channel length becomes shorter, electric field concentration occurs in the channel region even when the voltage applied between the source and the J-'' layer is low.

Various problems have arisen in terms of device characteristics.

For example, rewritable read-only semiconductor memory (EPROM, Erasable Program
mmable Read Only Memory)
Conventionally, a memory cell having a structure as shown in FIG. 1 is known. In other words, 1 in the figure is, for example, a p-type silicon substrate, and a field oxide film 2 is formed on the surface of this substrate 1. Elements of the substrate 1 surrounded by this field oxide group 2 have mutual magnetic fields. N+ type source and drain regions 3 and 4 are formed separately from each other. Furthermore, a floating gate electrode 6 is formed on the channel region between the source and drain regions 3.4 through a first gate oxide film 5, and a second gate oxide film 7 is further formed on this floating gate electrode 6. A control gate electrode 8 is formed through the gate. Further, an interlayer insulating film 9 is deposited on the entire surface, and on this interlayer insulating film 9, a source electrode 10 is connected to the source region 3 through a contact hole, and a drain electrode 11 is connected to the drain region 4, respectively. is formed.

In the memory cell having such a configuration, information is written by applying a high voltage of, for example, +20 V or more to the drain electrode 11 and the control gate electrode 8, and causing an avalanche phenomenon near the drain region 4 by electrons flowing through the channel region.

This is done by trapping some of the electrons through the first gate oxide film 5 to the floating gate N pole 6. Further, for reading information, a voltage of, for example, about +5V is applied to the drain electrode 11 and the control gate electrode 8, and judgment is made by turning on or off the transistor as the threshold voltage changes depending on whether writing is being performed or not. .

However, when the channel length becomes short, electric field concentration occurs in the channel region even when a relatively low drain voltage (about +5 V) is applied during readout, and electrons are sufficiently accelerated.
It becomes possible to cause an avalanche phenomenon. For this reason 1
A situation similar to that in which electrons are trapped in the floating gate electrode 6 of a memory cell to which information is originally not written and information is written (erroneous writing of information) occurs.

Further, a conventional MOS transistor has a structure as shown in FIG. That is, 21 in FIG. 1 is, for example, a p-type silicon substrate, and a field oxide film 22 is formed on the surface of this substrate 21. This field oxide film 22
On the surface of the element region of the substrate 21 surrounded by
A gate electrode 26 is formed on the channel region between them with a gate oxide film 25 interposed therebetween. Further, an interlayer insulating film 27 is deposited on the entire surface, and on this interlayer insulating film 27, a source electrode @42B is connected to the source region 23 through a contact hole, and a drain electrode is connected to the drain region 24, respectively. 29 is formed.

Even in a conventional MOS transistor having such a structure, when the channel length becomes short, an avalanche phenomenon tends to occur due to electric field concentration in the channel region near the drain region 24 even when a relatively low drain voltage is applied. As a result, electrons are trapped in the gate oxide film 25, causing problems in device characteristics such as fluctuations in threshold voltage.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and by providing a low concentration region only in either the source or drain region, the electric field concentration in the channel region due to the shortening of the channel length can be alleviated. The present invention aims to provide a method for manufacturing a high-performance, highly integrated semiconductor device that can prevent deterioration of characteristics.

[Summary of the invention]

The method for manufacturing a semiconductor device of the present invention includes forming at least one layer of a gate electrode on a semiconductor substrate of a first conductivity type via a gate insulating film, and then applying an impurity of a second conductivity type from vertically above using the gate electrode as a mask. Low-dose ion implantation and high-dose ion implantation of the second conductivity type impurity from an oblique direction using the gate electrode as a mask, followed by heat treatment to diffuse low concentration near the channel region only in one of the regions that will become the source and drain regions. This method manufactures a semiconductor device provided with layers.

According to this method, a low concentration diffusion layer is provided in the vicinity of the channel region only in one of the regions that will become the source and drain regions in a simple process without the need for additional complicated steps such as mask alignment. The device can be manufactured. In such a semiconductor device, electric field concentration in the channel region can be effectively prevented.

For example, it is possible to prevent deterioration of confectionery characteristics such as erroneous writing in EPROM cells and fluctuations in threshold voltage in MOS transistors.

[Embodiments of the invention]

Example 1 An example applied to the manufacture of an EPROM cell according to the present invention will be described below with reference to the 31st section) to (dl).

First, field oxidation v32 is formed on the surface of the p-type silicon substrate 31 by selective oxidation. Next, a first layer is formed on the surface of the element region of the substrate 31 surrounded by the field oxide film
After forming a thermal oxide film 33, a first polycrystalline silicon film 34, which will become a floating gate electrode, is deposited on the entire surface.

Part of it is selectively etched. Continuing.

After performing thermal oxidation to form a second thermal oxide film 35 on the surface of the first polycrystalline silicon film 34, a second polycrystalline silicon film 36 that will become a control gate electrode is deposited on the entire surface (the third (a) As shown).

Next, by patterning the second polycrystalline silicon film 36, the second thermal oxide film 35, the lth polycrystalline silicon film 34, and the lth thermal oxide film 33 in sequence, a first polycrystalline silicon film 36 is formed on the substrate 3. A floating gate electrode 38 is formed via a gate oxide film 37, and a control gate electrode 40 is further formed on the floating gate electrode 38 via a second gate oxide film 39. Next, ions of phosphorus or arsenic are implanted from vertically above at a low dose of about 5 x 10"CM" using the control gate electrode 40 and the like stacked on top of the substrate 31 as a mask (as shown in FIG. 3(b)). ).

Next, using the control gate electrode 40 etc. stacked on the substrate 31 as a mask, arsenic is applied in an amount of about 3 x 10"an-" to form a source and a drain.

Ion implantation is performed at a high dose bt (shown in the same figure (C1)).

Next, the impurity is activated by B treatment, and a low humidity (n-type) diffusion layer 41a (impurity Q U
'I o t 'I Crn"-") and the adjacent high-a degree (n-type) diffusion layer IJb (impurity concentration 10")
A high a degree (n type) diffusion layer (impurity concentration II IO") is formed on the surface of the substrate 31 on the other side of the floating gate electrode 38, etc..
n+ type region 42 consisting of 10"cr:t-')
Each r, form. Continuing.

After depositing the interlayer insulating film 43 on the entire surface, contact holes are opened. Next, go to the entire surface! After depositing the film,
Patterning is performed to form electrodes 44 and 45, and HF R
Manufacturing an OM cell (as shown in FIG. 3(d)) - When performing the information insertion in the EPROM cell shown in FIG. 3 (d1), one of the 11-type regions 42
is used as a drain region, and the other n-type region 41 is used as a source region. Namely.

? The electrode 44 is used as a drain electrode, the electrode 45 is used as a source electrode, and a high voltage is applied to the (drain) electrode 44 and the control gate electrode 40. In this case, the potential in the channel region is equal to the source region, that is, n Mold area 41
Therefore, the electric field between the source and the drain is concentrated in the drain region, that is, the channel region near the !1+ type region 42, and the electric field in this region is (Generation of hot carriers (electrons, pole pairs) and floating goo due to avalanche phenomenon) - Electrons are injected into the four poles 38, and information is written.

On the other hand, when reading information, one n-type region 42 is used as a source region and the other n-type region 41 is used as a drain region, contrary to when writing information. That is, the electrode 44 is used as a source electrode and the electrode 45 is used as a drain electrode, and a voltage of +5V, for example, is applied between the source and drain, and +5V, for example, is applied to the control gate electrode 4o to control the transistor as the threshold voltage VTR changes. Information is read by turning on and off. At this time, since a low concentration (n type) diffusion layer 41B is provided near the channel region in the n type region 4 which becomes the drain region, it becomes the source region.

This region can take charge of part of the voltage applied between the drains. Therefore, the electric field concentrated in the channel region near the drain region can be significantly weakened.

Referring to FIGS. 4 and 5(a) and 5(fb), the electric field in the channel region near the drain region during reading of the above embodiment and the conventional EP ROM cell will be compared in more detail.

FIG. 4 is an explanatory diagram showing a depletion layer generated near the drain region during information reading. The shaded region in the figure is the depletion layer 46 generated in the E P ROM cell of the above embodiment, which extends on both sides of the interface between the low ari' (n-type) diffusion layer 41a and the channel region. . At this time, the distribution state of the electric field becomes as shown in FIG. 5(a).

On the other hand, if the low concentration (n-type) diffusion layer 41a is not provided (corresponding to the conventional EFROM cell shown in Figure '41), what about the depletion layer? It occurs only in the area shown by the dashed line in Figure 44, that is, on the channel area side. This is because the concentration of the high m degree < n type) diffusion layer 4Jb is high and has the same properties as metal. On this occasion,
The distribution state of the electric field is as shown in FIG. 5 (bl).

From Figure 5 (al and (bl), it is clear that if the potential difference between the source and drain is the same, the peak value of the electric field will be lower in Figure 5 (al), which has a wider distribution, than in Figure (b). i.e. paper i as part of the drain region.
By providing the (n-type) diffusion W141a, the electric field concentrated in the channel region near the drain region can be significantly weakened. Therefore, the generation of hot carriers due to the avalanche phenomenon in this region is suppressed,
Erroneous writing of information can be prevented.

Furthermore, since there is no possibility of erroneous writing occurring when reading information, the channel length can be made sufficiently short, thereby increasing the writing efficiency when writing one piece of information. Therefore, the values of write voltages such as drain voltage and control gate voltage that should be applied when writing information can be reduced compared to conventional ones.1 For example, the voltage applied when writing information and the voltage applied when reading information can both be about +5V. As explained above, in the method of the present invention, low-dose ion implantation from the vertical direction using the control gate electrode 40 etc. as a mask in the step of FIG. Control game) By performing high-dose ion implantation from an oblique direction using an M-pole 4θ etc. as a mask, it is possible to achieve high performance and high concentration of M as described above without adding complicated processes such as mask alignment in photolithography. EFROM cells can be manufactured.

Embodiment 2 An embodiment in which the present invention is applied to the manufacture of an n-channel MOS transistor will be described below with reference to FIGS. 6(a) to (C1).

First, a field oxide film 52 is formed on the surface of a p-type silicon substrate 51 by selective oxidation, and then a gate electrode is formed on the element region of the substrate 51 surrounded by the field oxide film 52 via a gate oxide film 53 according to a conventional method. form 54. next.

Using the gate electrode 54 as a mask, ions of arsenic, for example, are implanted from the vertical direction at a low dose of about 5xlOC1rL (as shown in FIG. 6(a)).

Next, using the gate electrode 54 as a mask, ions of arsenic, for example, are implanted obliquely at a high dose of about 3.times.1 O"cm" (as shown in FIG. 1B) to form a source and a drain.

Next, the impurities are activated by heat treatment to form the gate electrode 5.
On the surface of the substrate 5Z on one side of 4, there are a low concentration (n-type) diffusion layer 55a (impurity concentration: about 10 cm) near the channel region and an adjacent high-temperature + degree (n-type) diffusion layer 55b (impurity concentration: 10 cm). ~1O
crrL) on the surface of the substrate 51 on the other side of the gate electrode 54.
n-type source regions 56 made of .om) are respectively formed. Subsequently, after depositing an interlayer insulating film 57 on the entire surface, contact holes are formed. Subsequently, after depositing an AA film on the entire surface, it is patterned to form a source 9@5g and a drain electrode 59, thereby manufacturing an n-channel MO8 transistor (as shown in FIG. 5C).

In the MOS transistor shown in FIG. 6(C) IJ, FIGS. 4 and 5 (al, (bl)
Since the low concentration (n-type) diffusion layer 558 is provided in the vicinity of the channel region of the drain region 55 in the stud as explained using the above, electric field concentration in the channel region in the vicinity of the drain region 55 can be prevented. Fine MO8) It is possible to prevent deterioration of element characteristics such as fluctuations in threshold voltage of transistors.

In addition, the so-called LDD (Liglltly Dop
ed Drain and 5source) Structure of M
In the case of an OS) range nut, the low concentration diffusion layer on the source region side causes a decrease in mutual conductance (i!-m), but in the MO8 transistor shown in FIG. Since no low concentration diffusion layer is formed, the mutual conductance ()m
) can be avoided.

As explained above, according to the method of the present invention, a high-performance and highly integrated MOS transistor can be manufactured without adding complicated steps such as mask alignment using photolithography.

Note that in Examples 1 and 2, low-dose ion implantation was first performed and then high-dose ion implantation was performed, but this order may be reversed.

In addition, in the above explanation, an n-channel EFROM cell and a MOS transistor were described.

A similar effect can be obtained with a p-channel one.

〔Effect of the invention〕

As described in detail above, according to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a high performance and highly integrated semiconductor device without deterioration of device characteristics due to shortening of channel length.

[Brief explanation of the drawing]

Figure 1 is a front view of a conventional EP ROM cell, Figure 2 is a cross-sectional view of a conventional MOS transistor, and Figure 3 (al~(
dl is h in Example 1 of the present invention: A 1-cross-sectional view showing the manufacturing method of the FROM cell, and FIG. 4 is an explanation of a depletion layer generated during reading of the MP ROM cell manufactured in Example 1 of the present invention. Figure 5 (al and (bl) are the electric field distribution diagrams of the first embodiment of the present invention and the conventional E F ROM cell, respectively, and Figure 6 (al~ (C1 is the MOS in the second embodiment of the present invention) It is a -12 side view showing the manufacturing method of a transistor. 31. 51... P-type silicon substrate, 32, 52... Field oxide film, 33... 54 L thermal oxide film. 34... First polycrystalline silicon film, 35... Second thermal oxide film, 36... Second polycrystalline silicon film. 3-7... First gate oxide film, 38... Floating gate. Electrode, 39... Second gate oxide film. 40... Control gate electrode, 41a... Low concentration (n type) diffusion layer, 4zb... High concentration (n+ type) + diffusion layer, 41. ... n-type region, 42 ... n-type region. 43 ... interlayer insulating film, 44. 45 ... electrode, 46 ...
... Depletion layer, 53... Gate oxide film, 54... Gate electrode, 55a... Low concentration (n type) diffusion layer, 55b
... + high temperature 1i (n type) diffusion layer, 55... drain region. 56... Source region, 57... Interlayer insulating film, 58...
...Source electrode, 59...Drain electrode.

Claims (3)

[Claims] (1) forming at least one layer of gate electrode on a first conductivity type semiconductor substrate via a gate insulating film;
A step of ion-implanting a second conductivity type impurity from a vertical direction at a low dose using the gate electrode as a mask, and a step of ion-implanting a second conductivity type impurity at a high dose from an oblique direction using the gate electrode as a mask. Then, the impurities are activated by heat treatment, and a second conductivity type region consisting of a low concentration diffusion layer near the channel region and a high concentration diffusion layer adjacent thereto is formed on the substrate surface on one side of the gate electrode. 1. A method of manufacturing a semiconductor device, comprising the step of forming second conductivity type regions each comprising a highly doped diffusion layer on the other side of the substrate surface. (2) A method for manufacturing a semiconductor device according to claim m1, characterized in that a gate electrode is formed on a semiconductor substrate via a gate insulating film to manufacture a MOS transistor. (3) The first gate insulating film is placed on the semiconductor substrate via the first gate insulating film.
forming a gate electrode, further forming a second gate electrode on the first gate electrode with a second gate insulating film interposed therebetween;
A method for manufacturing a semiconductor device according to claim 1, characterized in that a FROM cell is manufactured;