JPS63131575A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a MOS transistor having high current supply capacity and high breakdown strength by forming a gate electrode to an inverted projecting shape and making the thickness of a gate insulating film at the side end section of a drain region in a gate region thicker than that of the central section of the gate region. CONSTITUTION:A gate electrode 3 is shaped to a p-type Si substrate 1 through a gate oxide film 2. The gate electrode 3 is constituted of the laminated films of a first layer polycrystalline silicon film 31, to which phosphorus is doped in high concentration, and a second layer polycrystalline silicon film 32 to which phosphorus is doped in concentration lower than the film 31. The gate electrode 3 is formed to an inverted projecting shape in such a manner that it is thermally oxidized after the laminated films are shaped to a pattern and the side surface of the first layer polycrystalline silicon film 31 is oxidized in the lateral direction in size deeper than the side surface of the second layer polycrystalline silicon 32. That is, the gate oxide film 2 is thickened substantially at end sections. Accordingly, high surface breakdown strength can be acquired.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a high voltage MOS transistor and a method for manufacturing the same.

(Prior Art) Electrically erasable and programmable nonvolatile semiconductor memories (E2PROMs) are known.

In E'' FROM, information is written or erased by applying a high electric field to a thin insulating film and injecting electrons or holes into the floating gate by a tunnel current.

The writing and erasing operations of this E2PROM require approximately 20V.
MOs used for peripheral circuits such as column gates or memory cell selection gates
It is necessary to increase the withstand voltage of the S transistor. The biggest problem with increasing the breakdown voltage of MOS transistors is surface breakdown. This means that the drain potential is at a high potential (20V
), when the gate potential is the ground potential (OV), surface breakdown occurs near the gate in the drain region due to a strong electric field.

As a MOS transistor structure that improves the surface breakdown voltage near the drain, LDD
(Lightly D 0ped Drain
) structure is known. This is to provide a low impurity concentration layer on the channel side of the drain region. This LDD
In this structure, the depletion layer easily extends in the vicinity of the gate in the drain region, which alleviates the concentration of electric field, and as a result, the surface breakdown voltage is improved.

However, in the LDD structure, the series resistance between the electrode contact portion of the drain region and the channel region increases due to the low impurity concentration layer.

- This causes a reduction in the current supply capability of the MOS transistor. Furthermore, it is difficult to miniaturize the MOS transistor because it is necessary to provide a low impurity concentration layer on the channel region side of the drain region with high impurity concentration.

(Problems to be Solved by the Invention) As described above, when attempting to increase the withstand voltage of MOS transistors by introducing the LDD II structure, there were problems in that the current supply capacity decreased and miniaturization became difficult. .

An object of the present invention is to provide a MOS transistor and a method for manufacturing the same that solves such problems.

[Structure of the Invention] (Means for Solving the Problems) The MOS transistor according to the present invention has a gate electrode of an inverted convex shape, and the thickness of the gate insulating film at the end of the gate region on the drain region side is equal to that at the center of the gate region. It is characterized by being thicker than that of . Specifically, the gate electrode is a product Sa of a first-layer polycrystalline silicon film with a high impurity concentration and a second-layer polycrystalline silicon film with a low impurity concentration, and the side surface portion of the first-layer polycrystalline silicon film of this laminated film is is laterally oxidized to be deeper than that of the second layer polycrystalline silicon film.

The method of the present invention for manufacturing such a MOS transistor involves forming a gate insulating film on a semiconductor substrate, and depositing a first polycrystalline silicon film with a high impurity concentration and a second polycrystalline silicon film with a low impurity concentration on top of the gate insulating film.
1. After forming a stack of polycrystalline silicon films and selectively etching the stacked film to form a gate electrode pattern, at least the side surface on the drain side is thermally oxidized to form a second polycrystalline silicon film on the side surface of the first layer polycrystalline silicon film. An oxide film is formed thicker than the side surfaces of the crystalline silicon film, and then impurity ions are implanted using the gate electrode as a mask to form source and drain diffusion layers.

(Function) According to the present invention, since the gate insulating film is thick at the edge of the gate region, the electric field between the gate and drain becomes small, so that when the gate potential is OV and a high potential is applied to the drain, The depletion layer extending from the drain side becomes wider, and the electric field applied to this depletion layer becomes smaller, resulting in a higher surface breakdown voltage.

Further, according to the method of the present invention, by taking advantage of the difference in oxidation rate caused by the difference in impurity concentration of the polycrystalline silicon film,
By stacking polycrystalline silicon films with different impurity concentrations, buttering, and thermal oxidation, it is possible to easily make the gate insulating film at the edge of the gate region thicker than at the center, making it possible to easily realize a high voltage MOS transistor. can. Further, unlike the LDD structure in which a low impurity concentration layer is provided at the end of the drain region on the gate side, miniaturization is easy.

<Example) Hereinafter, one aspect of the present invention will be explained in detail.

FIG. 1 is a cross-sectional view showing the structure of an n-channel MOS transistor according to one embodiment. A gate electrode 3 is formed on a p-type Si substrate 1 with a gate oxide film 2 interposed therebetween. The gate electrode 3 is composed of a laminated film of a first layer polycrystalline silicon film 31 doped with phosphorus at a high concentration and a second layer polycrystalline silicon 1132 doped with phosphorus at a lower concentration. This gate electrode 3 is formed by thermally oxidizing the laminated film after patterning the first layer polycrystalline silicon film 3! By oxidizing the side surfaces of the second layer polycrystalline silicon 1132 deeper and laterally than the side surfaces of the second layer polycrystalline silicon 1132, an inverted convex shape is formed. That is, the gate oxide film 2 is substantially thicker at the ends.

Reference numeral 4.5 denotes an n+ type scattered layer which becomes the drain and source and is formed by ion-implanting impurities using the gate electrode 3 as a mask. Reference numeral 6 denotes a CVD oxide film, in which a contact hole is formed, and ohmic electrodes 7 and 8 are formed in contact with the n1 type diffusion layer 4.5.

FIGS. 2(a) to 2(e) are cross-sectional views for explaining the manufacturing process of this MOS transistor. To explain the specific manufacturing process using this, first, a necessary element isolation region (not shown) is formed on the p-type 3i substrate 1, and then boron ions are implanted into the MOS transistor region to form a channel ion-implanted layer. 9 and then a 400 gate oxide 112 is formed by thermal oxidation. Next, 1000 layers of the first polycrystalline silicon film 31 are deposited thereon, and phosphorus is diffused in a phosphorus atmosphere at 900°C. First layer polycrystalline silicon 1
The phosphorus concentration in I31 is set to a high concentration of 1×1020/α3. At this time, the surface of the first layer of polycrystalline silicon [13+] is oxidized to form an oxide film 10 (FIG. 2(a)). Next, the oxidized 1110 is removed by etching with dilute hydrofluoric acid, and the first
A second polycrystalline silicon layer 1132 of 3,000 layers is deposited overlying the polycrystalline silicon film 31. After that, phosphorus was diffused for 5 minutes in a phosphorus atmosphere at 900°C, and the phosphorus concentration in the second polycrystalline silicon +1132 was reduced to 2X1012/α3.
shall be. At this time, an oxide film 11 is formed on the surface of the second layer polycrystalline silicon film 32 (FIG. 2(b)).

Thereafter, the laminated film of the first layer polycrystalline silicon film 3I and the second layer polycrystalline silicon film 32 is patterned by anisotropic dry etching to form a gate electrode (FIG. 2(C)).
). Subsequently, thermal oxidation is performed at 1000°C. At this time, since the first layer polycrystalline silicon l13t with a high phosphorus concentration has a faster oxidation rate than the second layer polycrystalline silicon 1132 with a lower phosphorus concentration, the first layer polycrystalline silicon I! The oxide film 1112t on the side surface of 03 is thicker than the oxide film 122 on the side surface of the second layer polycrystalline silicon film 32 (FIG. 2(d)). As a result, the gate electrode 3 has an inverted convex shape. In other words, the gate oxide film 2 is substantially thicker at the periphery than at the center.

After that, according to the usual process, using the gate electrode 3 as a mask, As is ion-implanted to form an n+ type scattering layer 45 in the drain and source regions, CVD oxide fi 16 is deposited, a contact hole is made in this, and an AR The ohmic electrodes 7.8 are formed by (FIG. 2(e)).

As described above, according to this embodiment, the gate insulating film is made thicker at the end of the gate electrode than at the center, thereby making it possible to obtain a high surface breakdown voltage.
Compared to the case where a high concentration layer and an adjacent low concentration layer are formed in the drain region or the source region as in the DD structure, there is no reduction in the current supply capability of the MOS transistor, and it is easy to miniaturize the MOS transistor. It is. Furthermore, according to this embodiment, by gate electrode buttering and thermal oxidation using two layers of polycrystalline silicon with different impurity concentrations, the above film thickness distribution can be created in the gate insulating film without the need for particularly complicated processing steps. It can be made to stand.

In the above embodiment, the difference in phosphorus diffusion time was used to differentiate the phosphorus concentration between the two polycrystalline silicon films, but the phosphorus supply IIr! It may be possible to make a difference between 1 and 1. The present invention is also effective in combination with an LDD structure. That is,
If an LDD structure is used, the advantage of miniaturization cannot be obtained, but if the present invention is combined with an LDD structure, a higher breakdown voltage can be achieved than in the case of a simple LDD structure alone.

[Effects of the Invention] As described above, according to the present invention, a MOS transistor with high current supply capability and high breakdown voltage can be obtained. Further, according to the method of the present invention, a special thickness distribution of a gate insulating film can be formed with good controllability without requiring complicated steps.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a Mo8)-transistor according to an embodiment of the present invention, and FIGS. 2(a) to 2(e) are sectional views for explaining the manufacturing process of the MOS transistor. 1... p-type SiN plate, 2... gate oxide film, 3...
・Gate electrode, 31...first layer polycrystalline silicon film, 3
2...Second layer polycrystalline silicon film, 4.5...n+ type resistive diffusion layer 6...CVD! ! 7.8... Ohmic electrode, 9... Ion implantation layer, 10.11... Oxide film. Applicant's agent Patent attorney Takehiko Suzue 1st issue Figure 2 (1) Figure 2 (2)

Claims (2)

[Claims] (1) The gate electrode is formed by patterning a laminated film of a first layer polycrystalline silicon film with a high impurity concentration and a second layer polycrystalline silicon film with a low impurity concentration, and the first layer polycrystalline silicon of this laminated film A MOS transistor characterized in that a film portion is laterally oxidized deeper than a second layer polycrystalline silicon film portion. (2) A step of forming a gate insulating film on a semiconductor substrate, and laminating a first layer polycrystalline silicon film with a high impurity concentration and a second layer polycrystalline silicon film with a low impurity concentration thereon, and the formed laminated layer. A process of selectively etching the film to form a gate electrode pattern, and thermally oxidizing at least the side surfaces of the formed gate electrode to form a second polycrystalline silicon film on the first layer polycrystalline silicon film.
Manufacturing a MOS transistor characterized by comprising a step of forming an oxide film thicker than a layered polycrystalline silicon film portion, and a step of ion-implanting impurities using the gate electrode as a mask to form source and drain diffusion layers. Method.