JPS60110171A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify the manufacturing steps by forming a low density diffused layer near a channel region only in one of the regions to become source and drain regions of a memory cell. CONSTITUTION:A gate electrode 43 made of a control gate electrode 56 and a floating gate electrode 54 of an EPROM cell and gate electrodes 44, 58 of an MOS transistor are formed to cross perpendicularly to each other. High dosage ion implantation is performed oblique from above in parallel with the gate longitudinal direction of the electrode 56 and low dosage ion implantation is performed vertically directly from above to provide a low density (n type) diffused layer 59a near the channel region only in one of the regions to become source and drain regions of the EPROM cell and hence the region 59. Thus, the EPROM cell for effectively preventing the erroneous readout and the normal MOS transistor are formed in an extremely simple steps.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a read-only semiconductor memory device in which information can be rewritten.

[Technical background of the invention and its 5 problems] Read-only semiconductor memory with rewritable information (EP
ROM, eraable programmab
As a memory cell for the ReadOnly Memory (ReadOnly Memory), a type having a T-shaped structure as shown in FIG. 1 is conventionally known.

That is, 1 in the figure is, for example, a p-type silicon 1-in board;
A field oxide film 2 is formed on the surface of this substrate 1. The substrate 1 surrounded by this field oxide film 2
On the surface of the element region, n+W source and drain regions 3.4 are formed electrically isolated from each other. Further, a floating gate electrode 6 is formed on the channel region between the source and drain regions 3 and 4 with a first dirt oxide film 5 interposed therebetween, and a second dirt oxide film 7 is further formed on this floating gate electrode 6. A control gate electrode 8 is formed. Further, an interlayer insulating film 9 is deposited on the entire surface, and source electrodes 10 are formed on the interlayer insulating film 9, each connected to the source region 3 through a contact hole.
And a drain electrode 11 connected to the drain region 4 is formed.

In a memory cell having such a configuration, information is written by applying a high voltage of, for example, +20V or more to the drain electrode 11 and the control dart electrode 8, and causing an avalanche phenomenon in the vicinity of the seed drain region 4 by electrons flowing through the channel region. This is done by injecting some of the electrons into the 70-ring dirt electrode 6 through the first dirt oxide film 6 and trapping them. In addition, for reading information, for example, +5
A voltage of approximately V is applied, and a judgment is made based on whether the transistor is turned on or off as the threshold voltage changes depending on whether filling is being performed or not. Furthermore, once the information has been written down, it can be erased by irradiating it with ultraviolet light, and after the information has been erased, it is possible to rewrite the information.

Incidentally, in the current field of semiconductor devices, there are some remarkable advances in element microfabrication technology, and in particular, from the viewpoint of improving switching speed, reduction of channel length is being promoted. This trend is no exception in the field of EPROMs, and the channel length of each memory cell is becoming increasingly smaller. However, while the channel length has been reduced, problems have arisen in terms of characteristics. That is, as the channel length decreases, the source.

The voltage applied between the drains increases the electric field generated within the channel region. Therefore, even when a relatively low voltage (approximately +5 V') drain voltage and dart voltage, such as those used for reading EPROMs, are applied, electrons flowing from the source region to the drain region are accelerated by an amount of light, and the drain region It has energy that can cause an avalanche phenomenon in the nearby channel region.

Therefore, in EPROMs that are highly integrated and have short channel lengths, when information is retrieved, electrons are trapped in the floating gate electrodes of memory cells to which no information is originally written. , it ends up in the same state as when the information was written. Such a phenomenon is usually referred to as erroneous writing of information, and when a device as shown in FIG. 1 is highly integrated, the occurrence of erroneous writing cannot be prevented unless the power supply voltage is lowered.

However, when the power supply voltage is lowered, the f# information reading speed from the memory cells decreases.

Therefore, in order to eliminate the above-mentioned drawbacks, an EPROM cell as shown in FIG. 2 has been proposed. 21 in the diagram
is, for example, a PM silicon substrate, and a field oxide film 22 is formed on the surface of this substrate 21. On the surface of the element region of the substrate 21 surrounded by the field oxide film 22, an n+ type region 23 consisting of a high concentration (n+ type) diffusion layer that is electrically separated from each other and becomes a source and drain region.
, an n-type region 24 is formed which includes a low concentration (n type) diffusion layer 24a near the channel region and a high concentration (n+ type) diffusion layer 24b in instant contact therewith. Said meter area 23
The impurity concentration of the low concentration (n-type) diffusion layer 24a is set to about 1019 to 10ctn, whereas the impurity concentration of the low concentration (n-type) diffusion layer 24a is set to about 1019 to 10ctn. Also, n
A floating dirt electrode 26 is formed on the channel region between the + type region 23n2fi region 24 via a first dirt oxide film 25, and a second dart electrode 26 is formed on the 70- type dirt electrode 26. A control gate electrode 28 is formed with an oxide film 27 interposed therebetween. Also,
An interlayer insulating film 29 is deposited on the entire surface, and on this interlayer insulating film 29 are formed electrodes 3o and n-type regions 2 connected to the n+ type region 3 through contact holes, respectively.
A polarization 31 connected to 4 is formed.

That is, the EPROM cell shown in FIG. 2 is a source.

One n-type region 24, which will become the drain region, is connected to a low-concentration (n-type) diffusion layer 24m near the channel region and a high-concentration (n+ type) diffusion layer 24m.
It is formed by the diffusion layer 24b.

Note that the n+ type region 23 of the EPROM cell shown in FIG.
For example, as shown in FIG. 3(-), the n-type region 24 is formed by ion-implanting n-type impurities at a high dose from an oblique direction using the control dirt electrode 28 stacked on the substrate 21 as a mask, as shown in FIG. 3(-). As shown in b), using the control gate electrode 28 etc. as a mask, n is applied from the vertical direction at a low dose.
After ion implantation of type impurities, the impurities can be formed by heat treatment to activate the impurities.

In the EPROM cell as shown in FIG. 2, when performing 8-packing of information, one n+ type region 23 is used as a drain region and the other n type region 24 is used as a source region. That is, the electrode 30 is used as a drain electrode, the electrode 31 is used as a varnish electrode, and a high voltage is applied to both the drain electrode 30 and the control electrode 28. in this case,
The potential in the channel region is equal to or very close to the potential in the source region, that is, the nm region 24. This is no good, sauce.

The electric field between the drains is concentrated between the drain and the head, that is, n
In the channel region near the mold region 23, there is a strong phenomenon, and in this region, the avalanche phenomenon occurs and electrons are injected into the floating dirt electrode 26, and information is written.

On the other hand, when reading information, one n+ type region 23 is used as a source region and the other n type region 24 is used as a drain region, contrary to when writing information. That is, the electrode 30 is a source electrode, the electrode 3 is a drain electrode, the drain electrode 31 and the control r-) electrode 2
By applying an appropriate voltage of about +5V to both terminals 8 and 8, the transistors are turned on as the threshold voltage changes.

The off information is read out. At this time, since a low concentration (n-type) diffusion layer 24a is provided in the n-type region 24, which becomes the drain region, near the channel region, this region takes charge of part of the voltage applied between the source and drain. I can do it.

Therefore, the electric field concentrated in the channel region near the drain region can be significantly weakened.

Referring to FIGS. 4 and 5(a) and 5(b), the electric field in the channel region near the drain region during reading of the EPROM cells shown in FIGS. 1 and 2 will be compared in more detail.

FIG. 4 is an explanatory diagram showing a depletion layer generated near the drain region during information reading. The shaded area in the figure is the second
The depletion layer 32 generated in the illustrated EPROM cell is
It extends to both sides of the interface between the low concentration (n-type) diffusion layer 24m and the channel region. At this time, the distribution state of the electric field becomes as shown in FIG. 5(a).

On the other hand, when the low concentration (n-type) diffusion layer 24& is not provided (corresponding to the EPROM cell shown in FIG. 1), the depletion layer is only in the region shown by the dashed line in FIG. 4, that is, on the channel region side. Occur.

This is because the high concentration (n+ type) diffusion layer 24b has a high concentration and has the same properties as metal. At this time, the distribution state of the electric field becomes as shown in FIG. 5(b).

As shown in Figures 5(a) and 5(b), if the potential difference between the source and drain is the same, the peak value of the electric field in Figure 5(a) has a wider distribution than that in Figure 5(b). It is clear that it will be lower. That is, by providing the low concentration (n-type) diffusion layer 24m as a part of the drain region, the electric field concentrated in the channel region near the drain region can be significantly weakened. Therefore, the generation of hot carriers due to the avalanche phenomenon in this region is suppressed, and erroneous writing of information can be prevented.

Furthermore, since there is no risk of erroneous writing during information reading, the channel length can be shortened to an optical length, thereby increasing information writing efficiency. Therefore, the values of write voltages such as drain ratio and control gate voltage that should be applied when writing information can be reduced compared to conventional ones. For example, the voltage applied when writing information and the voltage applied when reading information are both +5V. It can be done to a certain extent.

As explained above, by using the method shown in FIGS. 3(a) and (b), the high-performance EP shown in FIG.
ROM cells can be manufactured.

By the way, the above explanation is valid for the memory confectionery (EPROM cell) that stores information among the elements constituting a semiconductor memory, but when considered as an LSI, external signals are transmitted to each memory element (EPROM cell). A low concentration (n-type) diffusion layer in the vicinity of the channel region is not required for so-called peripheral circuit elements around the memory element group, particularly transistors.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to manufacture a semiconductor memory device in which a low concentration diffusion layer is provided in the vicinity of a channel region only in one of the regions that become the source and drain regions of a memory element using a simple process. This is an attempt to provide a possible method.

[Summary of the invention]

In the method for manufacturing a semiconductor memory device of the present invention, a dart electrode of a memory element and a dart electrode of a transistor of a peripheral circuit are formed so that the dart length directions are orthogonal to each other, and the dirt electrodes are formed diagonally from above parallel to the dart length direction of the memory element. This method is characterized by ion-implanting impurities of a conductivity type opposite to that of the substrate at a high dose, and implanting impurities of a conductivity type opposite to the substrate from vertically above at a low dose.

According to this method, in the memory element, a region is created in which impurity ions implanted at a high dose from diagonally above do not reach the substrate because they are blocked by the dirt electrode, and this region is located in the low concentration diffusion layer near the channel region. However, since the dirt electrodes of the peripheral circuit transistors are formed in a direction perpendicular to the dirt electrodes of the memory element, high-dose ion implantation is not blocked by the dirt electrodes, and no low concentration diffusion layer is formed. Further, there is no need to add a photolithography process to manufacture such a semiconductor memory device.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 is a plan view of an EPROM LSI. Usually, the central part is the memory element area 4, and the outside is the peripheral circuit area 42.
It becomes. This memory element area 41 has an EPROM
A cell (indicated by MC in the figure) and a transistor (for example, MC8) (indicated by Tr in the figure) are formed in the peripheral circuit region 42, respectively.

The above EPROM cell (MC) part is enlarged in Figure 87, and the MC8l-transistor (Tr) part is enlarged in Figure 8.
Each is shown in the figure. EP as shown in Figures 7 and 8.
The two-layer dart electrode 43 of the control gate electrode and floating gate electrode of the ROM cell and the dart electrode 44 of the MC8 transistor are formed to be perpendicular to each other.

Below, Figure 9 (a
) to (d) and the cross section along the X-X line in Figure 8 @1
The method of the present invention will be explained in detail with reference to FIGS. 0(a) to (d).

First, a field oxide film 5 is formed on the surface of a p-type silicon substrate 51.
form 2. Next, according to a conventional method, a floating dirt electrode 54 is formed on the substrate 5 surrounded by the field oxide film 52 in the memory element region via the first dirt oxide film 53, and further on the floating r-) electrode 54. A control dirt electrode 56 is formed through the second dirt oxide film 55. Further, in the peripheral circuit region, a dirt electrode 58 is formed on the substrate 51 surrounded by the field oxide film 52 with a dirt oxide film 57 interposed therebetween. In addition, M.O.
The f-to electrode 58 of the S transistor may be formed from a first layer of r-to electrode material (for example, polycrystalline silicon) or may be formed from a second layer of dart electrode material (see FIG. 9). a)
and FIG. 10 (, ).

Next, the control dart electrode 56 of the EPROM cell
etc. and MC8) Mask the dart electrode 58 of the transistor and apply arsenic, for example, to the source and drain parallel to the dart length direction of the control dirt electrode 56 of the EPROM cell (indicated by arrows in FIGS. 6 to 8) from diagonally above. For formation, ions are implanted at a high dose. At this time, in the memory element region, arsenic ions are not implanted in the vicinity of the channel region, which is one of the regions that will become the source and drain regions because it is blocked by the control dart electrode 56 and the like.

On the other hand, in the peripheral circuit area, the dart electrodes are provided perpendicularly to the control dirt electrodes 56 of the EFROM cells, so that the arsenic ions are not blocked by the dirt electrodes 58 (see FIG. 9). b) and 10th
Figure (b) shown).

Next, the control gate electrode 5 of the EPROM cell
6 etc. and MOS) Using the dirt electrode 58 of the transistor as a mask, ions of, for example, arsenic are implanted vertically at a low dose (as shown in FIGS. 9(C) and 10(C)).

Next, the thin film is activated by heat treatment, and in the memory element region, a low concentration (n-type) diffusion layer 59m near the channel region is formed.
Next, an n-type region 59 made of a high concentration (n+ type) diffusion layer 59b and a meter-shaped region 60 made of a high concentration (n+ type) diffusion layer are formed. Furthermore, layered source and drain regions 61 and 62 are formed in the peripheral circuit region. Subsequently, after depositing a glabellar insulating film 63 on the entire surface, contact holes are formed. Subsequently, after depositing an At film on the entire surface, patterning is performed to form an At wiring 64. ..., forming E
EPR with PROM cell and MOS) transistor
Manufacture OM LSI (Fig. 9(d) and Fig. 10(
d) As shown).

According to the method of the present invention, the control gate electrode 56 etc. of the EPROM cell and the dart electrode 58 of the MOS transistor are formed so as to be perpendicular to each other, and the control gate electrode 56 etc. is diagonally parallel to the dart length direction. By performing high-dose ion implantation from above and low-dose ion implantation from vertically above, it is possible to eliminate the need for an additional photolithography process (one of the regions that will become the source and drain regions of the EPROM cell, that is, the n-type region). A low concentration (n-type) diffusion layer 59h can be provided in the vicinity of the channel region only in 59. Therefore, an EPROM cell that can effectively prevent erroneous writing and a normal MOS transistor can be formed in an extremely simple process. be able to.

Incidentally, in the above embodiment, the low-dose ion implantation of arsenic was performed after the low-dose ion implantation, but this order may be reversed.

Further, in the above explanation, an n-channel type has been described, but it goes without saying that similar effects can be obtained with a p-channel type.

〔Effect of the invention〕

As detailed above, according to the present invention, the source of the memory element,
It is possible to provide a method for manufacturing a high-performance, highly integrated semiconductor memory device in which a low concentration diffusion layer is provided in the vicinity of a channel region only in one of the regions that will become the drain region, using a simple process. .

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a conventional EPROM cell, Fig. 2 is a cross-sectional view of an improved EPROM cell, and Figs.
) is a cross-sectional view showing the manufacturing method of the EPROM cell shown in FIG. The electric field distribution diagram of the EPROM cell shown in FIG. 2,
Figure 6 is a plan view of the EFROM LSI, Figures 7 and 8.
Each figure shows an EPR produced in an embodiment of the present invention.
OM cell and MOS) Plane view of Runnostar, Figure 9 (
, ) to (d) are cross-sectional views showing the manufacturing process of the EPROM cell portion in the embodiment of the present invention, and Fig. 10<=> to (d)
1 is a cross-sectional view showing the manufacturing process of a MOS transistor portion in an embodiment of the present invention. 41...Memory element area, 42...Peripheral circuit area,
43... EPROM cell f-) electrode, 44...M
OS) dirt electrode of transistor, 51... p-type silicon substrate, 52... field enemy film, 53... first dirt oxide film, 54... floating r-) electrode, 55... Second dirt oxide film, 56... Control gate electrode, 57... Dirt oxide film, 58...
- Dirt electrode, 59a...Low concentration (n flood) diffusion layer, 5
9b...High concentration (n+ type) diffusion layer, 59...n type 'region, 60... layer type region, 61.62... n+ type source. Drain region, 63... Interlayer insulating film, 64... At
wiring. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 S3 \ \ \ \ \ \ \ \ \ \ Figure 4 4 Figure 5 Figure 6 Figure 7 Figure 8 X

Claims (1)

[Claims] In order to manufacture a read-only semiconductor memory device in which information can be rewritten, there are two steps: forming a dirt electrode of a memory element and a dirt electrode of a transistor of a peripheral circuit so that the dart length directions are perpendicular to each other; A process of ion-implanting an impurity of a conductivity type opposite to that of the substrate at a high dose from diagonally above parallel to the dart length direction of the element, and a process of ion-implanting an impurity of a conductivity type opposite to that of the substrate at a low dose from vertically above. A method of manufacturing a semiconductor memory device, comprising: