JPH0722187B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a read-only semiconductor memory (EPROM: Erasable Programmable Read) having a floating gate and a control gate and capable of rewriting information.
The present invention relates to a method for manufacturing a semiconductor device in which a memory cell (only memory) and a MOS transistor coexist.

[Technical background of the invention]

As a memory cell used for an EPROM, a memory cell having a structure shown in the sectional view of FIG. 10 is conventionally known. In the figure, 1 is a p-type silicon single crystal substrate, 2 is a field insulating film, 3 and 4 are n ⁺ type source and drain regions separately provided on the surface region of the substrate 1, and 5 is a gate insulating film. , 6 is a floating gate electrode provided on the gate insulating film 5, 7 is an insulating film provided on the floating gate electrode 6, 8 is a control gate electrode further provided on the insulating film 7, 9 is a source electrode, Reference numeral 10 is a drain electrode, and 11 is an insulating film.

In the memory cell having such a configuration, the drain electrode 10
By applying a high voltage, for example, +20 V or more to both the control gate electrode 8 and the control gate electrode 8, the source region 3 to the drain region 4
Due to the electrons flowing toward the drain region 4
Causes an impact ionization (avalanche) phenomenon in the vicinity of. Electrons are injected into the floating gate electrode 6 through the gate insulating film 5 and trapped in some of the electron-hole pairs generated at this time. This operation is referred to as writing of information. Since electrons are trapped in the floating gate electrode 6 when information is written, the threshold voltage V _TH becomes high and a read voltage is applied to the control gate electrode 3. However, this memory cell does not turn on. In addition, the state that information is not written,
That is, the threshold voltage V _TH remains low in a state where electrons are not trapped in the floating gate electrode 6 and easily turns on at this time. In such a memory cell, a state in which information is written and a state in which information is not written can be distinguished. Further, the information once written can be erased by irradiating with ultraviolet rays, and the information can be rewritten after the information is erased.

[Problems of background technology]

By the way, in the field of semiconductor devices at present, the fine processing technology of elements is remarkable, and in particular, from the viewpoint of improving the switching speed, the reduction of the channel length is being promoted. This tendency is no exception in the field of EPROM, and the channel length of each memory cell is being reduced more and more, but there is a problem in terms of characteristics. That is, as the channel length decreases, the electric field generated in the channel region becomes stronger due to the voltage (potential difference) applied between the source and the drain. Therefore, even when a drain voltage and a gate voltage of a relatively low voltage (about +5 V) used for reading an EPROM are applied, the electrons flowing from the source region to the drain region are sufficiently accelerated, and the electrons in the vicinity of the drain region are accelerated. It has energy that can cause the impact ionization as described above in the channel region. Therefore, in the highly integrated EPROM with a short channel length, when reading information, electrons are originally trapped in the floating gate electrode of the memory cell in which no information is written,
Eventually, the result will be the same as when the information was written. Such a phenomenon is usually called erroneous writing of information, and when the memory cell having the configuration shown in FIG. 10 is highly integrated, erroneous writing cannot be prevented unless the power supply voltage is lowered. However, if the power supply voltage is lowered,
The information read speed from the memory cell is reduced.

[Object of the Invention]

The present invention provides an EPROM cell that has a high switching speed, is less likely to cause erroneous writing of information, and can reduce the value of the write voltage to be applied at the time of writing information, and a threshold voltage variation due to a decrease in channel length. Another object of the present invention is to provide a method of manufacturing a semiconductor device including a MOS transistor having improved reliability.

[Outline of Invention]

A semiconductor device according to the present invention comprises a step of forming a control gate electrode on a part of the surface of a semiconductor substrate of the first conductivity type through a thin insulating film, and a step of forming an insulating film around the control gate electrode. A step of covering the entire surface with a conductive material film, and etching the conductive material film by an anisotropic etching method to leave the conductive material film in contact with the insulating films corresponding to both side surfaces of the control gate electrode. And a step of doping the surface of the semiconductor substrate with an impurity giving a relatively high concentration of the second conductivity type by using the control gate electrode and the remaining conductive material film as a mask, and on both side surfaces of the control gate electrode. A step of forming a floating gate electrode made of the remaining conductive material film by etching away one of the remaining conductive material films and etching the other; And a step of doping the surface of the semiconductor substrate with an impurity imparting a conductivity type. According to the present invention, as described above, the EPROM has a high switching speed, is less likely to cause erroneous writing of information, and can reduce the value of the writing voltage to be applied at the time of writing information.
It is possible to obtain a semiconductor device including a cell and a MOS transistor having improved threshold voltage variation due to a decrease in channel length and improved reliability.

Example of Invention

Hereinafter, an embodiment of the present invention will be described in detail with reference to the manufacturing steps shown in FIGS. 1 to 8 and 9. 1 (a) to 8 (a) are sectional views of the memory cell portion of the EPROM, and FIGS. 1 (b) to 8 (b) are sectional views showing the MOS transistor portion.

First, the p-type silicon substrate 101 is selectively oxidized to form a field oxide film 102 for separating the surface of the substrate 101 into islands, and then thermally oxidized in an oxidizing atmosphere at 900 to 1000 ° C. to form islands. An oxide film 103 having a thickness of about 250 Å was formed on the surface of the substrate 101. Subsequently, a 3000 Å-thick n-type or p-type impurity-doped polycrystalline silicon film was deposited on the entire surface by LPCVD, and this was patterned to form a control gate electrode 104a and a gate electrode 104b made of polycrystalline silicon. (Shown in FIG. 1).

Then, the control gate electrode 104a and the gate electrode 104b, which are thermally oxidized in an oxidizing atmosphere at 900 to 1000 ° C. and made of polycrystalline silicon.
After growing an oxide film 105 having a thickness of 500Å around the periphery of the substrate, a polycrystalline silicon film 106 doped with an n-type or p-type impurity having a thickness of 3500Å was deposited again on the entire surface by LPCVD (see FIG. 2). . Subsequently, the polycrystalline silicon film 106 was removed by etching by the anisotropic etching method, for example, the reactive ion etching method (RIE method). At this time, the thickness of the control gate electrode 104a and the gate electrode 104b in the height direction was effectively large, so that the polycrystalline silicon 106 'remained around the film (FIG. 3).

Then, the field oxide film 102, the control gate electrode 104a,
Using the gate electrode 104b and the remaining polycrystalline silicon 106 'as a mask, an n-type impurity such as arsenic is implanted and the energy is 50 ke.
P-type silicon substrate 101 under the conditions of V and dose 1 × 10 ¹⁵ cm ^-2
Ions were implanted on the surface (shown in FIG. 4). Subsequently, the remaining polycrystalline silicon 106 'is selectively etched away using the photoresist pattern 107 formed by the photo-etching method as a mask, and the floating gate electrode 108 located on one side of the control gate electrode 104a and only around the element portion is Was formed (shown in FIG. 5).

Next, after removing the photoresist pattern 107, the field oxide film 102, the control gate electrode 104a, and the gate electrode 104 are removed.
b and the floating gate electrode 108 are used as a mask to implant an n-type impurity such as phosphorus with an energy of 60 keV and a dose of 1 × 10 ¹² c
Ions were implanted into the surface of the silicon substrate 101 under the condition of m ⁻² (shown in FIG. 6). Subsequently, thermal oxidation was performed in an oxidizing atmosphere at 900 to 1000 ° C. to grow an oxide film 109 having a thickness of 500 Å around the floating gate electrode 108. At this time, the ion-implanted arsenic and phosphorus in the steps of FIGS. 4 and 6 were activated, and n-type impurity diffusion layers 110 to 113 were formed on the surface of the p-type silicon substrate 101. Here, since the implantation dose amount is large in the portion where arsenic is ion-implanted in the steps of FIGS. 4 and 6, the high-concentration diffusion layers 110, 111 ₁ , 112 ₁ , 113 ₁ are formed, Since the implantation dose is relatively small in the portion where only phosphorus is ion-implanted, the low-concentration diffusion layers 111 ₂ and 11
2 ₂ and 11 3 ₂ were formed (shown in FIG. 7). Subsequently, a SiO ₂ film 114 is deposited on the entire surface by the CVD method, and the contact hole 11
After opening 5, the Al film is vapor-deposited and patterned to
Electrodes 116 to 119 were formed to manufacture EPROM memory cells and MOS transistors (shown in FIGS. 8 and 9). In addition,
FIG. 9 is a plan view of FIG.

Therefore, according to the present invention, as shown in FIGS. 8 and 9, the p-type silicon substrate 1 separated by the field oxide film 102 is formed.
On the surface of the island region of 01, n-type diffusion regions 110 and 111 to be source or drain regions are provided separately from each other, and the gate oxide film 103 is formed on the substrate 101 region (channel region) between these n-type diffusion regions 110 and 111. Through the control gate electrode 104a,
A semiconductor device having an EPROM memory cell having a structure in which the floating gate electrode 108 is provided and the control gate electrode 104a and the floating gate electrode 108 are insulated from each other with the oxide film 105 interposed therebetween can be obtained.

In the memory cell having such a configuration, when writing information, one of the n-type diffusion regions 110 is a drain region,
The other n-type diffusion region 111 is used as a source region.
That is, using the electrode 116 as a drain electrode and the electrode 117 as a source electrode, a high voltage is applied to both the drain electrode 116 and the control gate electrode 104a. At this time, the potential in the channel region is equal to or extremely close to the potential of the source region, that is, the n-type diffusion region 111, so that the electric field between the source and the drain is concentrated in the drain region, that is, the n-type diffusion region. It becomes stronger in the channel region near the region 110, and hot carriers (electron-hole pairs) are generated and impact electrons are injected into the floating gate electrode 108 due to impact ionization in this region. As a result, information is written.

On the other hand, when information is read, one n-type diffusion region 110 is the source region and the other n
The type diffusion region 111 is used as a drain region. That is,
Using the electrode 116 as a source electrode and the electrode 117 as a drain electrode, applying an appropriate potential difference (eg, 5V) between the source and drain, and then applying an appropriate voltage (eg, + 5V) to the control gate electrode 104a.
The information is read by applying a voltage and examining the change in the characteristics of the cell in which the information is written and another cell, for example, the threshold voltage V _TH . Also in this case, the electric field between the source and the drain is concentrated in the drain region, that is, the n-type diffusion region 111.
Since it becomes strong in the vicinity, generation of hot carriers may occur in this portion. However, in such a case, since the floating gate electrode does not exist in the vicinity of the portion where hot carriers are generated, the generated carriers are generated by the floating gate electrode 10.
As a result, it is possible to prevent erroneous writing of information as a result.

Since the memory cells of the EPROM have no risk of erroneous writing when reading information as described above, the channel length can be sufficiently shortened. As a result, the writing efficiency at the time of writing information can be improved, so that the value of the writing voltage such as the drain voltage to be applied at the time of writing information, the voltage of the control gate electrode, etc. can be reduced more than ever before. For example, both the voltage applied when writing information and the voltage used when reading information can be set to about 5V.

In addition, as shown in FIGS. 8 and 9, EP on the same chip
A ROM memory cell and a normal MOS transistor without the floating gate electrode 108 can be manufactured at the same time. Moreover, EPROM
In the memory cell (shown in FIG. 8A), the n-type diffusion layer 111 on the side where the floating gate electrode 108 does not exist is formed as the low concentration diffusion layer 11b near the channel region. On the other hand, in the MOS transistor (shown in FIG. 8B), the low concentration diffusion layers 112b and 113b are formed in the vicinity of the channel regions of the n-type diffusion layers 112 and 113 serving as the source and drain regions. With such a configuration, it is possible to improve the fluctuation and the reliability of the threshold voltage due to the reduction of the channel length.

That is, as the channel length decreases, the threshold voltage of the channel region becomes shallow. The so-called short channel effect occurs.

Also, as the channel length decreases, the electric field generated in the channel region becomes stronger due to the voltage applied between the source and drain, and as a result, the probability of impact ionization due to the channel current increases. Some of the electrons or holes generated by impact ionization jump into the gate insulating film across the energy barrier between the semiconductor substrate and the gate insulating film and flow out to the gate electrode to generate a gate current. Stays trapped in the gate insulating film, changes the threshold voltage of the transistor, changes the channel conductance, and changes the operating characteristics of the transistor,
This is a major cause of loss of device reliability.

As described above, the semiconductor device of the present invention has a low-concentration diffusion layer 111 in the source and drain regions in contact with the channel region.
Since b, 112b and 113b are present, part of the voltage applied between the source and the drain is part of the low concentration diffusion layers 111b, 112b and
This can be taken care of by 113b, and the electric field can be weakened particularly in the channel region near the drain region.

Therefore, according to the present invention, a semiconductor device including an EPROM memory cell having excellent write efficiency and free from erroneous write and a highly reliable MOS transistor forming a peripheral circuit can be manufactured by a simple process.

In the above embodiment, the low-concentration diffusion layer is formed near the channel region of the n-type diffusion layer on the side where the floating gate electrode does not exist in the EPROM memory cell and the source side of the transistor. Normally, the presence of these low-concentration diffusion layers is not a major obstacle to device operation, but since it acts as a resistance connected in series between the source and drain, it is effectively applied between the source and drain. Voltage is lowered, for example, writing efficiency is lowered. In such a case, the formation of the low-concentration diffusion layer can be prevented by removing the remaining polycrystalline silicon 106 'in the portion where the low-concentration diffusion layer is not desired to be formed before the step of FIG. . Even if such a means is adopted,
A high-concentration diffusion layer formed of arsenic may be formed due to a difference in thermal diffusion coefficient between ion-implanted arsenic and phosphorus. In order to prevent this phenomenon, sufficient heat treatment is performed between the high-concentration impurity ion implantation step of FIG. 4 and the low-concentration impurity ion implantation step of FIG. 6 to activate the arsenic ions and It suffices to form a concentration diffusion layer so that the diffusion of phosphorus ions due to the heat treatment shown in FIG. 6 and thereafter is contained in the high concentration diffusion layer.

In the above embodiment, the case where the memory cell has n channels has been described, but the present invention is not limited to this, and the same effect can be obtained even if the memory cell has p channels.

〔The invention's effect〕

As described in detail above, according to the present invention, an EPROM cell that has a high switching speed, is less likely to cause erroneous writing of information, and can reduce the value of the write voltage to be applied at the time of writing information, and a channel length It is possible to provide a method capable of manufacturing a semiconductor device in which a MOS transistor improved in threshold voltage fluctuation and reliability due to a decrease in power consumption coexist on the same chip by a simple process.

[Brief description of drawings]

1 to 8 are sectional views showing a manufacturing process of a semiconductor device in an embodiment of the present invention, FIG. 9 is a plan view of FIG. 8, and FIG. 10 is a sectional view showing a memory cell of a conventional EPROM. . 101 ... P-type silicon substrate, 103 ... Gate oxide film, 104a ... Control gate electrode, 104b ... Gate electrode, 105 ... Oxide film, 108 ...
Floating gate electrode, 110-113 ... n type diffusion layer, 116-119 ... Al
electrode.

Claims (1)

[Claims] 1. A part of the surface of a semiconductor substrate of the first conductivity type,
Forming a control gate electrode through a thin insulating film; forming an insulating film around the control gate electrode; covering the entire surface with a conductive material film; and anisotropically forming the conductive material film. Etching by an etching method to leave a conductive material film in contact with the insulating films corresponding to both side surfaces of the control gate electrode, and a relatively high concentration using the control gate electrode and the remaining conductive material film as a mask And a step of doping the surface of the semiconductor substrate with an impurity imparting the second conductivity type, the conductive material film remaining on both side surfaces of the control gate electrode and the remaining conductive material film by etching away the other conductive material film. Forming a floating gate electrode made of a conductive material film, and doping the surface of the semiconductor substrate with an impurity giving a relatively low concentration of the second conductivity type. A method for manufacturing a semiconductor device, comprising: