JPS62125676A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent information from erroneously writing and to improve reading speed of information by interposing an insulating film between a floating gate and a control gate, and providing a gate electrode through a thin insulating film at least on a part on the floating gate. CONSTITUTION:First and second regions to become source 113 or drain regions 112 provided on a surface region of a semiconductor substrate 101, a floating gate 107 and a control gate 104 provided through an insulating film 114 on a channel region between the first and second regions are provided. The gate 107 is disposed by displacing it on a channel region at the gate 104 side disposed near the first region, an insulating film is interposed between the gates 107 and 104, and a gate electrode 109 is provided through a thin insulating film at least on part of the gate 107. Thus, even if a channel length is shortened as highly integrated, it can prevent information from erroneously writing and improve reading speed of information.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to an electrically rewritable read-only semiconductor memory ( E E P R
OM: E Electrically Erasa
bleProorammable Read 0nly
The present invention relates to a semiconductor device including a memory cell (Memory) and a method for manufacturing the same.

[Technical background of the invention and its problems]

For example, EEPROM memory cells have conventionally
The structure shown in the figure is known. That is, 1 in the figure is a p-type crystalline silicon substrate, and a field oxide film 2 is selectively provided on the surface of this substrate 1. In the island-shaped substrate 1 region separated by the field oxide film 2, n+ type source and drain regions 3.4 electrically isolated from each other are provided, and a channel between these regions 3.4 is provided. There is gate oxidation on the substrate 1 region including the
A floating gate 6 is provided via 5. A control gate 8 is provided on the floating goo 1-6 with an insulating film 7 interposed therebetween. The entire surface including the control gate 8 is covered with an inter-station insulating film 9, and the source and drain regions 3 are formed through contact holes on the insulating film 9.
．． A source electrode 10 and a drain electrode 11 connected to the electrode 4 are respectively provided (section A in the figure). On the other hand, an n+ type diffusion region 4-, which is an extension of the drain region 4, is provided on the surface of the substrate 1 region adjacent to and connected to the island-shaped substrate 1 region, as shown in FIG. ing.

An extended portion 6' of the floating gate 6 is provided on the diffusion region 4- with an insulating thin film 12 interposed therebetween.

The n1 type diffusion region 4-1 insulating film 12 and the extending portion 6'' of the floating gate 6 constitute a MOS capacitor shown at 8 in the figure.

In the memory cell configured as described above, the drain electrode 11
By applying a high voltage of 1ffE, for example, 20 V or more between the control group 1-8 and the control group 1-8, a voltage of 1 to 1 is applied between the extending portion 6- of the floating gate 6 and the n+ type diffusion region 4- through the insulating thin film 12.
．． A channel current flows, and charge is injected into and discharged from the floating goo 1-6. In EEPROM,
Normally, the state in which charges are accumulated in the floating gate 6 is defined as "0".
”, the state where there is no charge is “1”, and the 13th
In part A of the figure, the threshold voltage (VTH
) correspond to high and low states, respectively. In other words, in the EEPROM having such a configuration, information set in the memory cell is injected into the floating gate 6 through the insulating thin film 12, and the resulting threshold voltage of the transistor in section A is detected. is being read out.

By the way, in the process of manufacturing the memory cell having the above structure, the transistor region of part A is formed using a normal silicon gate M.
The manufacturing process is basically the same as the O8FET manufacturing process. That is, a gate oxide film 5 is formed by thermal oxidation on the surface of an island-shaped substrate 1 region separated by a field oxide film 2, and a floating gate 6 made of polycrystalline silicon and a field oxide film 2 are formed.
Using a mask, the surface of the substrate 1 is doped with an impurity imparting n-type conductivity, such as arsenic, by ion implantation or the like to form n+ type source and drain regions 1ii1i3.4.

The floating gate 6 is formed at the same time as the pattern of the control gate 8 made of similar polycrystalline silicon so as to be aligned with the control gate 8.

However, in the EEPROM memory cell having the above-described structure, the presence of the MOS capacitor region in part B significantly complicates the manufacturing process.

That is, the n+ type diffusion region 4' in the B part is an extension of the drain region 4 in the A part, but this region also needs to be formed under the extension part 6' of the floating gate 6 in the A part. Therefore, it cannot be formed in the same process as the drain region 4, which is formed using the floating gate 6 as a mask, as in the above process, and it is necessary to form it in advance before forming the floating gate 6 (6M). The insulation Wi 1112 formed between the n+ type diffusion region 4- and the floating gate extension 6- must have an appropriate thickness to allow a tunnel current to flow. The oxide film grown at the same time before the formation of the gate oxide film 5 cannot be used as it is, and after this step, it is necessary to remove the oxide film from that part and perform new thermal oxidation to form the insulating thin film 12. be.

In addition, when reading information from the memory cell having the above configuration, an appropriate read voltage is applied to the control gate 8 and the drain 6 to the in-electrode 11, and depending on the presence or absence of charge present in the floating gate 6, The written information is determined based on the magnitude of the current flowing between the source and drain regions 3.4. At this time, the state in which there is no charge in the floating gate 6 corresponds to the state in which the threshold voltage of the 1H transistor is low, and in this case, a current flows between the source and drain regions 3 and 4 due to the application of the read voltage. . However, with the miniaturization of devices, the channel length of EEPROM memory cells has become shorter, and the relatively low voltage used for reading (< +5 V)
Even when the drain voltage and control gate 8 are applied,
Electrons flowing from the source region 3 toward the drain region 4 are sufficiently accelerated to have energy capable of causing in-vacuum hair ionization in the channel region near the train region 4. Therefore, in EFPROMs that have become highly integrated and have shortened channel lengths, when reading information, electrons are also generated in the floating cells 1-6 of the memory cells that should originally hold the information "1". 1 to wrap, and the result is that the state is the same as when the rOJ information was written. Such a phenomenon is usually called erroneous writing of information, and when the memory cell having the configuration shown in FIG. 13 is highly integrated, the occurrence of erroneous writing cannot be prevented unless the power supply voltage is lowered. However, when the power supply voltage is lowered, the speed at which information is read from the memory hill decreases.

[Purpose of the invention]

The present invention relates to semiconductor devices such as ``Er'' ROM, which prevents erroneous writing of information and improves information read speed even when the tunnel length becomes shorter due to higher integration, and semiconductor devices such as EEPROM. It is an object of the present invention to provide a method by which a device can be manufactured through extremely simple steps.

[Summary of the invention]

The invention in Box 1 of the present invention provides a first . a second region, and these first regions. A floating gate and a control gate are provided on a channel region between the second regions via an insulating film, and the floating gate is unevenly distributed over the channel region on a side surface of the control gate located near the first region. A semiconductor device characterized in that an insulating film is interposed between the floating gate and the control gate, and a gate electrode is provided on at least a part of the floating gate 1 through an insulating thin film. be.

The invention in Box 2 includes a step of forming a control gate disposed on a part of the surface of a semiconductor substrate with an insulating film interposed therebetween, a step of forming an insulating film around the control gate, and a step of forming a conductive material film on the entire surface. This conductive material film is sequentially removed using an anisotropic etching method and a normal etching method, leaving a portion of the conductive material along the control gate to form a floating gate. forming an insulating thin film around part or all of the floating gate; forming a gate electrode in contact with at least a part of the floating gate through the insulating thin film; At any time from before the formation of the insulating thin film around the gate to after the formation of the gate electrode, impurities are doped into the surface of the semiconductor substrate using the control gate and the floating gate as a mask to form a source or drain region. A method of manufacturing a semiconductor device is characterized in that it comprises a step of forming first and second regions.

According to the present invention described above, even if the channel length becomes shorter due to higher integration as described above, the EEPR can prevent erroneous writing of information without causing a decrease in the information read speed.
Semiconductor devices such as OM and EEFROM can be manufactured through simple steps.

[Embodiments of the invention]

Hereinafter, an example in which the present invention is applied to a memory cell of an N17-channel EEPROM will be described in detail with reference to FIGS. 1 to 9. In addition, (a) of FIGS. 1 to 9 is a pattern plan view, (b) is a cross-sectional view along line A-A in (a), and (C) is a line BB in (a). FIG.

First, a p-type silicon substrate 101 is selectively oxidized to form a p-type silicon substrate 101.
After forming field 10 = -field oxide film 102 for separating the surface of 01 into islands, 900 to 1000
It is desired to form an oxide film 103 with a thickness of about 250 mm on the surface of the island-shaped substrate 101 by thermal oxidation in an oxidizing atmosphere at .degree. C. (as shown in FIG. 1). Subsequently, a polycrystalline silicon film doped with p-type or n-type impurities is deposited on the entire surface to a thickness of 3000 nm using the L P CV D method, and then this polycrystalline silicon film is patterned to form a control gate made of polycrystalline silicon. 104 (as shown in FIG. 2).

Next, thermal oxidation is performed in an oxidizing atmosphere at 900 to 1000°C to grow an oxide film 105 with a thickness of 500 nm around the control gate 104 made of polycrystalline silicon, and then a p-type or A polycrystalline silicon film 106 doped with n-type impurities was deposited (as shown in Figure 3).
. Subsequently, the polycrystalline silicon film 106 was etched away using an anisotropic etching method, such as reactive ion etching (RIE method). In this process, since the film around the control gate 104 is effectively thick in the height direction, a polycrystalline silicon film is formed around the control gate 104.
06' remained (as shown in Figure 4). Subsequently, using a photoresist pattern (not shown) formed by photolithography as a mask, the remaining polycrystalline silicon film 106' is selectively etched away, and an oxide film 105 is etched on one longitudinal side of the control gate 104. It is desired to form a floating gate 107 arranged as shown in FIG.

Then, it is thermally oxidized in an oxidizing atmosphere at 900 to 1000°C to form a layer around the floating goo 1-107 to a thickness of 10.

A thin oxide film 108 was grown to a certain extent (as shown in FIG. 6).
Subsequently, a polycrystalline silicon film doped with p-type or p-type impurities is deposited on the entire surface again to a thickness of 3,500 yen using the L P CV D method, and is patterned to at least cover the oxide thin film 108 of the floating gate 107. A built-in gate 109 was formed as a gate electrode (as shown in FIG. 7).

Next, thermal oxidation was performed in an oxidizing atmosphere at 900 to 1000° C. to grow an oxide film 110 with a thickness of 500 μm around the writing group 1-109. At this time, write gate 10
Oxide thin film 10 on the surface of the floating gate 107 except for the area under 9
8 is oxidized to form oxide 1111 with a thickness of 500. After that, using the field oxide film 102, the control layer 104 and the floating gate 107 as masks, an n-type impurity, for example arsenic, is implanted at an energy of 50keV and an implantation dose of 11.
Ion implantation was performed under the conditions of 1× 1 Q I 8 rt, yb4 (as shown in FIG. 8). Next, heat treatment is performed to activate the ion-implanted arsenic and form the n+ type resistive diffusion layer 11211.
3 was formed. Subsequently, 5t was applied to the entire surface using the CVD method.
After depositing an O2 film 114 and opening a contact hole 115, an Afi film is deposited and patterned to
+ type scattering layer 12, 113 and contact hole 11 respectively
forming Δg electrodes 116, 117 connected through 5;
When manufacturing an EEPROM memory cell (as shown in FIG. 9).

As shown in FIG. 9, in the memory cell of the EEPROM of the present invention, n++ diffusion regions 112 and 113, which become source or drain regions, are mutually arranged on the surface of an island region of a p-type silicon substrate 101 separated by a field oxide film 102. An oxide film 10 is formed on the substrate 101 region (channel region) between these n+ type diffusion regions 12 and 113, which are provided separately.
A control gate 104 and a floating gate 107 are provided through the control gate 10/I and the floating gate 107, and an oxide film 105 is interposed between the control gate 10/I and the floating gate 107 to insulate them from each other. Further, a write gate 109 is arranged on the floating gate 107 and in contact with it via a thin oxide film 108 formed on the surface thereof.

In a memory cell having such a configuration, the control gate 10
4 and write goo 1-109, e.g. 20
By applying a voltage of about V, a tunnel current flows between the write gate 109 and the floating gate 107 through the oxide 1 film 108, and as a result, charges are injected and discharged into the floating gate 1-107. . At this time, the substrate 10
1, n++ diffusion regions 112 and 113 are control gates 104
It is desirable that the potential is the same as that of

When reading information, one n++ diffusion region 112 is used as a source region, and the other n-type region 113 is used as a drain region. That is, the electrode 116 is a source electrode,
The electrode 117 is used as a train electrode, and an appropriate potential difference (for example, 5 V) is applied between the source and drain, and then the control group 1 is applied.
~104 by applying an appropriate voltage (e.g. +5V)
The information is read by checking the difference in characteristics between the cell to which the information of `` is written and the cell to which the information of rOJ is written, for example, the threshold voltage VT. In this case as well, the electric field between the source and drain is concentrated in the train region, that is, n+
Since the intensity increases near the type diffusion region 113, hot carriers may be generated in this area. however,
In such a case, since there is no floating gate near the portion where hot carriers are generated, the generated carriers are not injected into the floating gate, and as a result, erroneous writing of information can be prevented.

Furthermore, in the memory cell having the above-described configuration, charge can also be injected into the floating gate in the following manner. First, one n+ type diffusion region 112 is used as a drain region, and the other n+ type diffusion region 113 is used as a source region.

That is, the electrode 116 is used as a drain electrode, the electrode 117 is used as a source electrode, and a high voltage is applied to both the drain electrode 116 and the control gate 104. At this time, the potential in the channel region is equal to or very close to the potential of the source, that is, the n+ type diffusion region 113, so
The charge between the source and the drain becomes concentrated and strong in the drain region, that is, the channel region near the n+ type diffusion region 112, and in this region, hot carriers (electron-hole pairs) are generated by impact ionization and transferred to the floating gate 107. injection of electrons occurs.

As described above, in the memory cell having the structure of the present invention,
Since there is no risk of erroneous writing when reading information, the channel length can be made sufficiently short, and the power supply voltage applied when reading information can be kept high, so that the information from the memory cell is The read speed can be increased.

Further, in the memory cell having the above configuration, the oxide thin film 108 is located on the surface of the floating gate 107 and is formed on the drain region, that is, on the substrate 101, which is the path of the tunnel current when charge is injected into and discharged from the floating gate 107. Therefore, the oxide thin film 108 and the gate oxide film 103
can be formed completely independently, eliminating the need for the step of peeling off the gate oxide film, and also eliminating the need for the step of forming an n+ type diffusion region, which was necessary to form the extended portion of the drain region. Therefore, according to the method of the present invention, an EEPROM memory cell having the above-mentioned effects can be manufactured through extremely simple steps compared to the conventional method.

In the above embodiments, the control gate, floating gate, and write gate (gate electrode) are formed of polycrystalline silicon doped with n-type or p-type impurities, but the present invention is not limited thereto. For example, it may be formed from a silicide of a high melting point metal such as molybdenum, tungsten, titanium, or tantalum.

In the above embodiment, after the write gate 109 is formed in the steps shown in FIGS. 6 to 8, the n+ type diffusion region 112.1 is
Although ion implantation is performed to form the write gate 109, this ion implantation process may be performed before the write gate 109 is formed. By adopting such a method, even if the write gate 109 is placed across the device region in which the n+ type diffusion region is formed, the write gate does not inject the n+ type diffusion regions 112 and 113 into the device region. The formation is not impaired. Furthermore, by adopting such a method, a thin oxide film 1 is formed on the floating gate 107 (not shown in FIG. 6).
08 or the writing goo h shown in FIG.
In the step of forming the oxide film 110 around the oxide film 109, the thermal oxidation treatment and the heat treatment for activating the ion-implanted impurities can be used simultaneously.

Further, the semiconductor device of the present invention is not limited to the structure shown in the above embodiment. For example, FIG. 10 described below,
The structure shown in FIG. 11 or FIGS. 12(a) and (b) may be used. In FIG. 12, (a) is a plan view, and (b) is a sectional view taken along line A-A in (a).

That is, in the memory cell of FIG. 70, the diffusion region 113 that becomes a drain when reading information is formed of two regions, a highly doped region 1131 and a lightly doped region 1132, of which the lightly doped region 1132 serves as a channel region. It is configured to be in contact with In a memory cell having such a configuration, when reading information, electrode 116 is used as a source electrode, electrode 117 is used as a drain electrode, and a voltage is applied to control gate 104 after applying an appropriate potential difference between the source and the train. At this time, the diffusion region 11 which becomes the drain region
3, the part in contact with the channel region has a low impurity concentration f! Since it is composed of four regions 1132, this region can receive part of the voltage applied between the source and drain.

Therefore, in the memory cell shown in FIG. 10, the generation of hot carriers near the drain region when reading information can be more effectively suppressed, and erroneous writing can be effectively prevented.

The memory cell shown in FIG. 11 has a p+ type diffusion region 118 which is of the same 1j type as the substrate 101 and also has a high impurity concentration, adjacent to the n+ type diffusion region 112 shown in FIG.
This is a structure suitable for injecting charge into the floating goose 1 to 10 by generating pot carriers in the channel region.
The injection efficiency of the charges injected into the cell 7 is increased. That is, by adopting such a configuration, the n1 type diffusion region 112 is used as a drain region, and the n+ type diffusion region 113 is used as a drain region.
When writing information rOJ using as a source region, the electric field tends to concentrate on the newly formed p+ type diffusion region 118, and impact ionization tends to occur in this region, increasing the writing efficiency. It will be done. On the other hand, n+
The type diffusion region 112 is used as a source region, and the n+ type diffusion region 113
When reading information using the p+ type diffusion region 118 as the drain region, since the p+ type diffusion region 118 is adjacent to the n+ type diffusion region 112 which becomes the source region, its presence does not affect the readout characteristics in the slightest. However, there is no risk of writing errors.

In the memory cell shown in FIG. 12, a part of the oxide film 103 on the n+ type diffusion region 113 is removed to form a direct contact portion 1.
A hole 19 is opened, a part of the write gate 109 is extended to a part 119 of the contact 1, and the contact part 119 is connected to the n+ type diffusion region 113, so that the write gate 109 and the n+ type diffusion region 113 are connected to each other. The structure is such that they have the same potential. In the memory cell shown in FIG. 12, charges are injected into and discharged from the floating gate 107 by a high voltage applied between the control gate 104 and the n+ type diffusion region 113.

Of course, the means for bringing the write gate 109 and the n+ type diffusion region 113 to the same potential is the write gate 109 as described above.
The method is not limited to the method of directly contacting the n+ type diffusion region 113, and external wiring may be used. Note that the write gate 10
9 is an n+ type diffusion region 1 instead of the n+ type diffusion region 113.
12 so that the potential of the write gate 109 is the same as that of the n+ type diffusion region 112.

Further, in each of the above embodiments, the memory cell is an n-channel memory cell, but the present invention is not limited to this, and similar effects can be obtained with a p-channel memory cell.

〔Effect of the invention〕

As detailed above, the present invention provides a semiconductor device such as an EEPROM that can prevent erroneous writing of information and improve the speed of reading information even if the channel length becomes shorter due to higher integration, as well as the EEPROM. It is possible to provide a method for manufacturing semiconductor devices such as the above through extremely simple steps.

[Brief explanation of drawings]

1 to 9 are EEPROMs according to embodiments of the present invention.
10 and 11 are cross-sectional views of an EEPROM memory cell showing other embodiments of the present invention, and FIG. 12 shows still another embodiment of the present invention. FIG. 13 is a sectional view showing a conventional EEPROM memory cell. 101... P-type silicon substrate, 102... Field oxide film, 103... Oxide film, 104... Control gate, 107... Floating gate, 108... Oxide thin film,
109...Write gate (gate electrode), 112.1
13-=n+ type diffusion region, 114-8 i 02'F
A, 116.117-AC! , electrode, 118 ・l)+
Type diffusion region, 119...direct contact part. Applicant's agent Patent attorney Takehiko Suzue "≧ l・
11 L+-----1-J [Figure 10 Figure 11 Figure 13

Claims (3)

[Claims] (1) First and second regions are provided separately on the surface region of the semiconductor substrate and serve as source or drain regions, respectively, and a channel region between these first and second regions is provided with an insulating film interposed therebetween. A floating gate and a control gate are provided, the floating gate is unevenly arranged on the channel region on the side surface of the control gate located near the first region, and the floating gate is located between the floating gate and the control gate. 1. A semiconductor device comprising an insulating film interposed therebetween and a gate electrode provided on at least a portion of the floating gate via the insulating thin film. (2) Claim 1, characterized in that the gate electrode is connected to the first region or the second region directly or by external wiring, and has the same potential as the first region or the second region. The semiconductor device described. (3) A step of forming a control gate disposed on a part of the surface of the semiconductor substrate via an insulating film, a step of forming an insulating film around the control gate, and a step of covering the entire surface with a conductive material film. and a step of sequentially removing the conductive material film using an anisotropic etching method and a normal etching method, leaving the conductive material in a portion along the control gate to form a floating gate. , a step of forming an insulating thin film around part or all of the floating gate, a step of forming a gate electrode in contact with at least a part of the upper part of the floating gate via the insulating thin film, and a step of forming an insulating thin film around the floating gate. The semiconductor substrate surface is doped with impurities using the control gate and the floating gate as a mask at any time from before the formation of the insulating thin film to after the formation of the gate electrode to form the first and second regions, which become source or drain regions. 1. A method of manufacturing a semiconductor device, comprising the step of forming a region.