JP4040138B2 - Method for manufacturing nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device.
[0002]
[Prior art]
Conventionally, this type of non-volatile semiconductor memory device includes the following.
[0003]
9A and 9B are structural views of such a conventional nonvolatile semiconductor memory device, in which FIG. 9A is a plan view, FIG. 9B is a cross-sectional view taken along the line AA 'of FIG. FIG. 9C is a cross-sectional view taken along line BB ′ of FIG.
[0004]
Usually, an active region 2 and an element isolation region 3 are formed on a P-type silicon substrate 1 by using an element isolation method. Then, an ultra-thin silicon oxide film 4 having a thickness of about 100 mm is formed on the active region 2, a first polycrystalline silicon film 5 doped with an N-type impurity is further formed thereon, and a silicon film having a thickness of about 200 mm serving as an insulating film. A laminated film structure of an oxide film 6, a polycrystalline silicon film 7 serving as a second gate, and a refractory metal film 8 is formed. Also, after the laminated film is patterned in a batch, As ⁺ 60 keV, 5 × 10 ¹⁵ N-type source region 9 and N-type drain region 10 are formed by ion implantation to the extent.
[0005]
Normal, N type As shown in FIG. 9B, the source region 9 is located at a position sandwiched between the composite films 7 and 8 serving as two word lines and is electrically shared by all the memory cells. Yes. on the other hand, N type The drain region 10 is connected by a metal wiring 12 or the like through a contact 11 so as to be shared by two memory cells. Further, a silicon oxide film 13 for electrical insulation is deposited between the refractory metal film 8 and the metal wiring 12 by about 10,000 mm. Thereafter, a general protective film (not shown) is formed to complete the nonvolatile semiconductor memory device.
[0006]
In recent years, in order to reduce memory cells, SAS (self-aligned source) is often used as a method for forming a source region. This is shown below. The production procedure is the same as described above until the pattern formation of the laminated film.
[0007]
FIG. 10 is a structural diagram (part 2) of a conventional nonvolatile semiconductor device, FIG. 10 (a) is a plan view thereof, FIG. 10 (b) is a cross-sectional view taken along the line AA ′ of FIG. 10 (c) is a sectional view taken along the line BB 'in FIG. 10 (a), and FIG. 10 (d) is a sectional view taken along the line CC' in FIG. 10 (a).
The shape after forming such a laminated film pattern 11 Shown in The difference from the above-described conventional example is that the pattern of the source region is not formed when the active region 2 is formed. So at this point, figure 11 As shown in FIG. 5A, the active region 2 has a pattern orthogonal to the polycrystalline silicon film 7 and the refractory metal film 8 which are the second gate.
[0008]
Then figure 11 (B), Figure 11 As shown in (c), after patterning the photoresist so as to cover the drain region and part of the word lines 7 and 8, the silicon oxide film is anisotropically etched. The etching conditions at that time are selected so that the silicon oxide film and the silicon film have good selectivity. 11 As shown in (d), the silicon oxide films in the element isolation region 3 and the active region 2 are removed.
[0009]
Then, after removing the photoresist, As ⁺ 60 keV 5 × 10 ¹⁵ By implanting ions at a degree, 10 As shown in FIG. 2, an N-type source region 9 and an N-type drain region 10 are formed.
[0010]
The drain region 10 is connected by a metal 12 wiring or the like through a contact 11 so as to be shared by two memory cells. Further, a silicon oxide film 13 for electrical insulation is deposited between the refractory metal film 8 and the metal wiring 12 by about 10,000 mm. Thereafter, a general protective film (not shown) is formed to complete the nonvolatile semiconductor memory device.
[0011]
By using this SAS, the source region 9 can be produced in a self-aligned manner with respect to the word lines 7 and 8, so that the pattern alignment is shifted between the active region 2 of the source region 9 and the word lines 7 and 8. The memory cell area can be reduced because there is no need to allow for the expected margin.
[0012]
Next, bias conditions for programming a general memory array and bias conditions for reading are shown in FIGS. 12 and 13, respectively.
[0013]
FIG. 12 is a diagram showing program bias conditions of a conventional nonvolatile semiconductor device, and FIG. 13 is a diagram showing read bias conditions of the nonvolatile semiconductor device.
[0014]
Since the bias condition is common to the two conventional examples described above, one method will be described.
[0015]
Since the program needs to selectively program the memory cell, by applying a positive voltage to the drain region instead of the source region shared by the memory cell and making the voltage of the selected word line negative, The electrons in the first gate are extracted to the drain side. At this time, the concentration of the N-type diffusion layer is 5 × 10. ¹⁵ cm ^-2 The above is desirable.
[0016]
On the other hand, when a positive voltage is applied to the drain region and the voltage of the selected word line is set to about 3 V, the current between the source and drain of the memory cell is detected, and a current that can be detected can be detected. Is set to the program state, and conversely, when the current cannot be detected, it is set to the erase (ERASE) state.
[0017]
[Problems to be solved by the invention]
However, in the conventional non-volatile semiconductor memory device described above, as shown in FIG. 13C, a non-selected memory element sharing the same bit line at the time of reading is selected by applying a bit voltage. The problem is that the memory cell data (electrons accumulated in the first polycrystalline silicon) cannot be guaranteed for 10 years of warranty because the tunneling through the ultra-thin silicon oxide film will gradually escape. was there.
[0018]
The present invention provides a method for manufacturing a nonvolatile semiconductor memory device that eliminates the above-described problems, reduces the electric field applied to the ultrathin silicon oxide film, and reduces the amount of electrons emitted from the first gate. The purpose is to do.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides
[1] A source region which is arranged in a matrix on a P-type semiconductor substrate, and which is composed of a plurality of memory elements each having a floating gate and a control gate, is constituted by an N-type diffusion region, and extends in one direction. A word line composed of a control gate provided parallel to the source region and sandwiching the source region, and an N-type diffusion region provided at a position facing the source region across the word line A plurality of bit regions electrically connected to a plurality of drain regions formed by extending in a direction intersecting with the word lines. Or Second, a positive voltage is applied to a selected word line and a source region as a memory element read condition, a selected bit line potential is grounded, and a non-selected word line and a non-selected bit line are grounded and floated, respectively. A method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a N-type diffusion layer in a source region and a drain region in a self-aligned manner after forming the word line; and using the photoresist as a mask, the drain Higher concentration than the N-type diffusion layer in the region N type And a step of forming a diffusion layer.
[0020]
[ 2 A method of manufacturing a non-volatile semiconductor memory device according to the above [1], wherein a step of generating a first conductive layer for forming the floating gate and a bit line using the first conductive layer as a mask for a photoresist Patterning in parallel with the substrate, forming an N-type diffusion layer in a region where the first conductive layer of the source line is removed, generating a second conductive layer to be a control gate, and a word line And a forming step.
[0021]
[ 3 A source region arranged in a matrix on a P-type semiconductor substrate, each of which is composed of a plurality of memory elements each having a floating gate and a control gate, is composed of an N-type diffusion region, and extends in one direction; A word line composed of a control gate provided parallel to the source region and sandwiching the source region, and an N-type diffusion region provided at a position facing the source region across the word line. And a plurality of bit lines electrically connected to the plurality of drain regions formed extending in the direction intersecting the word line. Or Second, a positive voltage is applied to a selected word line and a source region as a memory element read condition, a selected bit line potential is grounded, and a non-selected word line and a non-selected bit line are grounded and floated, respectively. A method for manufacturing a nonvolatile semiconductor memory device, comprising: forming a N-type diffusion layer in a drain region using a photoresist as a mask after forming the word line; and a source region and a drain region in a self-aligned manner with the word line And simultaneously forming an N-type diffusion layer having a lower concentration than the N-type diffusion layer, forming a sidewall film made of an insulating film on a side surface of the word line, and self-adhering to the sidewall film and the word line. And a step of forming an N-type diffusion layer having a higher concentration than that of the N-type diffusion layer formed in the source region in a consistent manner.
[0022]
[ 4 A source region arranged in a matrix on a P-type semiconductor substrate, each of which is composed of a plurality of memory elements each having a floating gate and a control gate, is composed of an N-type diffusion region, and extends in one direction; A word line composed of a control gate provided parallel to the source region and sandwiching the source region, and an N-type diffusion region provided at a position facing the source region across the word line. And a plurality of bit lines electrically connected to the plurality of drain regions formed extending in the direction intersecting the word line. Or Second, a positive voltage is applied to a selected word line and a source region as a memory element read condition, a selected bit line potential is grounded, and a non-selected word line and a non-selected bit line are grounded and floated, respectively. A method for manufacturing a nonvolatile semiconductor memory device, the method comprising: after forming the word line, removing the insulating film in a self-aligned manner with respect to the word line in contact with the source region using a photoresist as a mask, and forming the source line; Forming a N-type diffusion layer in the source region using the photoresist as a mask, and forming an N-type diffusion layer having a higher concentration than the N-type diffusion layer concentration formed in the source region in the drain region using the photoresist as a mask. And a process.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0024]
First, a first embodiment of the present invention will be described.
[0025]
1 to 3 are cross-sectional views showing a manufacturing process of the nonvolatile semiconductor device according to the first embodiment of the present invention. The right side is a cross-sectional view corresponding to the line BB 'in FIG. 9, and the left side is a cross-sectional view corresponding to the line AA' in FIG.
[0026]
(1) First, as shown in FIG. 1A, a P-type silicon substrate 31 having a specific resistance of about 20 Ω · cm is prepared.
[0027]
(2) Next, as shown in FIG. 1B, an element isolation region and an active region are formed using a normal LOCOS method. At this time, the element isolation oxide film 32 is set to a film thickness that allows sufficient element isolation even for a high voltage used in a nonvolatile semiconductor. For example, the wet oxidation at 1000 ° C. is set to about 6000%. Thereafter, an ultrathin silicon oxide film 33 that will be a tunnel oxide film of the memory cell is formed by 100 ° C. wet oxidation at 850 ° C.
[0028]
(3) Thereafter, as shown in FIG. 1C, the first gate 34 which will eventually become the data storage layer of the memory cell is deposited by 1000 nm of the polycrystalline silicon film by the LPCVD method. After that, an N-type impurity is introduced into the first gate 34. ⁺ 1 × 10 about 20 keV ¹⁵ cm ^-2 Ion implantation. Then, in order to arrange the first gate 34 at a predetermined position of the memory cell, a pattern is formed only in the direction orthogonal to the word line at this time. A photoresist 43 is exposed on the first gate 34 so as to have a desired pattern, and a part of the polycrystalline silicon film (first gate) 34 is selectively dry-etched.
[0029]
(4) Thereafter, as shown in FIG. 2A, the photoresist 43 is removed, and a silicon oxide film 35 of about 200 mm is formed on the first gate 34 on which the pattern is formed by thermal oxidation at 950 ° C. Form. In this case, instead of the silicon oxide film 35, a composite film having a three-layer structure of silicon oxide film-silicon nitride film-silicon oxide film may be used.
[0030]
As a condition at this time, a silicon oxide film of about 100 第 is formed on the first gate 34 by a thermal oxidation method at 950 ° C., and then 100 シ リ コ ン of a silicon nitride film is deposited by an LPCVD method. Thereafter, a silicon oxide film of about 50 mm is formed on the silicon nitride film by wet oxidation at 1000 ° C. At this time, the film thickness of the final three-layer composite film becomes 200 mm in terms of silicon oxide film. Thereafter, a polycrystalline silicon film 36 is formed on the silicon oxide film 35 by LPCVD with a thickness of about 2000 mm.
[0031]
Thereafter, POC1 is added to the polycrystalline silicon film 36. _Three 5 × 10 by the diffusion method of ²⁰ cm ^Three To diffuse phosphorus. This is necessary in order to finally use the film including the polycrystalline silicon film 36 as a word line for wiring. Thereafter, a refractory metal film 37 such as tungsten is formed on the polycrystalline silicon film 36 by sputtering.
[0032]
Ultimately, the composite film of the refractory metal film 37 and the polycrystalline silicon film 36 becomes a word line that functions as a control gate.
[0033]
(5) Thereafter, as shown in FIG. 2B, exposure is performed so as to leave a photoresist 38 at a desired position for forming a word line, and a first gate 34, a silicon oxide film 35, and a polycrystalline silicon film 36 are left. The laminated film composed of the refractory metal film 37 is selectively anisotropically etched. At this time, since the first gate 34 is patterned in the word line direction, the floating gate is formed for the first time at this point.
[0034]
(6) Thereafter, as shown in FIG. 2 (c), the photoresist 38 is removed, and a heat of 900 ° C. is applied to the entire surface of the wafer. Because the refractory metal is silicided and oxidized at the same time by the treatment, A thermal silicon oxide film 39 of about 100 mm is formed.
[0035]
(7) Thereafter, as shown in FIG. 3A, phosphorus is 120 keV, 5 × 10 6 by ion implantation using the word line as a mask. ¹³ cm ^-2 About to be injected into the silicon substrate 31. In FIG. 3A, a thin N-type diffusion layer of the source region 40a and the drain region 40b is formed at the same time.
[0036]
(8) After that, as shown in FIG. 3B, the photoresist 42 is patterned so as to cover the source region 40a and a part of the word line gates 36, 37, and thereafter, arsenic is deposited at 40 keV, by ion implantation. 5 × 10 ¹⁵ cm ^-2 Implantation is performed to form a diffusion layer 41 having a higher concentration than the N-type diffusion layer (drain region 40b).
[0037]
Thereafter, although not shown, the photoresist 42 is removed and a silicon oxide film serving as an intermediate insulating film is deposited by the LPCVD method. Then, a contact hole is formed at a desired position, and an Al film containing silicon is sputtered. And patterning or the like. Thereafter, a silicon nitride film or the like serving as a protective film is generated to complete the nonvolatile memory element.
[0038]
Next, bias conditions for the nonvolatile semiconductor device of the present invention will be described.
[0039]
FIG. 4 shows a non-volatile semiconductor device according to the first embodiment of the present invention. Lead It is a figure explaining a bias condition.
[0040]
Unlike the conventional method, a bias of about 1 V is applied to the source line. When a certain memory cell is selected, the voltage of the word line of the memory cell is set to about 3V (in this case, Vwl3), and the selection bit is set to 0V (in this case, Vbit2). The unselected word line and the unselected bit line are set to 0 V and open, respectively. FIG. 4 (a) shows this as a matrix.
[0041]
The bias applied to the selected cell at this time is as shown in FIG.
[0042]
On the other hand, a non-selected cell is biased as shown in FIG.
[0043]
As described above, according to the first embodiment, the diffusion layer region to which a positive potential is applied at the time of programming and the diffusion layer region to which a voltage is applied at the time of reading are separated, and the diffusion layer concentration to which a voltage is applied at the time of reading is conventionally changed. Since the concentration is lower, the voltage applied to the diffusion layer at the time of reading does not change, but the electric field applied to the ultrathin silicon oxide film is effectively reduced and the amount of electrons emitted from the first gate is reduced. be able to.
[0044]
That is, by reducing the concentration of the diffusion layer, the depletion layer spreads more than the conventional depletion layer in the N-type diffusion layer immediately below the first gate at the time of reading.
[0045]
Next, a second embodiment of the present invention will be described.
[0046]
FIG. 5 is a cross-sectional view of the main part manufacturing process of the nonvolatile semiconductor device showing the second embodiment of the present invention. Note that the memory cell Lead The bias condition is the same as in the first embodiment.
[0047]
Since the manufacturing method is the same in FIGS. 1A to 2C of the first embodiment, the subsequent steps will be described in detail.
[0048]
(1) As shown in FIG. 5A, a photoresist 50 is patterned and left so as to cover a region which will eventually become a drain and a part of the word line, and phosphorus is 120 keV, 5 × 10 6 by ion implantation. ¹³ cm ^-2 Implanted to the silicon substrate 31 to the extent. In this step, the source region 51 is formed.
[0049]
(2) After that, the photoresist 50 is removed, and as shown in FIG. 5B, the photoresist 52 patterned so as to cover a part of the source region 51 and the word line is left, and the drain is formed by ion implantation. A region 53 is generated. The ion implantation conditions are arsenic 40 keV, 5 × 10 ¹⁵ cm ^-2 Degree. Subsequent steps are the same as in the first embodiment from the formation of the intermediate insulating film.
[0050]
As described above, according to the second embodiment, since the source region and the drain region are formed separately, the drain region has a single drain structure instead of the DDD structure, so that the effective gate length of the memory cell is set to the first embodiment. Can be smaller than the example. In addition, the same effect as that of the first embodiment can be obtained with respect to the resistance to charge loss during reading.
[0051]
Next, a third embodiment of the present invention will be described.
[0052]
FIG. 6 is a cross-sectional view showing the main part manufacturing process of the nonvolatile semiconductor device according to the third embodiment of the present invention. A top view of the memory cell portion is shown on the right side of FIG.
[0053]
However, since FIGS. 1A to 1C of the first embodiment are the same as those of the third embodiment, the subsequent steps will be described.
[0054]
(1) First, as shown in FIG. 6A, the patterning of the first gate 34 is completed.
[0055]
(2) After that, as shown in FIG. 6B, the photoresist 60 used for patterning the first gate 34 is left without being removed, and arsenic is 40 keV, 5 × 10 6 by ion implantation. ¹⁵ cm ^-2 Inject about. At this time, arsenic is implanted only in a part of the source line (see the hatched portion in FIG. 6B).
[0056]
After that, the photoresist 60 is removed, and the manufacturing process after FIG. 2A of the first embodiment is followed.
[0057]
As described above, according to the third embodiment, since the high-concentration N-type diffusion layer is formed in a part of the common source region, the diffusion layer resistance of the source region can be reduced, and read access can be performed. Increases speed. In addition, since the concentration of the N-type diffusion layer immediately below the first gate 34 of the memory cell can be maintained at a low concentration, the same effect as that of the first embodiment can be obtained with respect to the charge loss resistance of the non-selected cells at the time of reading.
[0058]
Next, a fourth embodiment of the present invention will be described.
[0059]
In the fourth embodiment, the second and third embodiments are performed simultaneously. That is, a high-concentration N-type diffusion layer is formed in a part of the source line [see FIG. 6B], and N-type ion implantation is performed after the first gate formation, which is a feature of the second embodiment. Then, the source region and the drain region are separately formed (see the steps of FIGS. 5A and 5B).
[0060]
As described above, according to the fourth embodiment, the resistance of the source line diffusion layer can be reduced by forming the high-concentration N-type diffusion layer in a part of the source line, so that the access time at the time of reading can be improved. In addition, since the source region and the drain region can be generated independently, the drain diffusion layer can be made a single drain, and the cell size with a short effective gate length can be reduced.
[0061]
Next, a fifth embodiment of the present invention will be described.
[0062]
FIG. 7 is a cross-sectional view of the main part manufacturing process of the nonvolatile semiconductor device showing the fifth embodiment of the present invention. Since FIG. 1A to FIG. 2C of the first embodiment are the same step, the subsequent steps will be described in detail.
[0063]
(1) As shown in FIG. 7A, after the word line is formed, a thermal silicon oxide film 39 is formed about 100 mm, and then a photoresist 70 patterned so as to cover a part of the source region and the word line is left. Arsenic is 40 keV, 5 × 10 5 by ion implantation. ¹⁵ cm ^-2 Implanted to the silicon substrate 31 to the extent. At this time, the drain region 71 is formed.
[0064]
(2) Next, the photoresist 70 is removed, and as shown in FIG. 7B, a source region 72a and a drain region 72b are formed by ion implantation in a self-aligning manner using a word line as a mask. The ion implantation conditions at this time are as follows: phosphorus is 120 keV, 5 × 10 ¹⁴ cm ^-2 Degree.
[0065]
(3) Thereafter, as shown in FIG. 7 (c), a 4000 PSG film 73 is deposited on the entire surface by the LPCVD method.
[0066]
(4) Next, as shown in FIG. 7D, the PSG film 73 is anisotropically etched to form a sidewall 74 of the PSG film on the side wall of the memory cell. Then, using the sidewall 74 and the word line as a mask, arsenic is 40 keV, 5 × 10 ¹⁵ cm ^-2 By implanting to a certain extent, a high concentration N type diffusion layer region 75 is formed in a part of the source region.
[0067]
After that, an intermediate insulating film is formed, but the first and subsequent steps follow that step.
[0068]
As described above, according to the fifth embodiment, a high concentration N-type diffusion layer can be formed in the common source region, and the N-type diffusion layer concentration immediately below the first gate can be lowered. The data omission can be suppressed in the same manner as in the first embodiment, and the diffusion layer resistance in the source region is further reduced as compared with the first and second embodiments. Can be improved.
[0069]
Next, a sixth embodiment of the present invention will be described.
[0070]
FIG. 8 is a cross-sectional view of the main part manufacturing process of the nonvolatile semiconductor device showing the sixth embodiment of the present invention. Since this embodiment is an application of a general SAS structure memory cell, it has an active region structure as shown in FIG. FIG. 8 shows an AA ′ section and a CC ′ section in FIG. 10.
[0071]
Regarding the manufacturing process, since FIGS. 1A to 2B of the first embodiment are the same, the subsequent steps will be described in detail.
[0072]
(1) FIG. 8A shows a pattern after word line patterning.
[0073]
(2) Thereafter, as shown in FIG. 8B, the photoresist 80 patterned so as to cover the region which will eventually become the drain and a part of the word line is left. Thereafter, the silicon oxide films (element isolation oxide films) 32 and 33 in the region to be the source line are anisotropically etched so as to be formed in a self-aligned manner with respect to the word line. As the etching condition at this time, a condition having good selectivity with respect to silicon is selected. Thereafter, the source region 81 is formed by ion implantation without removing the photoresist 80. The ion implantation conditions are phosphorus 120 keV, 4 × 10. ¹⁵ cm ^-2 Degree.
[0074]
(3) After that, as shown in FIG. 8C, the photoresist 83 is left so as to cover the source region 81 and a part of the word line, and the drain region 84 is formed by ion implantation.
[0075]
After that, the intermediate insulating film is formed, and this and subsequent steps are the same as those in the first embodiment, and therefore follow.
[0076]
Thus, according to the sixth embodiment, even in a general SAS formation process, the concentration of the source diffusion layer immediately below the gate of the memory cell can be kept low without newly increasing the mask step. The charge retention resistance at the time can be improved.
[0077]
In addition, this invention is not limited to the said Example, A various deformation | transformation is possible based on the meaning of this invention, and these are not excluded from the scope of the present invention.
[0078]
【The invention's effect】
As described above in detail, according to the present invention, the following effects can be obtained.
[0079]
(A) A diffusion layer region to which a positive potential is applied during programming of a semiconductor memory device and a diffusion layer region to which a voltage is applied during reading are separated, and the concentration of the diffusion layer to which a voltage is applied during reading is made lower than before. As a result, the voltage applied to the diffusion layer at the time of reading does not change, but the electric field applied to the ultrathin silicon oxide film is effectively reduced and the amount of electrons emitted from the first gate is reduced. Can do.
[0080]
That is, by reducing the concentration of the diffusion layer, the depletion layer spreads more than the conventional depletion layer in the N-type diffusion layer immediately below the first gate at the time of reading.
[0081]
(B) Since the source region and the drain region are formed separately, the drain region has a single drain structure instead of the DDD structure, so that the effective gate length of the memory cell can be made smaller than the above (A). In addition, the same effect as the above (A) can be obtained with respect to the resistance to charge loss during reading.
[0082]
(C) Since the high-concentration N-type diffusion layer is formed in a part of the common source region, the diffusion layer resistance of the source region can be reduced, and the read access speed is improved. In addition, since the concentration of the N-type diffusion layer immediately below the first gate of the memory cell can be kept low, the charge removal resistance of the non-selected cell at the time of reading has the same effect as the above (1). can get.
[0083]
(D) Since the source line diffusion layer resistance can be reduced by forming a high-concentration N-type diffusion layer in a part of the source line, the access time at the time of reading can be improved. In addition, since the source region and the drain region can be generated independently, the drain diffusion layer can be made a single drain, so that the effective gate length is shortened and the cell size can be reduced.
[0084]
(E) Since a high-concentration N-type diffusion layer can be formed in a common source region and the N-type diffusion layer concentration immediately below the first gate can be lowered, It can be suppressed similarly to A). In addition, since the diffusion layer resistance of the source region is further reduced as compared with the above (A) and (B), the access speed at the time of reading can be further improved.
[0085]
(F) Even in a general SAS formation process, the concentration of the source diffusion layer immediately below the gate of the memory cell can be kept low without increasing the number of mask steps, thereby improving the charge retention resistance during reading. it can.
[Brief description of the drawings]
FIGS. 1A and 1B are cross-sectional views (part 1) illustrating a manufacturing process of a nonvolatile semiconductor device according to a first embodiment of the invention. FIGS.
FIG. 2 is a manufacturing process cross-sectional view of the nonvolatile semiconductor device according to the first embodiment of the present invention (No. 2).
FIG. 3 is a manufacturing process cross-sectional view (No. 3) of the nonvolatile semiconductor device showing the first embodiment of the invention;
FIG. 4 shows a nonvolatile semiconductor device according to the first embodiment of the present invention. Lead It is a figure explaining a bias condition.
FIGS. 5A and 5B are cross-sectional views illustrating main steps of manufacturing a nonvolatile semiconductor device according to a second embodiment of the present invention. FIGS.
FIG. 6 is a cross-sectional view of a main part manufacturing process of a nonvolatile semiconductor device showing a third embodiment of the invention.
FIG. 7 is a cross-sectional view of the essential part manufacturing process of a nonvolatile semiconductor device showing a fifth embodiment of the invention.
FIG. 8 is a cross-sectional view of the essential part manufacturing process of a nonvolatile semiconductor device showing a sixth embodiment of the present invention.
FIG. 9 is a structural diagram (No. 1) of a conventional nonvolatile semiconductor memory device;
FIG. 10 is a structural diagram (No. 2) of a conventional nonvolatile semiconductor memory device.
FIG. 11 is a structure diagram (No. 3) of a conventional nonvolatile semiconductor memory device.
FIG. 12 is a diagram showing a program bias condition of a conventional nonvolatile semiconductor device.
FIG. 13 is a diagram showing a read bias condition of a conventional nonvolatile semiconductor device.
[Explanation of symbols]
31 P-type silicon substrate
32 Device isolation oxide film
33 Ultra-thin silicon oxide film
34 First gate
35 Silicon oxide film
36 Polycrystalline silicon film
37 refractory metal film
38 photoresist
39 Thermally oxidized silicon film
40a, 51, 72a, 81 Source region
40b, 53, 71, 72b, 84 Drain region
41 High concentration diffusion layer
42, 43, 50, 52, 60, 70, 80, 83 photoresist
73 PSG membrane
74 sidewall
75 High-concentration N-type diffusion layer region

Claims (4)

A plurality of memory elements each arranged in a matrix on a P-type semiconductor substrate, each of which has a floating gate and a control gate, is composed of an N-type diffusion region, and extends in one direction; A word line composed of a control gate provided parallel to the source region and sandwiching the source region, and an N-type diffusion region provided at a position facing the source region across the word line a plurality of drain regions, is composed of a plurality of bit lines electrically connected to the plurality of drain regions formed by extending in a direction crossing the word lines, one or, select the read condition of the memory device A positive voltage is applied to the word line and the source region, the selected bit line potential is grounded, and the unselected word line and the unselected bit line are grounded and floated, respectively. It A method of manufacturing a nonvolatile semiconductor memory device according to claim,
(A) after forming the word line, forming an N-type diffusion layer in a source region and a drain region in a self-aligned manner with the word line;
(B) forming a N-type diffusion layer having a higher concentration than the N-type diffusion layer in the drain region using a photoresist as a mask.   2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein a first conductive layer is formed for forming the floating gate, and the first conductive layer is parallel to a bit line using a photoresist as a mask. Patterning, forming an N-type diffusion layer in the region of the source line where the first conductive layer is removed, forming a second conductive layer to be a control gate, and forming a word line A process for manufacturing a nonvolatile semiconductor memory device. A plurality of memory elements each arranged in a matrix on a P-type semiconductor substrate, each of which has a floating gate and a control gate, is composed of an N-type diffusion region, and extends in one direction; A word line composed of a control gate provided parallel to the source region and sandwiching the source region, and an N-type diffusion region provided at a position facing the source region across the word line a plurality of drain regions, is composed of a plurality of bit lines electrically connected to the plurality of drain regions formed by extending in a direction crossing the word lines, one or, select the read condition of the memory device A positive voltage is applied to the word line and the source region, the selected bit line potential is grounded, and the unselected word line and the unselected bit line are grounded and floated, respectively. It A method of manufacturing a nonvolatile semiconductor memory device according to claim,
(A) after forming the word line, forming a N-type diffusion layer in the drain region using a photoresist as a mask;
(B) forming an N-type diffusion layer having a lower concentration than the N-type diffusion layer simultaneously in the source region and the drain region in a self-aligned manner with the word line;
(C) forming a sidewall film made of an insulating film on a side surface of the word line;
(D) forming a N-type diffusion layer having a higher concentration than the N-type diffusion layer formed in the source region in a self-aligned manner with respect to the sidewall film and the word line; Manufacturing method of semiconductor memory device. A plurality of memory elements each arranged in a matrix on a P-type semiconductor substrate, each of which has a floating gate and a control gate, is composed of an N-type diffusion region, and extends in one direction; A word line composed of a control gate provided parallel to the source region and sandwiching the source region, and an N-type diffusion region provided at a position facing the source region across the word line a plurality of drain regions, is composed of a plurality of bit lines electrically connected to the plurality of drain regions formed by extending in a direction crossing the word lines, one or, select the read condition of the memory device A positive voltage is applied to the word line and the source region, the selected bit line potential is grounded, and the unselected word line and the unselected bit line are grounded and floated, respectively. It A method of manufacturing a nonvolatile semiconductor memory device according to claim,
(A) after forming the word line, removing the insulating film in a self-aligned manner with respect to the word line in contact with the source region using a photoresist as a mask, and forming the source line;
(B) forming an N-type diffusion layer in the source region using the photoresist as a mask;
And (c) forming a N-type diffusion layer having a concentration higher than that of the N-type diffusion layer formed in the source region in the drain region using a photoresist as a mask. Method.

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