JP2729622B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a nonvolatile memory transistor comprising a floating gate type field effect transistor, and a semiconductor memory device comprising a field effect transistor for selecting the memory transistor. It is about.

(Prior Art) Conventionally, as one of nonvolatile memory elements that can be electrically written and erased, a nonvolatile memory transistor including a floating gate type field effect transistor that performs writing and erasing by tunneling injection is known.
In this floating gate type nonvolatile memory transistor, charge is tunnel-injected from a semiconductor substrate through a thin insulating layer, charges are accumulated in a floating gate electrode on an insulating film, and information is obtained by changing a threshold voltage of the transistor. The principle is to memorize.

Such a floating gate type nonvolatile memory transistor is connected to an EEPROM (Electrically Erasable and Progra
mable ROM) and other semiconductor integrated circuits,
Usually, in addition to the nonvolatile memory transistor, it is necessary to coexist a field effect transistor for selecting the memory transistor. Therefore, the memory cell of the conventional semiconductor memory device has a sectional structure as shown in FIG. In the figure, 1 is a P-type silicon substrate,
2, 3, and 4 are N-type diffusion layers, 5 is a silicon oxide film, and 6 'is a second
7 is a thin silicon oxide film which can be a tunneling medium, 8 is a silicon oxide film, 9 is a floating gate electrode made of a first polysilicon film, 10 is a silicon oxide film, and 11 is a silicon oxide film. 2 is a control gate electrode made of a polysilicon film,
12, 13 are N-type diffusion layers.

(Problems to be Solved by the Invention) In the above-mentioned conventional memory cell structure, the floating gate electrode 9 is formed of a first polysilicon film, and the control gate electrode 11 and the selection gate electrode 6 'are formed of a second polysilicon film. Therefore, in addition to the N-type diffusion layers 2, 3, and 4 formed in a self-aligned manner using the control gate electrode 11 and the selection gate electrode 6 as masks, the N-type diffusion layer 12 and the It is necessary to provide N-type diffusion layers 12 and 13 for determining the channel length of the memory transistor. Therefore, in the conventional memory cell structure as shown in FIG. 2, the manufacturing process becomes complicated, the overlap margin between the N-type diffusion layers 12 and 13 and the floating gate electrode 9, the N-type diffusion layer 2 and the select gate It is necessary to consider a separation margin with the electrode 6 ', and the structure is difficult to be highly integrated. In the memory cell having the floating gate structure as shown in FIG. 2, the thickness of the silicon oxide film 10 is reduced as much as possible to improve the performance (high speed, low voltage rewriting, etc.). In the conventional memory cell structure, since the control gate electrode 11 and the select gate electrode 6 'are formed of the same polysilicon film, the silicon oxide film 5 under the select gate electrode 6' The silicon oxide film 10 under the control gate electrode 11 is usually formed at the same time, and if the thickness of the silicon oxide film 10 is reduced, the thickness of the silicon oxide film 5 is also reduced at the same time. When the thickness of the silicon oxide film 5, which is a gate insulating film below the select gate electrode, is reduced, when a high voltage of 0V is applied to the select gate and 20 to 25V is applied to the N-type diffusion layer 2 at the time of writing information, the gate electrode The electric field between the N-type diffusion layers greatly affects the electric field between the N-type diffusion layer and the substrate,
Electric field concentration occurs in the channel region near the N-type diffusion layer, and N
There is a drawback that breakdown occurs between the mold diffusion layer and the substrate or the silicon oxide film portion on the region is easily broken,
This was one obstacle in circuit design.

SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional disadvantages and to simplify a manufacturing process in a memory cell structure including a floating gate type nonvolatile memory transistor and a field effect transistor for selecting the memory transistor. Another object of the present invention is to provide a method of manufacturing a semiconductor memory device that can significantly reduce the cell area.

(Means for Solving the Problems) The method of manufacturing a semiconductor memory device according to the present invention is directed to a method of manufacturing a semiconductor memory device, comprising: a first conductive type semiconductor substrate having a first, second and third conductive types opposite to a substrate provided apart from each other; A first gate insulating film on a first channel region sandwiched between the first and second diffusion layers; a select gate electrode on the first gate insulating film; An insulating film that can serve as a tunneling medium at a predetermined portion on the surface of the diffusion layer; a second gate insulating film over a second channel region sandwiched between the second and third diffusion layers; And a floating gate electrode on both insulating films of the second gate insulating film,
In a method of manufacturing a semiconductor memory device having a control gate electrode via an insulating film on the floating gate electrode, the tunneling insulating film is formed so as to be located inside and away from an end of the floating gate electrode, Further, the first, second and third diffusion layers are
The select gate electrode and the floating gate electrode are used as a mask to form a self-alignment, and the self-aligned second diffusion layer is allowed to reach below the tunneling insulating film. It is formed so as to cover the floating gate electrode.

(Operation) According to the memory cell structure of the present invention, it is not necessary to determine the channel length of the memory transistor and to provide the N-type diffusion layer provided for the diffusion layer in the tunneling region as shown in FIG. Since the manufacturing process can be simplified and the channel length of the memory transistor can be determined and the diffusion layer of the tunneling region can be determined in a self-aligned manner, the memory cell area can be significantly reduced.

Embodiment An embodiment of the present invention will be described with reference to FIG. First
FIG. 2 is a cross-sectional view of a memory cell according to the method for manufacturing a semiconductor memory device of the present invention. In this figure, the same parts as those in the conventional example shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, a silicon oxide film 5 serving as a gate insulating film of a MOS transistor for selecting a memory cell and a silicon oxide film 8 serving as a gate insulating film of a memory transistor are formed at the same time by about 700.degree. Then, only a predetermined portion of the silicon oxide film is opened by a photo-etching technique. After that, a thin silicon oxide layer 7 that can serve as a tunneling medium is placed on the silicon substrate 1 at the opening.
Formed by oxidation of In order to effectively use the tunneling effect, the thickness of the silicon oxide layer 7 needs to be reduced by about 50 to 150 °, and is set to 100 ° in this embodiment.

Next, phosphorus was doped on the silicon oxide films 5, 7, 8 (3.
× 10 ²⁰ cm approximately ^-3) select gate electrode 6 made of the first polysilicon layer to form the floating gate electrode 9.
In this embodiment, the thickness of the first polysilicon film is 5000 °.

Next, phosphorus ions are implanted (50 KeV, 1 × 10 ¹⁵ cm ⁻² ) by a self-alignment technique using the select gate electrode 6 and the floating gate electrode 9 as masks to form N-type diffusion layers 2, 3, and 4. After that, heat treatment is performed until a part of the surface region of the N-type diffusion layer 3 reaches below the tunneling silicon oxide film 7. In this embodiment, the heat treatment was performed at 1000 ° C. in a nitrogen atmosphere.

Next, a silicon oxide film 10 is formed on the floating gate electrode 9 to have a thickness of about 500 ° by a normal thermal oxidation method. After that, phosphorus was doped (about 3 × 10 ²⁰ cm ⁻³ )
A second polysilicon film is formed by about 4000 ° by a vapor phase epitaxy method, and then a control gate electrode 11 made of the second polysilicon film is formed by a photo etching technique,
A semiconductor memory device is manufactured.

According to the present invention, the channel length of the floating gate type nonvolatile memory transistor and the diffusion layer of the tunneling region can be determined in a self-aligned manner. Significant reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a structural sectional view for explaining a method of manufacturing a semiconductor integrated circuit in one embodiment of the present invention, and FIG. 2 is a structural sectional view of a conventional floating gate type nonvolatile memory cell. 1 ... P-type silicon substrate, 2,3,4 ... N-type diffusion layer, 5 ...
... A silicon oxide film, 6... A select gate electrode made of a first polysilicon film, 7... A thin silicon oxide film that can be a tunneling medium, 8, 10... A silicon oxide film, 9. Floating gate electrode,
11 ... Control gate electrode made of the second polysilicon film.

Continuing on the front page (72) Inventor Shinichi Hatakeyama 1006 Kazuma Kadoma, Kazuma, Osaka Prefecture Inside Matsushita Denshi Kogyo Co., Ltd. References JP-A-62-113478 (JP, A) JP-A-61-61470 (JP, A) JP-A-63-43377 (JP, A) JP-A-57-114282 (JP, A)

Claims (1)

(57) [Claims] A first diffusion layer provided on a surface region of the one-conductivity-type semiconductor substrate, the first, second, and third diffusion layers having opposite conductivity types to the one-conductivity-type semiconductor substrate; Second
A first gate insulating film on a first channel region sandwiched between the first and second diffusion layers, a select gate electrode on the first gate insulating film, and a predetermined portion on a surface of the second diffusion layer. An insulating film that can serve as a tunneling medium; a second gate insulating film on a second channel region sandwiched between the second and third diffusion layers;
A method of manufacturing a semiconductor memory device having a floating gate electrode on both insulating films of the gate insulating film and a control gate electrode on the floating gate electrode with an insulating film interposed therebetween, comprising: Forming the first, second, and third diffusion layers in a self-aligned manner using the select gate electrode and the floating gate electrode as a mask; Wherein the second diffusion layer formed in conformity with the second diffusion layer reaches below the tunneling insulating film, and thereafter, the control gate electrode is formed so as to cover the floating gate electrode. Production method.