JPS6255710B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory, and more particularly to a method of manufacturing an insulated gate nonvolatile semiconductor memory.

The applicant previously filed the specification of Japanese Patent Application No. 52-9911 (Showa
(filed on January 31, 1952), we proposed a new nonvolatile semiconductor memory device and its manufacturing method. In this proposed device, the control gate electrode and the floating gate electrode are self-aligned at least along the channel direction, and the source and drain regions are formed in self-alignment with respect to both electrodes. . It was shown that by adopting such a structure, the dimensions of the device can be minimized and the maximum effect can be achieved in terms of characteristics.

On the other hand, this kind of so-called SAMOS in general
(Stacked-Gate Avalanche-Injection MOS)
When using an electron injection method known as "channel injection method" for what is called memory, the higher the substrate surface concentration in the channel region, the more likely the injection will occur, and the so-called 〓writing'' will occur. To facilitate this, a method is known in which impurities of the same type and high concentration as the substrate are added to the surface of the substrate, which will become the channel region, by ion implantation, etc., for example, as described in Proceedings of the 1976 International
An example is given in Electron Device Meeting, pp. 173-176. However, increasing the substrate surface concentration in this channel region increases the threshold voltage of the memory transistor and therefore decreases the conductance of the memory transistor, and in order to obtain the necessary conductance, the dimensions of the memory transistor must be increased. This comes with the serious drawback of having to do so. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor memory device using a channel implantation method, which can minimize the above-mentioned drawbacks.

The insulated gate nonvolatile semiconductor memory obtained by the manufacturing method of the present invention includes a pair of regions having a conductivity type opposite to that of the substrate, which are spaced apart from each other near the main plane of the substrate, and a small number of these regions. a region having the same shape as the substrate and having a high impurity concentration provided in contact with one of the two regions, a floating gate electrode embedded in an insulating film on the main plane between the pair of regions, and an external gate electrode on the outer surface. , wherein the floating gate electrode is shaped in a self-aligned manner with respect to the external gate electrode, and the high concentration region and the pair of regions are also shaped in a self-aligned manner with respect to the external gate electrode. have.

The method for manufacturing an insulated gate nonvolatile semiconductor memory of the present invention relates to a method for stably and easily realizing the preferred structure as described above, and includes a first gate insulator on a main plane of a predetermined semiconductor substrate. A step of forming a first conductive film made of a conductor or semiconductor on this, a step of forming a second gate insulating film on this, and a step of forming a second conductive film made of a conductor or semiconductor on this. forming a conductive film, patterning the second conductive film to determine the shape of the external gate electrode, and patterning the first conductive film in self-alignment with the external gate electrode to form a floating The process of determining the shape of the gate electrode, and the step of applying impurities of the same shape and higher concentration as the substrate in a self-aligned manner to both the external gate electrode and the floating gate electrode whose shapes are determined in a self-aligned manner to each other near the main plane. The step of adding an impurity that gives each of the two types of gate electrodes a conductivity type opposite to that of the substrate in a self-aligned manner is added in the vicinity of the principal plane, and the high concentration region of the same type as the substrate also has a self-doping step. forming a matched substrate and a pair of regions having opposite conductivity types.

Next, in order to make the characteristics of this invention easier to understand,
Several embodiments will be described in detail with reference to the drawings.

1A to 1I are cross-sectional model diagrams showing an example of the manufacturing process of an insulated gate nonvolatile semiconductor memory related to the present invention.

In FIG. 1A, a SiO ₂ film 3 with a thickness of about 1 μm is formed on one principal plane 2 of a P-type Si semiconductor substrate 1 with a specific resistance of about 100 Ω-cm by a thermal oxidation method, and then later by a standard PR technique. Openings 4 are made in the SiO ₂ film 3 on the portions that are to become the source, channel, and drain regions to expose a portion of the substrate surface 2, and a layer of about 1000 Å thick is formed on the exposed substrate surface by thermal oxidation. 1 gate
A SiO ₂ film 5 is formed. In B, a first polycrystalline silicon film 6 having a thickness of about 1000 Å is grown on the entire surface by thermal decomposition of SiH ₄ in N ₂ . Next, the shape of the polycrystalline silicon film 6 in the drawing, that is, in the direction perpendicular to the channel direction is determined using standard PR technology. C
Next, a conductive type impurity is added to the first polycrystalline silicon film 6, and a second gate SiO ₂ film 7 having a thickness of about 1000 Å is formed by thermal oxidation. On top of this in D
A second polycrystalline silicon film 8 having a thickness of approximately 5000 Å is formed by thermal decomposition of SiH ₄ in N ₂ . In E, a mask layer 9 whose shape has been determined for patterning is formed on the second polycrystalline silicon film 8. Next, in F, using 9 as a mask, first determine the shape of the second polycrystalline silicon film 8, then partially remove the second gate SiO ₂ film 7, and then shape the first polycrystalline silicon film 6. Then, by partially removing the first gate SiO ₂ film 5, an external gate electrode consisting of the second polycrystalline silicon film 8 and the first polycrystalline silicon film 6 are formed in a mutually self-aligned manner. A floating gate electrode consisting of is obtained. In G, boron is applied in a self-aligned manner to both electrodes whose shapes are determined in a self-aligned manner as described above, at an energy of E=50 Kev and a dose of φ=4×10 ¹³ cm ^-2
After ion implantation at 1100° C. in N ₂ for 3 hours, P-type high concentration regions 10 and 11 are formed.
In H, after removing the mask layer 9, phosphorus is self-alignedly diffused into both electrodes whose shapes are determined in a self-aligned manner as described above, and phosphorus is added to the external gate electrode and the P-type region 10 , 11 as well, self-aligned N-type source regions 12 and drain regions 13 are formed. The following steps are similar to the known N-channel silicon gate technology: forming the SiO ₂ film 14, opening contact holes 15, 16, 17, forming the Al source extraction electrode 18, external gate extraction electrode 19, and drain extraction electrode 20. Complete the device as shown in I.

In this device, a positive voltage is applied to the external gate extraction electrode 19 to bring the source and drain into a conductive state, and hot electrons accelerated by a high electric field between the source and drain are injected into the floating gate electrode 6, which is a so-called channel. Writing is performed by increasing the threshold voltage of the memory transistor as viewed from the external gate lead-out electrode 19 using the injection method. At this time, since the shapes of the external gate electrode 8 and the floating gate electrode 6 are determined in a self-aligned manner, the injection effect due to the voltage applied to the external gate electrode 8 is maximized, and the device size is not increased in any way. Nor. Next, when erasing this memory device, both optical and electrical methods are possible. In the optical method, for example, by irradiating the device with ultraviolet rays, electrons injected into the floating gate electrode 6 are excited with energy and emitted to the substrate 1 or the external gate electrode 8. At this time, in the memory device of the present invention, the shapes of the external gate electrode 8 and the floating gate electrode 6 are determined in a self-aligned manner, so that the shielding effect of the external gate electrode 8 on the irradiated ultraviolet rays is small, so that erasing can be easily performed in a short time. The big advantage is that you can do it. Next, in the electrical erasing method, for example, the external gate lead electrode 19
is grounded, or a high positive voltage is applied to the source extraction electrode 18 with a negative voltage applied to break the P-N junction between the source N-type region 12, the P-type region 10, and the substrate 1. let it down,
Of the hot electron-hole pairs generated at this time, only the holes are selectively injected into the floating gate electrode 6 depending on the direction of the electric field in the first gate SiO ₂ film 5, and the charges are canceled out with the electrons already injected. This is done by During this hole injection, for exactly the same reasons as mentioned above for electron injection, the device of the present invention has the excellent advantage that the injection effect is maximized and erasing can be easily performed in a short time. . During a read operation of this memory device, for example, a positive voltage is applied to the external gate lead-out electrode 19, and it is confirmed that the source and drain are conductive when in the erased state, and non-conductive when written. This is done by making a distinction. During this read operation, it is desirable that the conductance of the memory device in the erased state is as high as possible; however, in the device of the present invention, the P-type regions 10 and 11, which have a higher concentration than the substrate, are the source and drain regions 1.
2 and 13 in a self-aligned manner, and are localized very close to each other, the decrease in conductance due to the P-type regions 10 and 11 is minimized, so that the necessary and sufficient conductance can be obtained even with a sufficiently small device size. There is an advantage. Furthermore, since the source and drain regions 12 and 13 are formed in a self-aligned manner with respect to both the external gate electrode 8 and the floating gate electrode 6, so-called mirror capacitance is small, and characteristics such as high frequency operation are also excellent. There is.

In this way, this insulated gate nonvolatile semiconductor memory is far superior to conventional devices in all write, erase, and read operations.

FIG. 2 is a cross-sectional model diagram showing a reference example of an insulated gate type nonvolatile semiconductor memory related to the present invention. In FIG. 2, the numbers indicating the outside of the device correspond to those in FIG. 1. In the device shown in FIG. 2, the heavily doped P-type region 11 is provided only in the vicinity of the drain N-type region 13. In this example, an extra mask step is required, and although writing is the same as in the case of FIG. 1, reading is determined on the source side and is therefore susceptible to the influence of the depletion layer from the drain.

3A to 3J are cross-sectional model views showing an example of the manufacturing process of the insulated gate type nonvolatile semiconductor memory of the present invention. The same parts of the apparatus in this figure as in FIG. 1 are designated by the same numbers. These FIGS. 3A and 3B are basically completely the same as FIGS. 1A and 1B. In step C, the first polycrystalline silicon layer 6 is roughly patterned also in the channel direction. D
Next, phosphorus is added to the first polycrystalline silicon layer whose rough shape has been determined, and a second gate SiO ₂ film 7 having a thickness of about 1000 Å is grown by a thermal oxidation method. 1st in E
A second polycrystalline silicon layer 8 and a mask layer 9 are formed in the same manner as in FIGS. D and E. In F, using 9 as a mask, the shape of the second polycrystalline silicon layer 8 is determined and the second gate SiO ₂ film 7 is partially removed. In G, a highly doped P-type region 10,
To form No. 11, boron ions are implanted at energy E=150 Kev and dose φ=4×10 ¹³ cm ⁻² , and then indentation is performed at 1100° C. in N ₂ for 3 hours. H
Then energy E=150Kev, dose φ=1×
Phosphorus is ion-implanted at 10 ¹⁴ cm ^-2 to form N-type regions 21 and 22 in a self-aligned manner between external gate electrode 8 and P-type regions 10 and 11. In I, the first gate SiO ₂ film 5 is partially removed using the first polycrystalline silicon layer as a mask, the mask layer 9 is also removed, and phosphorus is diffused to form the source N-type region 12 and drain N-type region. 13 and addition of phosphorus to the external gate electrode 8 made of the second polycrystalline silicon layer;
Further, phosphorus is added to the exposed portion of the first polycrystalline silicon layer 6 at the same time. At this time, the source and drain regions 12 and 13 and the N-type regions 21 and 22 are automatically connected to each other. In J, by utilizing the difference in film thickness between the first and second polycrystalline silicon layers 6 and 8,
The portion of the first polycrystalline silicon layer 6 located outside the external gate electrode 8 is heated with SiO ₂ by thermal oxidation.
At the same time, a SiO ₂ film 23 is formed on the external gate electrode 8 and the exposed substrate surface. J to K are the same known N as explained in Example 1.
The device is completed using channel silicon gate technology.

This K insulated gate nonvolatile semiconductor memory also includes an external gate electrode 8, a floating gate electrode 6, highly doped P-type regions 10 and 11, and a source region (12+2
1) and the drain region (13+22) are formed in self-alignment with each other, so that the advantages of the present invention detailed in the embodiment shown in FIG. 1 are fully exhibited.

FIG. 4 shows an insulated gate nonvolatile semiconductor memory according to the present invention which has been modified in exactly the same way as the embodiment shown in FIG. 1 has been modified to the embodiment shown in FIG.

It is clear from the above description that the several embodiments described above are merely for illustrative purposes and the present invention is not limited thereto. For example, it is possible to change the materials, dimensions, and manufacturing methods of each part of the device, and to some extent it is also possible to change the conductivity type and conductivity type impurities, as well as the polarity of the voltages to be applied to various electrodes in various operating states. be.

[Brief explanation of the drawing]

1A to 1I are cross-sectional model views showing an example of the manufacturing process of an insulated gate type nonvolatile semiconductor memory according to a reference example of the present invention, and in particular, FIG. 1A is a completed view thereof. FIG. 2 is a cross-sectional model diagram showing another reference example of the present invention, FIGS. 3 A to K are cross-sectional model diagrams showing an example of the manufacturing process of the embodiment of the present invention, and in particular, K is a completed view thereof, and FIG. FIG. 2 is a cross-sectional model diagram showing still another embodiment of the present invention. In these figures, 1... P-type Si semiconductor substrate, 2... main plane of 1, 3, 14, 23...
SiO ₂ film, 4... Openings made in SiO ₂ film, 5...
First gate SiO ₂ film, 6...First polycrystalline Si layer, 7
...Second gate SiO ₂ film, 8...Second polycrystalline Si
Layer 9... Mask layer, 10, 11... P-type high concentration region, 12, 13... Source, drain N-type region, 15, 16, 17... Source, external gate,
Drain contact hole, 18, 19, 20...source, external gate, drain extraction electrode, 2
1, 22...N type region.

Claims (1)

[Claims] 1. A step of forming a first conductive layer pattern to become a floating gate electrode through a first insulating film uniformly formed on an element formation region of a semiconductor substrate;
forming a second conductive layer pattern which becomes an external gate electrode and has a smaller area than the first pattern on the conductive layer pattern;
forming a shallow portion by ion implantation in a self-aligned manner with the second pattern;
using the pattern as a mask to remove the first insulating film except under the first pattern, and diffusing impurities from the removed portions of the first insulating film to form each of the source and drain regions. forming a second portion connected to the extraction electrode deeply in self-alignment with the first pattern;
a step of re-patterning the pattern using the second pattern as a mask so as to overlap the second mask.