JPS6286764A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the occupying area of a cell by a method wherein a gate electrode is provided with a double-layer structure in which an insulating film is sandwiched by two layers of the gate material and a conductive material layer is formed on the side wall of the gate electrode corresponding to the lower gate material layer with an insulating film in between. CONSTITUTION:An oixde film 14 and a polycrystalline film 15 is formed on a substrate 13 and the polycrystalline film 15 is left only a part where a cell is to be formed by photoetching. After an oxide film 16 for element isolation is made to grow, a floating gate 15 is formed. At that time, the oxide film 14 is removed by etching and an oxide film 17 is made to grow as a 1st gate oxide film. After that, the gate 15 is subjected to thermal oxidization to make an oxide film 19 grow and the oxide film 19 and the gate 15 are removed by etching with a gate 18 as a mask. Then ions are implanted with those gate electrodes as a mask to form regions 20 and 21. Then the gate 16 is oxidized to form a thermal oxide film 22. Then an electrode 23 is formed by patterning and electrons is the gate 15 are drawn out by applying a voltage to the electrode 23 for erasing. with this constitution, the occupying area per one cell can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides an electrically erasable and electrically rewritable RO.
This relates to M (Read Only Memory).

[Conventional technology]

Conventional EEPROM (Electrical
Brasable and Programmable
The structure of the read only memory is shown in FIG. This device is a Si gate N-channel MNO
5 technology. Two transistors are required to provide one memory function. One transistor is a read MOS transistor having a gate electrode 10, and the other is an MNOS transistor having a silicon nitride film 12 and a gate electrode 11 and having a memory function. Charges are tunneled from the substrate through a thin oxide film and stored in traps near the oxide film-nitride interface, providing a memory function. (Nikkei Electronics 1
9B2.5.24 P, P, 154-168) [Problems to be Solved by the Invention] As shown in Figure 2, the EEFROM of the conventional structure has a circuit function as one memory. In order to do this, two MOS transistors are required: a read transistor and a memory transistor. Therefore, there was a problem in that the area occupied by one cell became large.

[Means for solving problems]

In the present invention, an erasing electrode 23 is provided on the side of the floating gate 15 under the gate electrode via an insulating film 22.
By applying a voltage to this electrode, the electrons in the floating gate 15 are pulled out to perform an erasing operation, and one transistor is provided with reading, selection, and memory functions, thereby solving the above problems.

[Effect]

Conventionally, the Fowler-Norde signal used when erasing
A thin oxide film for the heim tunnel current to flow was formed on the N2 diffusion layer in the source region, and the area of this N2 diffusion layer had to be made large. Therefore, in the present invention, instead of performing the erase operation as a F-N channel current from above the N1 diffusion layer, a thin insulator 22 capable of tunneling is provided on the side surface of the floating gate 15, and a conductor 23 is grown on top of the thin insulator 22. This solved the problems of the conventional method.

A voltage is applied to this conductor 23 and the floating gate 1
Since the charge is extracted from the inside of 5 as a tunnel current by an electric field and erased, it is no longer necessary to take up an unnecessarily large area as in conventional devices.

〔Example〕

A method of manufacturing an EEFROM according to the present invention will be explained based on FIGS. 1A to 1G.

First, an oxide film 14 and a polycrystalline film 15 are formed on a semiconductor substrate 13 (FIG. 1A). By photo-etching, the polycrystalline film 15 is left only in the cell formation area.

(Figure 1B). In FIG. 1C, an oxide film 16 for isolation between elements is shown.
The figure shows up to the point where a floating gate 15 for accumulating electrons is formed.

At this time, the oxide film 14 is etched off to grow the oxide film 14 as a first gate oxide film. Thereafter, before patterning the control gate 18, the floating gate 15 is thermally oxidized to grow a second gate oxide film 19 (FIG. 1D). Then, using this control gate 18 as a mask, the second gate oxide film 19 and floating gate 15 are removed by etching, and using these gate electrodes as a mask, ion implantation is performed to form source/drain regions 20.21 (FIG. 1E). ). After this, the floating gate 15 is oxidized to form a thermal oxide film 22 of about 200 to 300 layers, which is used as a tunnel oxide film (see Fig. 1F).
). Then, an electrode 23 for performing an erasing operation is formed by patterning (FIG. 1G). By applying a voltage to this electrode 23, the electrons in the floating gate 15 are pulled out and erased. Erasing is done using electrodes 15 and 23.
Fowler-Nordheim due to the electric field between
Take advantage of the channel effect.

〔effect〕

Compared to conventional devices, the area occupied by each cell is smaller. Moreover, the EEFROM of the present invention can be manufactured by a manufacturing method that is less complicated than conventional manufacturing processes.

[Brief explanation of drawings]

FIGS. 1A to 1G show each step of manufacturing the EEPROM of the present invention. FIG. 2 shows the structure of a conventional EEPROM. 1...N-type substrate 2...P-well13...
- Source or drain 4...Drain or source 5...Source or drain 6...Inter-element isolation region 7...Interlayer insulating film 8.9...AI electrode 10-
...Gate electrode (Poly-Si) 11... Gate electrode 12... Silicon nitride 13... Semiconductor substrate 14... Oxide film 15... Floating gate 16... Element isolation oxide film 17. ...First gate oxide film 18...Control gate 19...Second gate oxide film 20...Source 21...Drain 22...
... Oxide film 23 ... Erasing electrode patent applicant Soni - Representative patent attorney Sawa Co., Ltd. 1) Masao and 1 other J-to Moe's EE
PROM player 5 people t41 Figure 1

Claims (1)

[Claims] In a MOS type semiconductor device, the gate material of the gate electrode has a two-layer structure with an insulating film interposed therebetween, and a conductive material is formed at least on the side of the gate electrode in the lower layer of the gate material with the insulating film interposed therebetween. A semiconductor device characterized by: