JP2001332709A - Nonvolatile semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor storage device wherein irregularity of threshold voltage of a nonvolatile semiconductor storage device can be reduced by isolating P wells every plural memory cells which are adjacent to each other in the lengthwise direction of a bit line diffusion layer and a common source diffusion layer, without increasing a cell array area and manufacturing cost. SOLUTION: In this method of manufacturing a nonvolatile semiconductor storage device, the following processes are included. A second and a first conductivity type wells 2, 3 are formed on a first conductivity type semiconductor substrate 1. A tunnel oxide film 4 and floating gates(FG) 5 stretching in the Y direction are formed on the first conductivity type well 3, and an impurity diffusion layer 7 is formed by using the FG's 5 as masks. The impurity diffusion layer 7 is divided into two parts in the X axis direction. Trenches which penetrate the impurity diffusion layer 7 and reach the second conductivity type well 2 are formed, and insulating films 12 are buried in the trenches.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly, to a method of manufacturing a plurality of memory cells adjacent to each other in a longitudinal direction of a pair of impurity diffusion layers arranged in parallel with each other. The present invention relates to a method for manufacturing a non-volatile semiconductor memory device that divides a well.

[0002]

2. Description of the Related Art Generally, a flash memory that stores electric charges in a floating gate has a plurality of memory cells arranged on the same word line and the same bit line, respectively. Are formed in the same well formed on the surface of the semiconductor substrate, and the bit lines are formed in the well by a diffusion layer. In such a flash memory, a memory cell is selected by a word line potential and a bit line potential,
Writing and erasing are performed on predetermined memory cells.
However, when a predetermined memory cell is selected for writing or erasing, if a voltage is applied to a word line and a bit line corresponding to the selected cell, even in a non-selected memory cell,
Voltage will be applied to the word line or bit line,
There has been a problem that disturb is given to non-selected cells.

For example, Japanese Patent Application Laid-Open No. 9-51
No. 043, in a memory cell in which writing and erasing is performed using an FN tunnel current over the entire channel region, a P-well is separated by a buried insulating film from a deep N-well surrounding the P-well for every plural cells in the bit line direction. A way to do that has been proposed. According to this method, it is possible to reduce disturbance to unselected cells, to perform bit-by-bit verification on both the erase side and the write side, and to reduce variations in threshold voltage. it can. However, according to this method, since a well is formed by forming a photoresist pattern and performing ion implantation, a margin for alignment is required, and there is a problem that a cell array area increases. Therefore, SOI
There has been proposed a method of isolating a P-well by forming a trench isolation film reaching a buried oxide film using a substrate having a (Silicon On Insulater) structure.

[0004] This method will be described with reference to FIGS. FIG. 3 is a schematic plan view showing an EEPROM cell array, and FIGS. 4A to 4D are AA ′ in FIG.
4 (a ') to 4 (d') are sectional views taken along line BB 'of FIG. First, as shown in FIGS. 4A and 4A, a P-well 23 is formed in a surface silicon layer of an SOI substrate composed of a silicon substrate 21, a buried oxide film 22, and a surface silicon layer. A plurality of trenches reaching the buried oxide film 22 are formed in the surface silicon layer.
A silicon oxide film is formed on the obtained SOI substrate, and the silicon oxide film 2 is formed in the trench by flattening the surface.
By embedding 0, the P well 23 is separated.

Next, as shown in FIGS. 5B and 5B, a tunnel insulating film 24, a polysilicon film and a silicon nitride film 26 are formed on the obtained SOI substrate, and these polysilicon films are formed. Then, the lower floating gate pattern 25 is formed by patterning the silicon nitride film 26. Using the patterned silicon nitride film 26 as a mask, arsenic is ion-implanted to form a bit line diffusion layer 7a and a source diffusion layer 7b.

Further, a silicon oxide film is deposited on the obtained SOI substrate. This silicon oxide film is etched back to form a lower floating gate pattern 2.
The space between the layers 5 is filled with a silicon oxide film 28, and the silicon nitride film 26 disposed on the lower floating gate pattern 25 is removed to flatten the surfaces of the lower floating gate pattern 25 and the silicon oxide film 28.
Thereafter, a polysilicon film is deposited on the obtained SOI substrate, phosphorus ions are implanted into the polysilicon film, and the polysilicon film is patterned to form a lower floating layer as shown in FIGS. 5C and 5C. An upper floating gate pattern 29 is formed on the gate pattern 25.

Next, as shown in FIGS. 5D and 5D, the S including the upper floating gate pattern 29 is formed.
An ONO film 30 and a polysilicon film are sequentially formed on the OI substrate, and upper and lower floating gate patterns 29 and 25 are formed.
A resist pattern (not shown) having an opening extending in a direction perpendicular to the direction is formed, and using this resist pattern as a mask, the polysilicon film, the ONO film 30, and the upper and lower floating gate patterns 29, 25 are continuously etched. Then, a tunnel insulating film 24, upper and lower floating gates 29a and 25a, an ONO film 30, and a control gate 31 are formed. Thereby, a memory element is formed in a region surrounded between the bit diffusion layer 27a and the source diffusion layer 27b previously formed in the surface silicon layer.
Thereafter, an insulating film (not shown) is formed on the entire surface of the SOI substrate, connection holes are opened, and metal wiring is formed.

However, in this method of manufacturing a nonvolatile semiconductor memory device, it is necessary to use an SOI structure substrate which is more expensive than a bulk semiconductor substrate or a wafer formed by epitaxial growth in order to separate the P well 23 by a trench separation film. There is a problem that manufacturing costs increase. The present invention has been made in view of the above problems, and has been made in order to reduce the variation in the threshold voltage of a nonvolatile semiconductor memory device without increasing the cell array area and without increasing the manufacturing cost. P is set for each of a plurality of memory cells adjacent in the length direction of the diffusion layer and the common source diffusion layer.
It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of separating wells and a method for manufacturing the same.

[0009]

According to the present invention, (a)
A first conductivity type semiconductor substrate is provided with a second conductivity type well and the second conductivity type well.
Forming a first conductive type well located on the conductive type well; (b) forming a tunnel insulating film and a lower floating gate extending in the Y-axis direction on the first conductive type well; (c) Forming an impurity diffusion layer using the lower floating gate as a mask, and then forming an upper floating gate; and (d) dividing the impurity diffusion layer into two parts in the X-axis direction using the upper floating gate as a mask. And a step of forming, in a self-aligned manner, a trench penetrating through the impurity diffusion layer and reaching the second conductivity type well, and (e) a step of embedding an insulating film in the trench. A manufacturing method is provided. Further, according to the present invention, there is provided a nonvolatile semiconductor memory device obtained by the above method.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION In a nonvolatile semiconductor memory device of the present invention, a first conductivity type well having a plurality of memory cells is mainly composed of a second conductivity type well disposed thereunder and an impurity of an adjacent memory cell. A plurality of memory cells are separated from each other by a trench isolation film reaching the second conductivity type well formed between the diffusion layers.

A nonvolatile semiconductor memory device according to the present invention has a first
It is formed on a conductive semiconductor substrate. Examples of the semiconductor substrate used here include elemental semiconductors such as silicon and germanium, and compound semiconductors such as GaAs, InGaAs, and ZnSe. Among them, silicon is preferred. The semiconductor substrate preferably has a resistance value controlled by doping with an N-type impurity such as phosphorus or arsenic or a P-type impurity such as boron, and more preferably a P-type semiconductor substrate.

In the semiconductor substrate, a second conductivity type well is formed in a partial region or the entire surface, and a first conductivity type well is formed on the second conductivity type well. The well may have an impurity concentration or a depth which is usually formed when a semiconductor device is formed. For example, the second conductivity type well has a height of 0.5 to 3 μm from the substrate surface.
Suitably, it is formed with a thickness of about 1 μm and an impurity concentration of about 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ⁻³ . The first conductivity type well disposed on the second conductivity type well has, for example, a depth of about 1.5 to 2 μm from the substrate surface and an impurity of about 5 × 10 ¹⁶ to 2 × 10 ¹⁷ cm ^−3. Suitably, it is formed in a concentration. Note that the first conductivity type well and the second conductivity type well are preferably formed in contact with each other. The semiconductor substrate may have one or more other wells in other regions, or may be formed by combining semiconductor elements and circuits such as transistors and capacitors, insulating films, wiring layers, and the like. .

A nonvolatile semiconductor memory device according to the present invention comprises a plurality of memory cells arranged in a matrix on the first conductivity type well of the semiconductor substrate. The memory cell mainly includes a tunnel insulating film, a floating gate, a pair of impurity diffusion layers, an insulating film, and a control gate. The tunnel insulating film is, for example, a silicon oxide film, a silicon nitride film, or a stacked film thereof.
It is appropriate that the thickness is about 7 to 15 nm.

The floating gate is not particularly limited as long as it is formed of a conductive film. For example, polysilicon is a metal such as copper and aluminum; and a single material of a high melting point metal such as tungsten, tantalum and titanium. A layer film or a laminated film; silicide with a high melting point metal; polycide, etc., of which polysilicon is preferred. The thickness of the floating gate is 100 to 150 n
m. The floating gate is not particularly limited as long as it has a shape such that a control gate to be described later is partially or entirely covered. For example, the floating gate may have a single-layer structure with a substantially rectangular or trapezoidal cross section. And
A laminated structure having a cross-sectional shape of a substantially convex shape, an inverted convex shape, or the like may be used. Among them, a two-layer structure having an inverted convex cross section is preferable.

The impurity diffusion layer is formed as a pair on both sides of the floating gate in the X-axis direction. Although the impurity concentration of the impurity diffusion layer is not particularly limited, for example, 1 × 10
^{About 20 to} 5 × 10 ²⁰ cm ⁻³ . These impurity diffusion layers function as source / drain regions. However, in a memory cell adjacent in the Y-axis direction, one of the impurity diffusion layers may be connected to function as a bit line. preferable. It is preferable that a plurality of the other impurity diffusion layers are connected and function as a common source. Note that the connection between adjacent impurity diffusion layers may be performed by connecting a wiring layer to each impurity diffusion layer. However, when each impurity diffusion layer extends in the Y-axis direction, Preferably they are connected to each other.

The insulating film and the control gate disposed on the floating gate can be selected from the same materials as the tunnel insulating film and the floating gate, respectively. In this case, the thicknesses of the insulating film and the control gate are each 14 to 20 nm.
About 150 to 200 nm. Note that, as described above, the control gate is preferably arranged so as to cover the floating gate, and is arranged so as to extend over a plurality of memory cells adjacent in the X-axis direction. Is preferred.

In the nonvolatile semiconductor memory device of the present invention, a trench isolation film reaching the second conductivity type well is formed between impurity diffusion layers in memory cells adjacent in the X-axis direction. Thus, the first conductivity type well is separated for each of the plurality of memory cells arranged in the Y-axis direction.

The trench isolation film is formed by burying an insulating film in a trench formed in a semiconductor substrate. The shape of the trench is not particularly limited as long as it is arranged between the impurity diffusion layers of adjacent memory cells, and it is preferable that the shape be such that the impurity diffusion layers can be separated from each other in the X-axis direction. . When a plurality of impurity diffusion layers are connected in the Y-axis direction, it is preferable that the shape is such that the plurality of connected impurity diffusion layers can be separated from each other in the X-axis direction. The width of the trench may be any size as long as the impurity diffusion layers can be electrically separated from each other. The depth of the wrench is
The depth can be appropriately adjusted depending on the depth of the first conductivity type well and the like. For example, the depth may completely penetrate the first conductivity type well and reach the second conductivity type well, or may be the first conductivity type well. The depth may not completely penetrate the mold well. However, in the latter case, it is necessary that the surface of the second conductivity type well partially protrudes so as to contact the bottom of the trench. The insulating film for filling the trench can be appropriately selected and used from the same materials as the tunnel insulating film and the like. Note that the insulating film preferably has a film thickness that completely fills the trench.

According to the method for manufacturing a nonvolatile semiconductor memory device of the present invention, first, in the step (a), a second conductive type well and a position above the second conductive type well are formed on a semiconductor substrate of a first conductive type. And a first conductivity type well to be formed. Any of these wells may be formed first. The method of forming the well may be to form the first and second conductivity type wells by selecting implantation energy in consideration of the range of N-type or P-type impurities by ion implantation, for example, or a semiconductor substrate. Doping an N-type impurity such as phosphorus or arsenic or a P-type impurity such as boron during the crystal growth of the second conductivity type well and the first conductivity type well in the first conductivity type semiconductor substrate. Alternatively, the second conductivity type well and the first conductivity type well may be doped on the semiconductor substrate of the first conductivity type by doping impurities while epitaxially growing the semiconductor.
The conductivity type well may be formed in this order, or the second conductivity type well and the first conductivity type well may be formed in this order by selecting appropriate conditions and the like by plasma doping, vapor phase diffusion or solid phase diffusion. You may. Above all, ion implantation is preferable.

In step (b), a tunnel insulating film and a lower floating gate extending in the Y-axis direction are formed on the first conductivity type well. The tunnel insulating film can be formed by, for example, a thermal oxidation method, a sputtering method, an evaporation method, a CVD method, or the like. The floating gate is formed by forming the above-described conductive material over almost the entire surface of the semiconductor substrate by a sputtering method, an evaporation method, a CVD method, or the like, and patterning the conductive material into a predetermined shape by a photolithography and etching process. be able to. The shape of the floating gate in this case is not particularly limited, but is a preliminary shape until it finally becomes a shape that can function as a floating gate of a semiconductor memory device, that is, a final shape in the X-axis direction. However, it is preferable that the gate electrode has a stripe shape which extends in the Y-axis direction and can serve as a mask when forming an impurity diffusion layer in a later step.

In step (c), an impurity diffusion layer is formed using the lower floating gate as a mask.
It is preferable that the impurity diffusion layer is formed by implanting an impurity by ion implantation at an appropriate dose so that the impurity concentration is in the above-described range. At this time, it is preferable to perform ion implantation by selecting an appropriate implantation energy that usually forms an impurity diffusion layer that can function as a source / drain region of the semiconductor memory device.

In the case where the floating gate is formed with two or more layers, the upper floating gate is formed in this step after forming the impurity diffusion layer using the lower floating gate as a mask. Forming the upper floating gate substantially in step (b)
The lower floating gate can be formed in the same manner as described above, but it is preferable that the lower floating gate be completely covered and a mask having an opening wider in the X-axis direction than the lower floating gate is used.

In the step (d), the impurity diffusion layer is divided into two in the X-axis direction, and a trench penetrating through the impurity diffusion layer and reaching the second conductivity type well is formed. The trench can be formed by forming a mask having an opening at a position where the impurity diffusion layer can be divided into two in the X-axis direction, and using this mask by a dry etching method, a wet etching method, or the like. It is necessary to divide the impurity diffusion layers so that the divided impurity diffusion layers can function as a source / drain region, a bit line, and / or a common source of the semiconductor device, respectively.

If an upper floating gate wider than the lower floating gate is formed in the step (c) in step (c), the mask used for patterning the upper floating gate is used as a mask for dividing the impurity into two. It can be used as it is. Further, the upper floating gate may be used as a mask. Thus, a trench can be formed in a self-aligned manner with respect to the upper floating gate, and a mask step for forming the trench can be omitted.

The trench formed in this step is preferably formed to a depth penetrating the impurity diffusion layer, completely penetrating the first conductivity type well, and reaching the second conductivity type well. Accordingly, the second well in which the first conductivity type well is disposed therebelow only by embedding the insulating film in the trench in a later step.
It can be separated by the conductivity type well and the insulating film (trench element isolation film) in the trench.

In this step, when the trench is formed at a depth penetrating the impurity diffusion layer but not reaching the second conductivity type well, subsequently, the second conductivity type impurity is ion-implanted into the trench bottom. Then, the second conductivity type well is projected. As a result, a trench that finally reaches the second conductivity type well can be formed. Here, the ion implantation of the second conductivity type impurity is performed by the depth of the formed trench and the first impurity.
It is necessary to appropriately select the conditions under which the second conductivity type impurity diffusion layer connected to the second conductivity type well can be formed in consideration of the depth of the conductivity type well and the like.

In the step (e), an insulating film is buried in the trench. The insulating film is appropriately selected from those described above, and is formed on almost the entire surface of the semiconductor substrate including the trench by a sputtering method, an evaporation method, a CVD method, or the like.
Wet etching using hot phosphoric acid, nitric acid, sulfuric acid, etc.
It can be embedded by etching back by various methods such as dry etching such as RIE and CMP (chemical mechanical polishing). Especially, it is preferable to use the etch back by the CMP method.

After the above steps, an insulating film and a conductive film serving as a control gate are usually formed on the floating gate, for example. The insulating film and the conductive film can be formed by the above materials and methods. Thereafter, a resist pattern having an opening extending in the X-axis direction is formed on the conductive film, and the control gate, the insulating film, and the floating gate are continuously etched using the resist pattern as a mask. Thus, the floating gate can be patterned in a self-aligned manner with respect to the control gate.

In the method of manufacturing a nonvolatile semiconductor memory device according to the present invention, ion implantation, heat treatment, formation of an insulating film, formation of a contact hole, and / or formation of a wiring layer are performed before, during, and after a desired step. By performing the above, a nonvolatile semiconductor memory device can be completed. An embodiment of a method for manufacturing a semiconductor memory device according to the present invention will be described below with reference to FIGS.

FIG. 1 is a schematic plan view showing a part of a cell array of an N-channel floating gate type EEPROM, and FIGS. 2A to 2D are cross-sectional views taken along the line AA 'of FIG. 2 (a ') to (d') are cross-sectional views taken along line BB 'of FIG. First, as shown in FIGS. 2A and 2A, phosphorus is added to a P-type silicon substrate 1 by 2.5 to 3 MeV.
Ion implantation at a dose of 1-5 × 10 ¹² cm ^-2 , and further, boron is implanted at 100 KeV and 250 K.
Change the implantation energy to eV, 500 KeV, 1-5 ×
Ion implantation at a dose of 10 ¹² cm ^-2 , heat treatment,
An N well 2 is placed at a depth of about 3 μm and a depth of 1.5 to 2
A P well 3 is formed at a position of about μm.

Next, a silicon oxide film having a thickness of about 8 to 10 nm is formed as a tunnel insulating film 4 on the silicon substrate 1 by a thermal oxidation method.
Polysilicon film of about 100 nm and thickness of 150 to 2
A silicon nitride film 6 of about 50 nm is sequentially formed. The polysilicon film and the silicon nitride film are patterned using photolithography and dry etching techniques to form a lower floating gate pattern 5.
Subsequently, arsenic is ion-implanted into the silicon substrate 1 using the silicon nitride film 6 as a mask, and an N ⁺ diffusion layer 7 is formed between the lower floating gate patterns 5.

Thereafter, as shown in FIGS. 2B and 2B, thermal oxidation is performed using the silicon nitride film 6 as a mask, and then a silicon oxide film 8 is deposited by a CVD method. The silicon oxide film 8 is etched back to bury the silicon oxide film 8 between the lower floating gate patterns 5, and
The upper silicon nitride film 6 is removed, and the surfaces of the lower floating gate pattern 5 and the silicon oxide film 8 are flattened. A polysilicon film having a thickness of about 50 to 100 nm is formed thereon, and phosphorus is ion-implanted. A silicon nitride film 10 having a thickness of about 100 to 150 nm is formed on the polysilicon film by a CVD method. The silicon nitride film 10 and the polysilicon film are patterned into a predetermined shape to form an upper floating gate pattern 9.

Next, as shown in FIGS. 2C and 2C, using the silicon nitride film 10 as a hard mask, the silicon oxide film 8 between the lower floating gate patterns 5, and then the N ⁺ diffusion The layer 7 and the P well 3 are etched by reactive ion etching to form a trench. Subsequently, phosphorus is applied to the bottom of the trench by 50 to 150 Ke.
Ion implantation is performed at an implantation energy of V to form an N ^- diffusion layer 11 connected to the N well 2, and the P well is completely electrically separated. Subsequently, the silicon substrate 1 including the trench
A silicon oxide film having a thickness of about 500 nm is deposited thereon by the CVD method, and the trench is filled with the silicon oxide film 12 by etching back.

Next, the silicon nitride film 10 on the upper floating gate pattern 9 is removed, and a silicon oxide film having a thickness of about 7 nm is formed on the entire surface of the silicon substrate 1 including the upper floating gate pattern 9 by thermal oxidation.
Silicon nitride film of about 9 nm thickness by VD method, reduced pressure C
An ONO film 13 is formed by sequentially depositing a silicon oxide film having a thickness of about 4 nm by a VD method. This ONO
A polysilicon film having a thickness of about 150 nm is formed on the film 13 by a low pressure CVD method, and a predetermined resist pattern is formed in a direction orthogonal to the upper and lower floating gate patterns 9 and 5 by photolithography and etching techniques. Using this resist pattern as a mask,
Polysilicon film, ONO by reactive ion etching
By patterning the film 13 and the upper and lower floating gate patterns 9 and 5 sequentially, as shown in FIGS.
The NO film 13 and the upper and lower floating gates 9a and 5a are formed.

As a result, a memory element is formed in a region surrounded by the N ⁺ diffusion layer 7 previously formed in the silicon substrate 1 and between the bit line diffusion layer 7a and the source diffusion layer 7b. The P well 3 can be separated for each of a plurality of cells in the vertical direction. Thereafter, an insulating film (not shown) is formed on the entire surface of the semiconductor substrate by a known technique,
A connection hole is opened and a metal wiring is formed.

[0036]

According to the method of manufacturing a nonvolatile semiconductor device of the present invention, after forming an impurity diffusion layer between floating gates, a trench is formed so as to divide the impurity diffusion layer into two. It is not necessary to provide a separate margin only for performing the operation, and the area occupied by the cell array can be reduced.
Only by forming a well and a trench element isolation film without using an I-structure substrate, a well can be separated for each of a plurality of memory cells, and a reduction in manufacturing cost can be realized. In particular, when the trench is formed by using the mask in the case of forming the floating gate as it is, the manufacturing process can be simplified, the manufacturing cost can be further reduced, and the floating gate can be formed. As a result, the trench can be formed in a self-aligned manner, so that the occupied area of the cell array can be further reduced.

After the trench is formed, the second conductivity type impurity is introduced into the bottom of the trench to ensure the connection between the trench and the second conductivity type well. The first without control
Separation of the conductivity type well can be performed.

Further, according to the nonvolatile semiconductor memory device of the present invention, the side surface of the first conductivity type well whose bottom is covered by the second conductivity type well is completely formed by the trench isolation film reaching the second conductivity type well. Since the first conductivity type well is separated for each of the plurality of memory cells,
It is possible to suppress the influence of disturb, which has conventionally been a problem, and to provide a highly reliable device. Moreover, since the trench isolation film is located between the impurity diffusion layers of the adjacent memory cells, the area occupied by the cell array does not increase.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a main part showing a nonvolatile semiconductor memory device of the present invention.

2 (a) to 2 (d) are schematic cross-sectional process diagrams taken along the line AA 'of FIG. 1 for describing a method of manufacturing a nonvolatile semiconductor memory device, and FIGS. FIG. 2 is a schematic cross-sectional process drawing along a line BB ′ in FIG. 1.

FIG. 3 is a schematic plan view of a main part showing a conventional nonvolatile semiconductor memory device.

FIGS. 4A to 4D are schematic cross-sectional process views taken along the line AA 'of FIG. 3 for explaining the method of manufacturing the nonvolatile semiconductor memory device; FIGS. FIG. 4 is a schematic sectional process view taken along the line BB ′ of FIG. 3.

[Explanation of symbols]

Reference Signs List 1 P-type silicon substrate (first conductivity type semiconductor substrate) 2 N well (second conductivity type well) 3 P well (first conductivity type well) 4 Tunnel insulating film 5 Lower floating gate pattern 5 a Lower floating gate 6 Silicon nitride film 7 N ⁺ diffusion layer (impurity diffusion layer) 8 silicon oxide film 9 upper floating gate pattern 9 a upper floating gate 10 silicon nitride film 11 N ⁻ diffusion layer (projection of second conductivity type well) 12 silicon oxide film (trench element isolation) Film) 13 ONO film (insulating film) 14 control gate

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Masahisa Wada 22-22, Nagaike-cho, Abeno-ku, Osaka City, Osaka F-term (reference) 5F001 AA25 AA30 AA43 AA63 AB08 AD05 AD12 AD60 AD61 AD63 AD80 AG07 AG10 AG30 5F083 EP05 EP23 EP55 GA27 HA06 JA04 JA35 JA36 JA37 JA39 JA53 KA07 KA08 NA01 NA04 PR03 PR07 PR29 PR38 5F101 BA07 BA12 BA36 BB05 BD02 BD31 BD35 BD36 BD38 BD40 BH14 BH16 BH19

Claims (3)

[Claims] (A) a second conductive type semiconductor substrate is provided with a second conductive type semiconductor substrate;
Forming a conductive type well and a first conductive type well located on the second conductive type well; and (b) forming a tunnel insulating film and a lower floating gate extending in the Y-axis direction on the first conductive type well. (C) forming an impurity diffusion layer using the lower floating gate as a mask, and thereafter forming an upper floating gate; and (d) forming an impurity diffusion layer using the upper floating gate as a mask. Forming a trench through the impurity diffusion layer and reaching the second conductivity type well in a self-aligning manner, and (e) embedding an insulating film in the trench. A method for manufacturing a nonvolatile semiconductor memory device, comprising: 2. In the step (d), after forming a trench penetrating the impurity diffusion layer but not reaching the second conductivity type well, ion implantation of a second conductivity type impurity is performed at the bottom of the trench to form a second conductivity type impurity. By forming well projections,
The method of claim 1, wherein a trench is formed to reach the second conductivity type well. 3. A non-volatile semiconductor memory device formed by the method according to claim 1.