JP2004006433A - Semiconductor memory device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device for higher density of a peripheral circuit transistor, and to provide its manufacturing method. <P>SOLUTION: The semiconductor memory device comprises a semiconductor substrate 10 provided with an NAND cell array comprising a gate part in which adjoining memory cells share a source/drain diffusion layer 16, with each memory cell comprising an electric charge storage layer, and a peripheral circuit transistor. Gate parts SG and CG of the NAND cell array and a gate electrode 17b of the peripheral circuit transistor are formed by patterning with the same electrode material film. Silicone oxide films 21a and 21b fill between the gate parts SG and CG of the NAND cell array. The side surface of the gate electrode 17b of a peripheral circuit transistor is covered with the silicone oxide film 21b. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device using a NAND cell array and a method for manufacturing the same.
[0002]
[Prior art]
As a nonvolatile semiconductor memory, an EEPROM capable of electrically rewriting data is known. Normally, a MOS transistor having a stacked gate structure in which a floating gate as a charge storage layer and a control gate are stacked is used for the memory cell of the EEPROM.
[0003]
Among the EEPROMs, a NAND type EEPROM is most suitable for increasing the capacity. In the NAND type EEPROM, a plurality of adjacent memory cells form a NAND cell unit connected in series so as to share a source / drain diffusion layer, and a plurality of NAND cell units are arranged to form a NAND cell array. You. Both ends of each NAND cell unit are connected to a bit line and a common source line via a select gate transistor.
[0004]
Although the floating gate is separated for each memory cell, the control gate is continuously patterned as a word line (control gate line) common to the memory cells arranged in one direction. Similarly, the gate electrode of the select gate transistor is arranged in parallel with the word line as a select gate line. A bit line provided to cross the word line is connected to the diffusion layer of the drain-side select gate transistor of the NAND cell unit. A common source line is connected to the diffusion layer of the source-side select gate transistor of the NAND cell unit.
[0005]
[Problems to be solved by the invention]
In a NAND type EEPROM, it has already been proposed to form a gate portion of a NAND cell array and a gate electrode of a transistor of a peripheral circuit by a common process. In addition, a technique has been proposed in which a region between the NAND cell units is covered with a protective film such as a silicon nitride film by burying an insulating film between gate portions of the respective memory cells of the NAND cell unit.
[0006]
However, in the prior art, several problems arise when the size / space of the peripheral circuit transistor is reduced with the increase in capacity and function of the NAND type EEPROM. This will be specifically described with reference to FIG. FIG. 17 shows a state in which a main part of an element is formed by a common process in the area of the NAND cell unit (sele array area) and the peripheral circuit area. The gate portion of the memory cell of the NAND cell unit has a stacked structure of a floating gate 2 formed on a silicon substrate 1 via a tunnel insulating film and a control gate 4 formed on the floating gate 2 via an inter-gate insulating film. Have. This gate portion is patterned while being covered with the silicon nitride film 4. The gate electrode 5 of the peripheral circuit has a laminated structure of a double-layer polycrystalline silicon film forming the floating gate 2 and the control gate 3 of the NAND cell unit, and is also patterned so as to be covered with the silicon nitride film 4.
[0007]
On the NAND cell unit side, after patterning the gate portion, ion implantation is performed to form source / drain diffusion layers 6. Thereafter, a first silicon oxide film 7a and a second silicon oxide film 7b are deposited between the gate portions of the NAND cell unit and are buried almost flat. In the peripheral circuit, the first and second silicon oxide films 7a and 7b are deposited simultaneously with the cell array side, and thereafter, the source and drain diffusion layers 8 are formed by performing ion implantation.
[0008]
However, when two layers of silicon oxide films 7a and 7b are formed on the side surfaces of the gate electrodes of the peripheral circuit, as shown in FIG. This can result in offset gates that do not overlap. Also, when the distance between the gate electrodes is reduced, it becomes difficult to form a diffusion layer between the gate electrodes, and it is also difficult to make a wiring contact at the same time.
[0009]
In order to prevent the gate from becoming an offset gate, for example, as in the case of the source / drain diffusion layer 6 on the cell array side, ion implantation is performed before depositing the silicon oxide films 7a and 7b to reduce the concentration of the source / drain diffusion. It is conceivable to form a layer. However, even in such a case, it is still difficult to form a high concentration source / drain diffusion layer and form a wiring contact.
[0010]
In some cases, a transistor of a peripheral circuit requires channel ion implantation using oblique ion implantation for threshold control before and after the step of forming a source / drain diffusion layer. In the state where the distance between the gate electrodes is reduced and two silicon oxide films 7a and 7b are formed on the side surfaces of the gate electrodes as shown in FIG. 17, such channel ion implantation becomes difficult.
[0011]
The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory device capable of increasing the density of peripheral circuit transistors and a method of manufacturing the same.
[0012]
[Means for Solving the Problems]
The present invention provides a semiconductor memory device in which a NAND cell array and a peripheral circuit transistor are formed on a semiconductor substrate, in which adjacent memory cells share a source / drain diffusion layer and each memory cell includes a gate portion having a charge storage layer. A gate portion of the NAND cell array is buried with first and second insulating films, and a side surface of a gate electrode of the peripheral circuit transistor is covered with the second insulating film.
[0013]
According to the present invention, it becomes possible to form peripheral circuit transistors formed by a process substantially similar to that of the NAND cell unit at minute intervals without impairing the performance thereof.
[0014]
More specifically, in the present invention, the gate portion of the NAND cell array and the gate electrode of the peripheral circuit are patterned while being covered with the third insulating film. In the wiring contact portion of the NAND cell array, the first and second insulating films are selectively removed, and the side surface of the wiring contact portion and the side surface of the gate electrode covered with the second insulating film of the peripheral circuit transistor are removed. It is assumed that it is covered with a fourth insulating film.
Preferably, the fourth insulating film is left so as to cover between the gate portions of the NAND cell array.
[0015]
A method of manufacturing a semiconductor memory device according to the present invention includes a step of forming an element isolation insulating film on a semiconductor substrate, and a step of forming, on the semiconductor substrate, a charge storage layer of a NAND cell unit in which adjacent memory cells share source and drain diffusion layers. Forming a gate portion and a gate electrode of a peripheral circuit, a step of depositing a first insulating film so as to cover a region of a cell array in which the NAND cell units are arranged and a region of a peripheral circuit; Removing a portion of the insulating film covering the region of the peripheral circuit, and depositing a second insulating film so as to cover the cell array and the region of the peripheral circuit and to bury between the gate portions of the NAND cell unit. Forming a source and drain diffusion layer of the peripheral circuit;
It is characterized by having.
[0016]
In the manufacturing method of the present invention, more specifically, the gate portion of the NAND cell unit and the gate electrode of the peripheral circuit are patterned in a state where the gate portion is covered with the third insulating film. Then, after depositing the second insulating film, a step of removing the first and second insulating films in the wiring contact portion of the NAND cell unit, and depositing a fourth insulating film covering a region of the cell array and the peripheral circuit. And a process. The step of forming the source and drain diffusion layers of the peripheral circuit may be performed by ion implantation after depositing the second insulating film or after depositing the fourth insulating film.
[0017]
The fourth insulating film may be removed leaving the side surface of the wiring contact portion and the side surface of the gate electrode covered with the second insulating film in the region of the peripheral circuit. Further, after depositing the second insulating film, etching the first and second insulating films until the third insulating film is exposed, and forming the first and second insulating contacts on the wiring contact portion of the NAND cell unit. The method may also include a step of removing the insulating film and a step of depositing a fourth insulating film covering a region of the cell array and the peripheral circuit. Also in this case, the step of forming the source and drain diffusion layers of the peripheral circuit may be performed by ion implantation after depositing the second insulating film or after depositing the fourth insulating film.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
1A and 1B to 8 are cross-sectional views showing a manufacturing process of a NAND type EEPROM according to one embodiment. 1A and FIGS. 2 to 8, the NAND cell array shows a cross section along a bit line, and FIG. 1B shows a cross section along a word line in a process corresponding to FIG. 1A.
[0019]
FIGS. 1A and 1B show that a gate portion of a NAND cell unit (a gate portion CG of a memory cell and a gate portion SG of a select gate transistor on a bit line side and a source side) are formed on a silicon substrate 10 to form a peripheral circuit region. The state where the gate electrode 17 is formed is shown. The NAND cell unit has a large number of memory cells such as 16 or 32 and select gate transistors at both ends thereof. FIG. 1A shows only the vicinity of the bit line contact portion.
[0020]
The steps so far will be specifically described. Necessary wells (p-type wells in the NAND cell array region and wells required in the p-channel and n-channel regions in the peripheral circuit region) are formed in the silicon substrate 10, but are not shown. Then, a gate insulating film 11 (a tunnel insulating film 11a for a memory cell, a gate insulating film 11b for a select gate transistor, and a gate insulating film 11c for a peripheral circuit transistor) necessary for each element region of the silicon substrate 10 are formed.
[0021]
Thereafter, a first-layer polycrystalline silicon film used as the floating gate 12 is deposited, a mask film such as a silicon nitride film (not shown) is formed thereon, and these are etched to form an element isolation groove 18. Thus, the first-layer polycrystalline silicon film is self-aligned with the element isolation region and patterned so as to remain only in the element formation region. Thereafter, a silicon oxide film 19 is buried in the element isolation groove 18 as an element isolation insulating film. The buried depth of the silicon oxide film 19 is set so that the upper surface is located in the middle of the film thickness of the polycrystalline silicon film to be the floating gate 12.
[0022]
Further, after removing the mask on the first-layer polycrystalline silicon film, a laminated insulating film 13 of a silicon oxide film (O) / silicon nitride film (N) / silicon oxide film (O) serving as an inter-gate insulating film is deposited. . After unnecessary portions of the laminated insulating film 13, that is, portions of the select gate transistor region and the peripheral circuit transistor region of the cell array are removed by etching, a second-layer crystalline silicon film serving as a control gate 14 and a silicon nitride film 15 are sequentially deposited. . The removal of the laminated insulating film 13 may be performed not only in the transistor region in the peripheral circuit region but also in the entire surface. Next, the silicon nitride film 15 and the two-layer polycrystalline silicon film are sequentially etched by RIE to form the floating gate 12 and the control gate 14 of the NAND cell unit, and at the same time, the gate electrode 17a of the select gate transistor and the peripheral circuit. A gate electrode 17b of the transistor is formed. The gate electrode 17a of the select gate transistor and the gate electrode 17b of the peripheral circuit are formed as a laminated structure of a two-layer polycrystalline silicon film.
[0023]
The gate electrode 17a of the select gate transistor and the control gate 14 of the memory cell are continuously patterned as shown in FIG. 1B to become a select gate line and a word line, respectively. The gate portions SG and CG of the NAND cell array and the gate electrode 17b of the peripheral circuit are patterned so as to be covered with the silicon nitride film 15 as described above. Thereafter, ion implantation is performed in the NAND cell array region to form the source and drain diffusion layers 16.
[0024]
Thereafter, as shown in FIG. 2, a first silicon oxide film (first insulating film) 21a covering the NAND cell array and the peripheral circuit region is deposited. Then, as shown in FIG. 3, the peripheral circuit region of the first polycrystalline silicon film 21a is etched away. Subsequently, as shown in FIG. 4, a second silicon oxide film (which covers the entire surface of the substrate so as to bury the gate portions SG and CG of the NAND cell array flat except for the bit line contact portion and the common source line contact portion. A second insulating film 21b is deposited. At this time, in the peripheral circuit region, the second silicon oxide film 21b covers the side surface of the gate electrode 17b, but a gap between the gate electrodes is secured.
[0025]
Thereafter, in the peripheral circuit region, ion implantation is performed to form source / drain diffusion layers 22. Although only the n-channel MOS transistor region is shown in the figure, p-type source and drain diffusion layers are formed in the p-channel region. Further, before and after the formation of the diffusion layer 22, channel ion implantation by oblique ion implantation is performed to adjust the threshold value of each transistor.
[0026]
Unlike the conventional case where the side surface of the gate electrode 17b of the peripheral circuit is covered with two layers of silicon oxide films 21a and 21b, this embodiment is only covered with one layer of silicon oxide film 21b. The source and drain diffusion layers 22 without offset are formed. In addition, since a sufficient ion implantation space is provided between the gate electrodes 17b, oblique ion implantation for controlling a threshold value is easy.
[0027]
After the device forming process is completed as described above, as shown in FIG. 5, the bit line contact portions in the cell array region and the silicon oxide films 21a and 21b in the source line contact portions (not shown) are selectively etched. Subsequently, as shown in FIG. 6, a silicon nitride film 23 is deposited to protect the gate sidewall exposed at these contact portions. The silicon nitride film 23 is also formed on the side surface of the gate electrode 17b covered with the silicon oxide film 21b of the peripheral circuit.
[0028]
With the silicon nitride film 23, it is possible to reliably prevent a short circuit between the wiring and the gate in the process of contacting the metal wiring of the NAND cell array and the peripheral circuit. In the contact portion of the NAND cell array, since the silicon oxide films 21a and 21b are removed to form the silicon nitride film 23, a large contact diameter can be secured.
[0029]
Next, an interlayer insulating film 24 such as BPSG is deposited, and as shown in FIG. 7, flattening is performed by CMP processing or fluidization by heat treatment. FIG. 7 shows a state obtained by performing CMP until the silicon nitride film 15 is exposed.
[0030]
Thereafter, a metal wiring is formed according to a normal process. That is, as shown in FIG. 8, an interlayer insulating film 25 is deposited, and metal wirings 27a and 27b in a cell array region and a peripheral circuit region are formed thereon. In the example shown in the figure, contact plugs 26a and 26b connected to the diffusion layer are buried in the interlayer insulating film 25 of the wiring contact portion, and the metal wires 27a and 27b are buried in the interlayer insulating film 25 by the damascene method. The case where the connection is made to the diffusion layer via 26a and 26b is shown.
[0031]
According to this embodiment, the first silicon oxide film is removed in the peripheral circuit region in the step of burying the space between the gate portions of the NAND cell array with the first and second silicon oxide films. Therefore, as shown in FIG. 4, in the source / drain diffusion layer forming step of the peripheral circuit, the side wall insulating film of the gate electrode 17b is not formed so thick. The drain diffusion layer 22 can be formed. In addition, contact with the source / drain diffusion layer 22 can be ensured.
[0032]
Note that the ion implantation step of forming the source / drain diffusion layers 22 of the peripheral circuit can also be performed after forming the silicon nitride film 23 on the side wall of the gate electrode 17b as shown in FIG. In this case, a gate offset may occur depending on the thicknesses of the silicon nitride film 23 and the silicon oxide film 21b. To avoid this, for example, before and after the step of forming a source / drain diffusion layer in a NAND cell array. Then, at the stage of FIG. 1A, low-concentration source and drain diffusion layers may be formed also in the peripheral circuit. If the ion implantation at the stage of FIG. 6 is made high in concentration, the peripheral circuit transistor has an LDD structure.
[0033]
[Embodiment 2]
In the first embodiment, the silicon nitride film 23 formed in the step of FIG. 6 is left as it is at the bottom of the wiring contact portion. Therefore, the etching of the silicon oxide film and the etching of the silicon nitride film must be performed when forming the contact holes. In particular, in the peripheral circuit region, since there is a laminated film of the silicon oxide film 21b and the silicon nitride film 23 at the bottom of the contact portion, a silicon oxide film, a silicon nitride film, It is necessary to sequentially etch the silicon oxide film. Therefore, when the contact becomes deep with a fine dimension, a low-resistance wiring contact may not be able to be obtained due to etching residue or the like. When forming a diffusion layer of a peripheral circuit in the state of FIG. 6, ions must be implanted through a stacked film of the silicon oxide film 21b and the silicon nitride film 23, and the ion implantation conditions become strict.
[0034]
In order to solve these difficulties, the silicon nitride film 23 formed in FIG. 6 may be removed leaving only the side walls of each gate. The manufacturing process of such an embodiment is shown in FIGS. 1A and 1B to FIG. 6 are the same as those of the previous embodiment. Thereafter, the silicon nitride film 23 is etched by RIE to leave only the contact portions of the cell array and the gate electrode sidewalls in the peripheral circuit region as shown in FIG.
[0035]
Thereafter, as in the previous embodiment, an interlayer insulating film 24 is deposited and flattened as shown in FIG. Further, as shown in FIG. 11, an interlayer insulating film 25 is deposited, and metal wirings 27a and 27b are formed.
According to this embodiment, there is no silicon nitride film above the wiring contact portion of the cell array and the diffusion layer in the peripheral circuit region, and contact formation is facilitated. Further, if the ion implantation is performed in the state of FIG. 9, the diffusion layer of the peripheral circuit can be easily formed.
[0036]
[Embodiment 3]
Next, an embodiment in which a region of the NAND cell array is completely covered with a silicon nitride film will be described. 1A and 1B to 4 described in the first embodiment. That is, similarly to the first embodiment, a state is obtained in which the NAND cell array region is covered with the two-layer silicon oxide film and the peripheral circuit region is covered with only the second silicon oxide film of the two-layer silicon oxide film. Thereafter, the silicon oxide film is etched by RIE to expose the silicon nitride film 15 as shown in FIG. At this time, recesses of the two-layered silicon oxide films 21a and 21b are formed between the gate portions of the NAND cell array. Although the figure shows a state in which a V-shaped dent is formed, it becomes a U-shaped dent depending on the etching conditions. In the contact portion of the NAND cell array and the gate electrode of the peripheral circuit, the silicon oxide film is formed only on the side wall.
[0037]
Hereinafter, the same steps as those of the first embodiment are performed. That is, as shown in FIG. 13, the bit line contact portions in the cell array region and the silicon oxide films 21a and 21b in the source line contact portions (not shown) are selectively etched. Subsequently, as shown in FIG. 14, a silicon nitride film 23 is deposited to protect the gate sidewall exposed at these contact portions. Next, an interlayer insulating film 24 such as BPSG is deposited, and flattened by a CMP process or fluidization by a heat treatment as shown in FIG. FIG. 15 shows a state obtained by performing CMP polishing until the silicon nitride film 15 is exposed.
[0038]
In this state, since the silicon nitride film 23 is embedded in the recess formed by the oxide film etching of the NAND cell array, the entire NAND cell array is completely covered by the silicon nitride films 15 and 23.
[0039]
Thereafter, a metal wiring is formed according to a normal process. That is, as shown in FIG. 16, an interlayer insulating film 25 is deposited, and metal wirings 27a and 27b in a cell array region and a peripheral circuit region are formed thereon. In the example shown in the figure, contact plugs 26a and 26b connected to the diffusion layer are buried in the interlayer insulating film 25 in the wiring contact portion, and the metal wires 27a and 27b are buried in the interlayer insulating film 25 by the damascene method. The case where the connection is made to the diffusion layer via 26a and 26b is shown.
[0040]
As described above, according to this embodiment, in addition to the effect of the above-described embodiment, since the NAND cell array region is completely covered with the silicon nitride film, impurity diffusion such as hydrogen from the upper portion to the memory cell region is performed. And the effect of suppressing the deterioration of the memory cell characteristics can be obtained.
[0041]
【The invention's effect】
As described above, according to the present invention, it becomes possible to form peripheral circuit transistors formed by a process substantially similar to that of the NAND cell unit at minute intervals without impairing the performance thereof.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view along a bit line for describing a process up to formation of a gate electrode of a NAND cell and a peripheral circuit transistor according to the embodiment of the present invention;
FIG. 1B is a cross-sectional view along a word line corresponding to FIG. 1A.
FIG. 2 is a cross-sectional view showing a step of depositing a first-layer silicon oxide film of the embodiment.
FIG. 3 is a sectional view of a step of removing a first-layer silicon oxide film in a peripheral circuit region according to the embodiment;
FIG. 4 is a sectional view showing a step of depositing a second-layer silicon oxide film and forming a diffusion layer of a peripheral circuit according to the embodiment.
FIG. 5 is a cross-sectional view showing a step of etching a silicon oxide film of the bit line contact portion according to the embodiment.
FIG. 6 is a cross-sectional view showing a step of depositing a silicon nitride film of the embodiment.
FIG. 7 is a cross-sectional view showing a planarization step of the embodiment.
FIG. 8 is a cross-sectional view showing a metal wiring forming step of the embodiment.
FIG. 9 is a cross-sectional view showing a silicon nitride film etching step after a step corresponding to FIG. 6 according to another embodiment;
FIG. 10 is a cross-sectional view showing a planarization step (corresponding to FIG. 7) of the embodiment.
FIG. 11 is a cross-sectional view showing a metal wiring forming step (corresponding to FIG. 9) of the embodiment.
FIG. 12 is a cross-sectional view showing a silicon oxide film etching step after a step corresponding to FIG. 4 according to another embodiment;
FIG. 13 is a cross-sectional view showing a step (corresponding to FIG. 5) of etching the silicon oxide film of the bit line contact portion according to the embodiment.
FIG. 14 is a cross-sectional view showing a step (corresponding to FIG. 6) of depositing a silicon nitride film of the embodiment.
FIG. 15 is a cross-sectional view showing a planarization step (corresponding to FIG. 7) of the embodiment.
FIG. 16 is a cross-sectional view showing a metal wiring forming step (corresponding to FIG. 8) of the embodiment.
FIG. 17 is a cross-sectional view for explaining a problem of a conventional NAND type EEPROM.
[Explanation of symbols]
Reference Signs List 10: silicon substrate, 11a, 11b, 11c: gate insulating film, 12: floating gate, 13: inter-gate insulating film, 14: control gate, 15: silicon nitride film, 16: source and drain diffusion layers, 17a, 17b ... Gate electrode, 18: isolation trench, 19: isolation insulating film, 21a, 21b: silicon oxide film, 23: silicon nitride film, 24, 25: interlayer insulating film, 26a, 26b: contact plug, 27a, 27b: metal wiring.

Claims (11)

In a semiconductor memory device, a NAND cell array and a peripheral circuit transistor are formed on a semiconductor substrate, in which adjacent memory cells share a source / drain diffusion layer and each memory cell has a gate portion having a charge storage layer.
A space between the gates of the NAND cell array is buried with first and second insulating films,
A semiconductor memory device, wherein a side surface of a gate electrode of the peripheral circuit transistor is covered with the second insulating film. A gate portion of the NAND cell array and a gate electrode of a peripheral circuit are buttered while being covered with a third insulating film;
The first and second insulating films are selectively removed from a wiring contact portion of the NAND cell array; and
2. The semiconductor memory device according to claim 1, wherein a side surface of the wiring contact portion and a side surface of the gate electrode of the peripheral circuit transistor covered with the second insulating film are covered with a fourth insulating film. 3. The semiconductor memory device according to claim 2, wherein said fourth insulating film is left so as to cover between gate portions of said NAND cell array. 4. The semiconductor memory device according to claim 2, wherein said first and second insulating films are silicon oxide films, and said third and fourth insulating films are silicon nitride films. The gate portion of the NAND cell array has a floating gate as a charge storage layer made of a first-layer polycrystalline silicon film, and a control made up of a second-layer polycrystalline silicon film laminated on the floating gate via an inter-gate insulating film. 2. The semiconductor memory device according to claim 1, further comprising a gate, wherein a gate electrode of said peripheral circuit is formed by a stacked film of said first and second polycrystalline silicon films. Forming an element isolation insulating film on the semiconductor substrate;
Forming, on the semiconductor substrate, a gate portion having a charge storage layer of a NAND cell unit in which adjacent memory cells share a source and a drain diffusion layer and a gate electrode of a peripheral circuit;
Depositing a first insulating film so as to cover a cell array region where the NAND cell units are arranged and a peripheral circuit region;
Removing a portion of the first insulating film that covers a region of the peripheral circuit;
Depositing a second insulating film so as to cover the area of the cell array and the peripheral circuit and to bury the space between the gate portions of the NAND cell unit;
Forming source and drain diffusion layers of the peripheral circuit;
A method for manufacturing a semiconductor memory device, comprising: The gate portion of the NAND cell unit and the gate electrode of the peripheral circuit are patterned while being covered with a third insulating film,
Removing the first and second insulating films of the wiring contact portion of the NAND cell unit after depositing the second insulating film, and depositing a fourth insulating film covering the cell array and a peripheral circuit region And a step of
7. The method according to claim 6, wherein the step of forming the source and drain diffusion layers of the peripheral circuit is performed by ion implantation after depositing the second insulating film or after depositing the fourth insulating film. Manufacturing method of a semiconductor memory device of the present invention. A step of removing the fourth insulating film while leaving the side surface of the gate contact covered with the second insulating film in a side surface of the wiring contact portion and a region of the peripheral circuit. 8. The method for manufacturing a semiconductor memory device according to item 7. The gate portion of the NAND cell unit and the gate electrode of the peripheral circuit are patterned while being covered with a third insulating film,
Etching the first and second insulating films until the third insulating film is exposed after depositing the second insulating film; and forming first and second wiring contact portions of the NAND cell unit. Removing the second insulating film, and depositing a fourth insulating film covering the cell array and the peripheral circuit region,
7. The method according to claim 6, wherein the step of forming the source and drain diffusion layers of the peripheral circuit is performed by ion implantation after depositing the second insulating film or after depositing the fourth insulating film. Manufacturing method of a semiconductor memory device of the present invention. 10. The semiconductor device according to claim 7, wherein the first and second insulating films are silicon oxide films, and the third and fourth insulating films are silicon nitride films. Production method. The gate portion of the NAND cell unit includes a floating gate as a charge storage layer made of a first-layer polycrystalline silicon film, and a second-layer polycrystalline silicon film laminated on the floating gate with an inter-gate insulating film interposed therebetween. A gate electrode of the peripheral circuit is formed by a laminated film of the first and second polycrystalline silicon films,
Forming the element isolation insulating film, after depositing the first layer polycrystalline silicon film, etching the first layer polycrystalline silicon film to a predetermined depth of the semiconductor substrate to form an element isolation groove; Embedding an element isolation insulating film in the formed element isolation groove,
The step of forming a gate portion of the NAND cell unit and a gate electrode of a peripheral circuit includes forming an inter-gate insulating film on the floating gate, depositing the second-layer polycrystalline silicon film, 7. The semiconductor memory device according to claim 6, wherein the second polycrystalline silicon film is etched to form a stacked structure of a floating gate and a control gate of the memory cell and a gate electrode of the peripheral circuit. Manufacturing method.

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