JP4284311B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor memory equipment, a method for manufacturing a semiconductor memory equipment of the electrode such as the charge storage layer and the gate electrode are formed in self-alignment with the particular element isolation region by a trench structure.

  In recent years, semiconductor memory devices have been highly integrated, and research on fine semiconductor memory devices has been actively conducted. For example, a nonvolatile memory element is expected as an alternative to a hard disk device among various semiconductor memory devices, and further higher integration is desired.

  This non-volatile memory element has a special structure using a floating gate that is not found in other semiconductor memory devices, and the technology for finely forming the floating gate is an important element in element miniaturization. One.

  The floating gate is formed by separating the deposited film. When a nonvolatile memory element is formed on a silicon semiconductor substrate, a photolithography method is used for the floating gate separation. However, it is extremely difficult to separate floating gates with a width (slit) of 0.4 μm or less even with the latest technology using the photographic contact method.

  Further, when using the photo-engraving method, misalignment occurs, and therefore, in a high-density element of 64M or later, there is a risk of performing floating gate isolation on the element. In this case, since the control gate is directly formed on the tunnel oxide film, the dielectric breakdown of the tunnel oxide film occurs during the operation of the element, which has a fatal effect on the element operation. In order to avoid this, the element formation region must be enlarged.

Therefore, a technique for separating the floating gate in a self-aligned manner has been developed (see, for example, Patent Documents 1 and 2). However, further improvements are desired.
JP-A-3-220778 JP-A-4-208572

The present invention is intended to provide a method of manufacturing a semiconductor memory equipment equipped without giving variations in device operating characteristics, the finely separated electrodes.

A method of manufacturing a semiconductor memory device according to the present invention includes a first step of sequentially forming a thermal oxide film and a mask layer made of a predetermined material on the surface of a semiconductor substrate, the thermal oxide film other than the element formation region, and the A second step of removing the mask layer; a third step of forming a groove by etching the surface of the semiconductor substrate exposed in the second step using the mask layer remaining on the element formation region as a mask; A fourth step of depositing an insulating film from the bottom of the groove to the upper end surface of the mask layer; and removing the mask layer so as to leave a portion of the insulating film protruding from the groove, the insulating layer on the element formation region A fifth step of forming an opening of the film, a sixth step of peeling off the thermal oxide film formed on the surface of the semiconductor substrate, and removing a desired amount of the insulating film protruding from the groove Open the outside of both ends of the element formation area Ninth step of forming a seventh step of spreading in a self-aligned manner with respect to the device formation region, an eighth step of forming a gate insulating film on a semiconductor substrate surface, a conductive film for charge storage layer formed When, a tenth step of planarizing the removed the conductive film surface to the conductive film is an upper end surface of the insulating film is exposed, the insulating film on the conductive film and the insulating film formed And an twelfth step of forming a conductive film for forming a control gate on the interelectrode insulating film.

According to the present invention, without giving a variation in device operation characteristics, it can provide a method of manufacturing the semiconductor memory equipment having a finely separated electrodes.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan view of a NAND type EEPROM according to a reference example of the present invention. 2 and FIG. 3 show an AA ′ sectional view and a BB ′ sectional view of the NAND type EEPROM of FIG. 1, respectively.

  As shown in FIGS. 1 and 2, in this NAND type EEPROM, a plurality of control gates 9 and a plurality of active layers 30 are arranged in an orthogonal arrangement, and a floating oxide film 22 and an ONO film 8 are interposed at the intersection of the two. Gates 7 are provided in a sandwiched manner, and each intersection forms a storage node.

  In this reference example, as shown in FIGS. 1 and 3, the element isolation region 31 is formed by embedding the groove 12 provided on the surface of the semiconductor substrate 1 with two kinds of insulating films 5 and 6 up to the upper end surface. The floating gate electrode 7 is formed in a self-aligned manner between the adjacent element isolation regions 31. In this reference example, the floating gate electrode 7 has a wing structure in which the first insulating film 5 in the element isolation region 31 is overlapped.

  In this reference example, the floating gate electrode is formed in a self-aligned manner between adjacent element isolation regions, so that it is possible to obtain a floating gate electrode that is extremely finely separated and formed, and at the same time, a photographic contact that has been a problem in the past. It is possible to completely eliminate fluctuations in operating characteristics without causing fluctuations in the element shape due to misalignment of time.

  In this reference example, since the floating gate electrode has a wing structure, a large capacitance can be provided between the control gate electrode and the floating gate electrode. In this reference example, as shown in FIG. 3, a capacitance is also formed between the side wall of the floating gate electrode and the control gate electrode formed between the side walls of the floating gate electrode, so that the capacitance can be further increased. it can.

  A manufacturing process for obtaining an EEPROM having the structure as shown in FIG. 3 will be described below.

  First, for example, a P-type well is formed on an N-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 5 to 50 Ω · cm. For example, a thermal oxide film 2 having a thickness of 25 nm is formed in an HCl atmosphere. Further, polycrystalline silicon is formed to a thickness of about 400 nm to form the first mask layer 3, and a silicon oxide film is formed to a thickness of about 500 nm by the CVD method to form the second mask layer 4.

  Thereafter, it is selectively covered with a resist film (not shown) by photolithography, and this is used as a mask, the CVD silicon oxide film 4 is etched, and then the resist is peeled off. Then, using this CVD silicon oxide film 4 as a mask, the polycrystalline silicon film 3 which is the first mask layer exposed by the previous process is etched, and the thermal oxide film 2 below is further etched.

Next, using the remaining CVD silicon oxide film 4 and polycrystalline silicon film 3 as a mask, the exposed surface of the silicon substrate 1 is etched, for example, in an HBr / SiF ₄ / O ₂ atmosphere, and the depth is about 0.5 μm. A groove 12 having a width of about 0.4 μm is formed.

Then, after performing the field I / I, as the first element isolation insulating film 5 for burying the trench, a silicon oxide film formed by, for example, a CVD method is formed to a thickness of 100 nm. In order to improve the film quality, this silicon oxide film 5 is preferably baked and hardened at about 1000 ° C. in an N ₂ atmosphere, for example.

FIG. 4 is a schematic cross-sectional view of the semiconductor device at the time when the above steps are completed. 4 to 11 described later, the p ⁺ type layer 20 is omitted.

  Next, a silicon nitride film 6 is formed to a thickness of about 200 nm, and the groove 12 is completely buried as shown in FIG. At this time, it is desirable to bury the silicon nitride film 6 so as not to generate voids.

  Further, the silicon nitride film 6 is etched back by a CDE (Chemical Dry Etching) method or the like, and a portion sandwiched between the polycrystalline silicon layers 3 as the first mask layer and the grooves 12 formed on the surface of the silicon substrate 1 are formed. Only the film-formed part is left inside (FIG. 6).

  Thereafter, the first insulating film 5 which is a silicon oxide film formed by the CVD method and the second mask layer 4 which is a silicon oxide film similarly formed are selectively etched by, for example, the RIE method, so that the first The polycrystalline silicon layer 3 as one mask layer and the silicon nitride film 6 as the second insulating film are not etched, and are the first insulating film up to the upper end portion of the polycrystalline silicon layer 3 as the first mask layer. It is embedded with the CVD silicon oxide film 5 and the silicon nitride film 6 as the second insulating film (FIG. 7).

  Thereafter, the polycrystalline silicon layer 3 which is the first mask layer is removed by, for example, the CDE method, and further etched by a solution such as ammonium fluoride, for example, to thereby form the thermal oxide film 2 formed on the silicon substrate 1. The portions other than the portion embedded in the trench 12 formed in the silicon substrate 1 are removed from the CVD silicon oxide film 5 as the first insulating film. Thereafter, a gate oxide film 22 is formed (FIG. 8).

  Next, a polycrystalline silicon film 7 doped with phosphorus is formed (FIG. 9), and the surface is planarized by, for example, a CMP (Chemical Mechanical Polishing) method (FIG. 10). Thereby, at the same time as forming the floating gate electrode 7, it is possible to perform the separation between the floating gate electrodes 7 in a self-aligned manner by the silicon nitride film 6 as the second insulating film.

  Thereafter, the silicon nitride film 6 on the sidewall of the floating gate is etched by, for example, the CDE method (FIG. 11), the ONO film 8 is formed, the control gate electrode 9 is formed, the CVD insulating film 10 is deposited, The element formation is completed (FIG. 3).

  According to the reference example described above, the trench and the first mask layer formed on the semiconductor substrate are filled with the first insulating film and the second insulating film, and then the first insulating film and the first mask layer are formed. Since the electrode is formed at a place where the electrode is removed (between adjacent second insulating films), the electrode can be formed in a self-aligned manner between the adjacent element isolation regions. As a result, it is possible to obtain electrodes that are separated and formed extremely finely, and it is possible to completely eliminate variations in element shape and operating characteristics due to misalignment during photo-engraving.

  Further, the slit width between the electrodes can be formed with extremely good controllability by controlling the film thicknesses of the first insulating film and the second insulating film.

  In addition, the number of photo-engraving steps can be reduced.

<Modification 1>
Here, in the above manufacturing method, after performing the steps up to FIG. 5 in the same manner as in the above reference example, the silicon oxide film 4 as the second mask layer, the CVD silicon oxide film 5 as the first insulating film, and the second insulating film. Etching is performed so that the upper end portion of the polycrystalline silicon layer 3 as the first mask layer is finished under the condition that the silicon nitride film 6 as the film has the same etching rate, and then the step shown in FIG. 6 is omitted. However, it is possible to proceed with the following steps of FIG.

  In this case, in addition to the advantages of the reference example described above, there is an advantage that the process can be simplified.

<Modification 2>
Here, in the manufacturing method according to the reference example, the field I / I was performed before the first insulating film 5 was formed as shown in FIG. 4, but instead, the first insulating film 5 was formed first. After the light etching is performed so that the bottom of the trench 12 is exposed, field I / I is performed (FIG. 12), and the second insulating film 6 may be formed (FIG. 13).

Thus, it is possible to provide small area of the p ⁺ -type layer 21 as compared to the reference example, junction between the n ⁺ -type layer 19 shown in the p ⁺ -type layer 21 and Figure 1 Breakdown can be made difficult to occur. Of course, the advantages of the above-described reference example can be obtained at the same time.

<Modification 3>
The ONO film 8 may be formed on the structure of FIG. 10 without etching the silicon nitride film 6 between the floating gate electrodes 7 (floating gate sidewalls) (FIG. 14).

  In this way, the process can be further simplified.

(Example)
FIG. 22 is a sectional view of a NAND type EEPROM according to the embodiment of the present invention. In this example, the process is further simplified as compared with the reference example.

  As shown in FIG. 22, in this embodiment, the element isolation region is formed by embedding the groove 12 provided on the surface of the semiconductor substrate 1 with the insulating film 16, and the gate electrode 7 is self-aligned between adjacent element isolation regions. Is formed. In this embodiment, the gate electrode 7 has a non-wing structure in which it does not overlap the first insulating film 5 in the element isolation region 31.

  In this embodiment, since the floating gate electrode is formed in a self-aligned manner between the adjacent element isolation regions, it is possible to obtain a floating gate electrode that is extremely finely separated and formed, and at the same time, a photographic contact that has been a problem in the past. It is possible to completely eliminate fluctuations in operating characteristics without causing fluctuations in the element shape due to misalignment of time.

  Hereinafter, a manufacturing process for obtaining an EEPROM having the structure as shown in FIG. 22 will be described.

  First, for example, a thermal oxide film 2 having a thickness of, for example, 25 nm is formed in a HCl atmosphere on a P-type silicon substrate 1 having, for example, a plane orientation (100) and a specific resistance of 5 to 50 Ω · cm, and further a silicon nitride film 14 is formed to a thickness of about 400 nm. A mask layer is formed.

  Thereafter, it is selectively covered with a resist film 40 by photolithography (FIG. 15).

  Using this as a mask, the silicon nitride film 14 and the underlying thermal oxide film 2 are sequentially etched (FIG. 16). Thereafter, the resist 40 is peeled off.

Next, using the remaining silicon nitride film 14 as a mask, the exposed surface of the silicon substrate 1 is etched in, for example, an HBr / SiF ₄ / O ₂ atmosphere to form a groove 12 having a depth of about 0.5 μm and a width of about 0.4 μm. Form. Then, field I / I is performed (FIG. 17).

  Next, as the element isolation insulating film 16 for burying the trench, for example, a silicon oxide film formed by the CVD method is formed to a thickness of about 1000 nm and completely buried from the bottom surface of the groove 12 to above the mask layer 14 made of a silicon nitride film.

  Further, of the CVD silicon oxide film 16 formed by the CVD method, only a portion sandwiched between the silicon nitride films 14 which are mask layers and a portion formed in the groove 12 formed by the silicon substrate 1 are left. As shown in FIG. 18, CVD etch back is performed.

  Thereafter, the silicon nitride film 14 as a mask layer is removed by, for example, the CDE method (FIG. 19).

  Further, the thermal oxide film 2 formed on the silicon substrate 1 is removed by etching with a solution such as ammonium fluoride. Then, dummy oxidation, channel I / I, and dummy oxidation peeling are sequentially performed (FIG. 20).

  Then, after forming the tunnel oxide film 22, a polycrystalline silicon film 7 doped with phosphorus is formed, and the surface is planarized by, for example, a CMP (Chemical Mechanical Polishing) method (FIG. 21).

  As a result, the floating gate electrodes 7 can be formed, and at the same time, the separation between the floating gate electrodes 7 can be performed in a self-aligned manner by the CVD silicon oxide film 16 as an insulating film.

  Thereafter, after the ONO film 8 is formed, the control gate electrode 9 is formed, post-oxidation is performed, and the CVD insulating film 14 is deposited to complete the element formation (FIG. 22).

<Modification>
In the structure of FIG. 21, the control gate electrode 9 may be formed after etching the CVD silicon oxide film 16 on the side wall of the floating gate 7 by the CDE method to form the ONO film 8 (FIG. 23). ).

  In this way, the capacitance is formed between the floating gate electrode sidewall and the control gate electrode formed between the floating gate electrode sidewalls, so that the capacitance can be increased. In this case, it is preferable that the mask layer is stacked thick because the side wall of the floating gate electrode to be formed later becomes higher and the capacitance becomes larger.

  In this embodiment, an example in which the present invention is applied to an EEPROM (floating gate) has been described. However, the present invention can also be applied to a gate electrode of a MIS transistor.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention.

The top view of EEPROM which concerns on the reference example of this invention AA 'sectional view of the EEPROM according to the reference example BB 'sectional view of the EEPROM according to the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the modification of the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the modification of the reference example Sectional drawing of EEPROM which concerns on the other modification of the reference example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the Example of this invention Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the Example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the Example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the Example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the Example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the Example Process sectional drawing which shows the manufacturing method of EEPROM which concerns on the Example Sectional drawing of EEPROM which concerns on the same Example Sectional drawing of EEPROM which concerns on the modification of the Example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Thermal oxide film, 3 ... 1st mask layer, 4 ... 2nd mask layer, 5 ... 1st element isolation insulating film, 6 ... 2nd element isolation insulating film, 7 ... Floating gate 8 ... ONO film, 9 ... control gate, 10 ... CVD insulating film, 12 ... groove, 13 ... oxide film, 14 ... CVD insulating film, 16 ... element isolation insulating film, 19 ... n ⁺ type layer, 20, 21 , 23 ... p ⁺ -type layer, 22 ... tunnel oxide film, 30 ... element isolation region, 31 ... element formation region, 32 ... contact hole, 40 ... resist film.

Claims (3)

A first step of sequentially forming a thermal oxide film and a mask layer made of a predetermined material on the surface of the semiconductor substrate;
A second step of removing the thermal oxide film and the mask layer other than the element formation region;
A third step of forming a groove by etching the surface of the semiconductor substrate exposed in the second step using the mask layer remaining on the element formation region as a mask;
A fourth step of depositing an insulating film from the bottom of the groove to the upper end surface of the mask layer;
A fifth step of removing the mask layer so as to leave a portion of the insulating film protruding from the trench and forming an opening of the insulating film on the element formation region;
A sixth step of peeling the thermal oxide film formed on the surface of the semiconductor substrate;
A seventh step of removing a desired amount of the insulating film protruding from the groove and expanding the opening in a self-aligned manner with respect to the element formation region outside both ends of the element formation region;
An eighth step of forming a gate insulating film on the surface of the semiconductor substrate;
A ninth step of forming a conductive film for forming the charge storage layer;
A tenth step of removing the conductive film until an upper end surface of the insulating film is exposed and planarizing the surface of the conductive film;
An eleventh step of forming an interelectrode insulating film on the conductive film and the insulating film;
A twelfth step of forming a conductive film for forming a control gate on the interelectrode insulating film;
A method of manufacturing a semiconductor memory device. Etching back the insulating film between the conductive films to expose at least a part of the side wall of the conductive film between the tenth step and the eleventh step. A method of manufacturing a semiconductor memory device according to claim 1. 2. The method according to claim 1, further comprising a step of separating the thermal oxide film after forming a thermal oxide film on the surface of the semiconductor substrate between the seventh step and the eighth step. Manufacturing method of semiconductor memory device.

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