CN111326516A - Non-volatile memory structure and manufacturing method thereof - Google Patents
Non-volatile memory structure and manufacturing method thereof Download PDFInfo
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- CN111326516A CN111326516A CN201811632865.4A CN201811632865A CN111326516A CN 111326516 A CN111326516 A CN 111326516A CN 201811632865 A CN201811632865 A CN 201811632865A CN 111326516 A CN111326516 A CN 111326516A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000003860 storage Methods 0.000 claims abstract description 148
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
Abstract
The invention discloses a non-volatile memory structure and a manufacturing method thereof, wherein the non-volatile memory structure comprises a substrate, a selection grid, a first charge storage layer, a control grid and a first dielectric layer. A trench extending along a first direction is provided in the substrate. The select gate is disposed in the trench. The first charge storage layer is disposed on a sidewall of the trench. The first charge storage layer has a first side and a second side opposite to each other. The first side and the second side are arranged in a first direction. The control gate is disposed on the select gate and the first charge storage layer in the trench. The control grid covers the first side and the second side. A first dielectric layer is disposed between the control gate and the first charge storage layer.
Description
Technical Field
The present invention relates to a memory structure and a method for fabricating the same, and more particularly, to a non-volatile memory structure and a method for fabricating the same.
Background
Non-volatile memory (non-volatile memory) is widely used in personal computers and electronic devices because it can perform many operations such as data storage, data reading, and data erasing, and has the advantages of no loss of stored data when power supply is interrupted, short data access time, and low power consumption. However, how to further enhance the electrical performance (electrical performance) of the memory device is a goal of continuous efforts in the industry.
Disclosure of Invention
The invention provides a non-volatile memory structure and a manufacturing method thereof, which can effectively improve the electrical performance of a memory element.
The invention provides a non-volatile memory structure, which comprises a substrate, a selection grid, a first charge storage layer, a control grid and a first dielectric layer. A trench extending along a first direction is provided in the substrate. The select gate is disposed in the trench. The first charge storage layer is disposed on a sidewall of the trench. The first charge storage layer has a first side and a second side opposite to each other. The first side and the second side are arranged in a first direction. The control gate is disposed on the select gate and the first charge storage layer in the trench. The control grid covers the first side and the second side. A first dielectric layer is disposed between the control gate and the first charge storage layer.
According to an embodiment of the present invention, in the nonvolatile memory structure, the select gate, the first charge storage layer, the control gate and the substrate may be electrically insulated from each other.
According to an embodiment of the present invention, in the nonvolatile memory structure, the first charge storage layer is, for example, a floating gate.
According to an embodiment of the invention, in the nonvolatile memory structure, the first charge storage layer may further have a third side surface connected between the first side surface and the second side surface. The control gate may cover the third side.
According to an embodiment of the invention, the nonvolatile memory structure may further include a second charge storage layer. The second charge storage layer is disposed on the other sidewall of the trench. The second charge storage layer may have a fourth side and a fifth side opposite to each other. The fourth side and the fifth side may be arranged in the first direction. The control gate may cover the fourth side and the fifth side. The first dielectric layer is disposed between the control gate and the second charge storage layer.
According to an embodiment of the present invention, in the nonvolatile memory structure, the first charge storage layer and the second charge storage layer may be arranged in a second direction. The second direction may intersect the first direction.
According to an embodiment of the invention, in the nonvolatile memory structure, the second charge storage layer may further have a sixth side connected between the fourth side and the fifth side. The control gate may cover the sixth side.
According to an embodiment of the present invention, the nonvolatile memory structure may further include a first doped region and a second doped region. The first doped region is located in the substrate below the trench. The second doped region is located in the substrate at one side of the trench.
According to an embodiment of the invention, the nonvolatile memory structure may further include a third doped region. The third doped region is located in the substrate on the other side of the trench.
According to an embodiment of the present invention, the nonvolatile memory structure may further include a second dielectric layer and a third dielectric layer. The second dielectric layer is arranged between the selection grid and the substrate. The third dielectric layer is disposed between the first charge storage layer and the substrate.
The invention provides a manufacturing method of a non-volatile memory structure, which comprises the following steps. A trench extending along a first direction is formed in a substrate. Select gates are formed in the trenches. A first charge storage layer is formed on a sidewall of the trench. The first charge storage layer has a first side and a second side opposite to each other. The first side and the second side are arranged in a first direction. A control gate is formed over the select gate and the first charge storage layer in the trench. The control grid covers the first side and the second side. A first dielectric layer is formed between the control gate and the first charge storage layer.
According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory structure, the select gate, the first charge storage layer, the control gate and the substrate may be electrically insulated from each other.
According to an embodiment of the invention, in the method for manufacturing the non-volatile memory structure, the first charge storage layer may further have a third side surface connected between the first side surface and the second side surface. The control gate may cover the third side.
According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory structure, the method for forming the first charge storage layer and the first dielectric layer may include the following steps. A charge storage material layer is conformally formed in the trench. And carrying out an etching back process on the charge storage material layer to form a charge storage gap wall on the side wall of the groove. And carrying out patterning process on the charge storage gap wall to form a first charge storage layer. After the first charge storage layer is formed, a first dielectric layer covering the first charge storage layer is formed.
According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory structure, a second charge storage layer may be formed on another sidewall of the trench. The second charge storage layer may have a fourth side and a fifth side opposite to each other. The fourth side and the fifth side may be arranged in the first direction. The control gate may cover the fourth side and the fifth side. The first dielectric layer is disposed between the control gate and the second charge storage layer.
According to an embodiment of the present invention, in the method for manufacturing the non-volatile memory structure, the first charge storage layer and the second charge storage layer may be arranged in a second direction. The second direction may intersect the first direction.
According to an embodiment of the invention, in the method for manufacturing the non-volatile memory structure, the second charge storage layer may further have a sixth side surface connected between the fourth side surface and the fifth side surface. The control gate may cover the sixth side.
According to an embodiment of the invention, the method for manufacturing the non-volatile memory structure further includes the following steps. A first doped region is formed in the substrate below the trench. A second doped region is formed in the substrate on one side of the trench.
According to an embodiment of the invention, in the method for manufacturing the non-volatile memory structure, a third doped region may be formed in the substrate on the other side of the trench.
According to an embodiment of the invention, the method for manufacturing the non-volatile memory structure further includes the following steps. A second dielectric layer may be formed between the select gates and the substrate. A third dielectric layer may be formed between the first charge storage layer and the substrate.
In view of the above, in the non-volatile memory structure and the manufacturing method thereof provided by the present invention, the control gate is disposed on the first charge storage layer and covers the first side surface and the second side surface of the first charge storage layer, and the first dielectric layer is disposed between the control gate and the first charge storage layer. Therefore, the control grid and the first charge storage layer can be coupled on the first side surface and the second side surface of the first charge storage layer, and the coupling area of the control grid and the first charge storage layer can be increased. Therefore, the nonvolatile memory structure provided by the invention can have higher coupling ratio (coupling ratio), so that the electrical performance of the memory element can be effectively improved.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1A to FIG. 1J are top views of a manufacturing process of a non-volatile memory structure according to an embodiment of the present invention;
FIGS. 2A to 2J are sectional views taken along line I-I' in FIGS. 1A to 1J, respectively;
fig. 3A to 3J are sectional views taken along line II-II' in fig. 1A to 1J, respectively.
Description of the symbols
10: non-volatile memory structure
100: substrate
102: isolation structure
104: patterned hard mask layer
106: groove
108. 128, 130: doped region
110. 110a, 114, 124: dielectric layer
112: select gate material layer
112 a: selection grid
116: layer of charge storage material
118. 120: charge storage spacer
118a, 120 a: charge storage layer
122: patterned photoresist layer
126: control gate material layer
126 a: control grid
AA: active (active) region
D1: a first direction
D2: second direction
S1-S6: side surface
TS1, TS 2: the top surface
Detailed Description
Fig. 1A to fig. 1J are top views of a manufacturing process of a non-volatile memory structure according to an embodiment of the invention. Fig. 2A to 2J are sectional views taken along line I-I' in fig. 1A to 1J. Fig. 3A to 3J are sectional views taken along line II-II' in fig. 1A to 1J.
Referring to fig. 1A, fig. 2A and fig. 3A, an isolation structure 102 may be formed in a substrate 100, and an active area AA may be defined in the substrate 100 by the isolation structure 102. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The material of the isolation structure 102 is, for example, silicon oxide. The isolation structure 102 is, for example, a Shallow Trench Isolation (STI) structure, but the invention is not limited thereto. The isolation structure 102 is formed, for example, by performing a shallow trench isolation process. In addition, the active areas AA may be arranged in the first direction D1 and may extend in the second direction D2. The second direction D2 may intersect the first direction D1. In the embodiment, the second direction D2 is perpendicular to the first direction D1 for illustration, but the invention is not limited thereto.
Referring to fig. 1B, fig. 2B and fig. 3B, a patterned hard mask layer 104 is formed on the substrate 100. The material of the patterned hard mask layer 104 is, for example, silicon nitride. The patterned hard mask layer 104 is formed by, for example, a deposition process, a photolithography process, and an etching process.
Next, a portion of the substrate 100 and a portion of the isolation structure 102 may be removed by using the patterned hard mask layer 104 as a mask, so as to form a trench 106 extending along the first direction D1 in the substrate 100. The method for removing a portion of the substrate 100 and a portion of the isolation structure 102 is, for example, a dry etching method.
A doped region 108 may then be formed in the substrate 100 below the trench 106. The doped region 108 may be used as a source line (source line). In the present embodiment, the doped region 108 is an N-type doped region for illustration, but the invention is not limited thereto. In another embodiment, the doped region 108 may also be a P-type doped region. The doped region 108 is formed by ion implantation, for example.
Referring to fig. 1C, fig. 2C and fig. 3C, a dielectric layer 110 may be formed on the surface of the trench 106. The material of the dielectric layer 110 is, for example, silicon oxide. The dielectric layer 110 is formed by, for example, thermal oxidation.
Next, a layer of select gate material 112 may be formed filling the trench 106. The material of the select gate material layer 112 is, for example, a conductive material such as doped polysilicon. The select gate material layer 112 is formed by, for example, chemical vapor deposition.
Referring to fig. 1D, fig. 2D and fig. 3D, an etch-back process may be performed on the select gate material layer 112 to remove the select gate material layer 112 outside the trench 106, so as to form a select gate 112a in the trench 106.
The hard mask layer 104 may then be removed. The hard mask layer 104 is removed by, for example, wet etching. Furthermore, a portion of the dielectric layer 110 not covered by the select gate 112a may be removed, and a dielectric layer 110a may be formed between the select gate 112a and the substrate 100. The dielectric layer 110a may serve as a gate dielectric layer. Thus, the select gate 112a and the substrate 100 may be electrically insulated from each other. The removal of the portion of the dielectric layer 110 is performed by wet etching, for example. In the present embodiment, the hard mask layer 104 is removed first, and then a portion of the dielectric layer 110 is removed, but the invention is not limited thereto. In another embodiment, a portion of the dielectric layer 110 may be removed first, and then the hard mask layer 104 may be removed.
Referring to fig. 1E, 2E and 3E, a dielectric layer 114 may be formed on the surface of the trench 106. In addition, a dielectric layer 114 may be further formed on the top surface of the substrate 100 and the top surface of the select gate 112 a. The dielectric layer 114 may serve as a tunneling dielectric layer. The material of the dielectric layer 114 is, for example, silicon oxide. The dielectric layer 114 is formed by a thermal oxidation method or a chemical vapor deposition method, for example. In the present embodiment, a method for forming the dielectric layer 114 is described by taking a thermal oxidation method as an example.
Next, a charge storage material layer 116 may be conformally formed in the trench 106. The material of the charge storage material layer 116 may be a floating gate material, such as doped polysilicon or undoped polysilicon.
Referring to fig. 1F, fig. 2F and fig. 3F, an etch-back process may be performed on the charge storage material layer 116. Thus, charge storage spacers 118 may be formed on one sidewall of trench 106 and charge storage spacers 120 may be formed on the other sidewall of trench 106.
Referring to fig. 1G, 2G and 3G, a patterned photoresist layer 122 may be formed on the dielectric layer 114 and the charge storage material layer 116. The patterned photoresist layer 122 may have an opening 122a exposing a portion of the charge storage material layer 118 and a portion of the charge storage material layer 120. The patterned photoresist layer 122 is formed, for example, by performing a photolithography process.
Referring to fig. 1H, 2H and 3H, a portion of the charge storage spacers 118 and a portion of the charge storage spacers 120 may be removed by patterning the photoresist layer 122 as a mask. Thus, a patterning process may be performed on charge storage spacers 118 and 120 to form charge storage layer 118a on a sidewall of trench 106 and charge storage layer 120a on another sidewall of trench 106. Charge storage layer 118a and charge storage layer 120a may be arranged in a second direction D2. Charge storage layer 118a and charge storage layer 120a are, for example, floating gates.
The charge storage layer 120a may have a side S4 and a side S5 opposite to each other. The side S4 and the side S5 may be aligned in the first direction D1. In addition, the charge storage layer 120a may also have a top surface TS2 and a side surface S6 connected between the side surface S4 and the side surface S5. A dielectric layer 114 may be disposed between the charge storage layer 120a and the substrate 100 and between the charge storage layer 120a and the select gate 112 a. Thus, the charge storage layer 120a and the substrate 100 may be electrically insulated from each other, and the charge storage layer 120a and the select gate 112a may be electrically insulated from each other.
The patterned photoresist layer 122 may then be removed. The patterned photoresist layer 122 is removed by, for example, a dry stripping method (dry stripping) or a wet stripping method (wet stripping).
Referring to fig. 1I, 2I and 3I, after forming the charge storage layer 118a, a dielectric layer 124 covering the charge storage layer 118a may be formed. The material of the dielectric layer 124 is, for example, silicon oxide, silicon nitride, or a combination thereof. The dielectric layer 124 may be a multi-layer structure or a single-layer structure. For example, the dielectric layer 124 may be a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO). The dielectric layer 124 is formed by, for example, chemical vapor deposition. Dielectric layer 124 may cover top surface TS1, side surface S1, side surface S2, and side surface S3 of charge storage layer 118a, and may cover top surface TS2, side surface S4, side surface S5, and side surface S6 of charge storage layer 120 a.
Next, a layer of control gate material 126 may be formed in the trench 106. The material of the control gate material layer 126 is, for example, a doped polysilicon or other conductive material. The control gate material layer 126 is formed by a chemical vapor deposition method, for example.
Referring to fig. 1J, 2J, and 3J, a portion of the control gate material layer 126 outside the trench 106 may be removed, and a control gate 126a is formed on the select gate 112a, the charge storage layer 118a, and the charge storage layer 120a in the trench 106. A method of removing a portion of the control gate material layer 126 is, for example, Chemical Mechanical Polishing (CMP). The control gate 126a covers the top surface TS1, the side surface S1, the side surface S2 and the side surface S3 of the charge storage layer 118a, and covers the top surface TS2, the side surface S4, the side surface S5 and the side surface S6 of the charge storage layer 120 a. Dielectric layer 124 may be disposed between control gate 126a and charge storage layer 118a, between control gate 126a and charge storage layer 120a, between control gate 126a and select gate 112a, and between control gate 126a and substrate 100. Accordingly, the control gate 126a may be electrically insulated from the charge storage layer 118a, the charge storage layer 120a, the select gate 112a, and the substrate 100 by at least the dielectric layer 124.
Then, a doped region 128 may be formed in the substrate 100 on one side of the trench 106, and a doped region 130 may be formed in the substrate 100 on the other side of the trench 106. The doped regions 128 and 130 may be referred to as a source or a drain, respectively. In the present embodiment, the doped regions 128 and 130 are illustrated as N-type doped regions, but the invention is not limited thereto. In another embodiment, the doped regions 128 and 130 can also be P-type doped regions. The doped regions 128 and 130 are formed by ion implantation, for example.
The nonvolatile memory structure 10 of the present embodiment is described below with reference to fig. 1J, fig. 2J and fig. 3J. In addition, although the formation method of the non-volatile memory structure 10 is described by taking the above method as an example, the invention is not limited thereto.
Referring to fig. 1J, fig. 2J and fig. 3J, the nonvolatile memory structure 10 includes a substrate 100, a select gate 112a, a charge storage layer 118a, a control gate 126a and a dielectric layer 124. The substrate 100 has a groove 106 therein extending along a first direction D1. Select gate 112a is disposed in trench 106. Charge storage layer 118a is disposed on sidewalls of trench 106 and over select gate 112 a. Charge storage layer 118a has side S1 and side S2 opposite each other. The side S1 and the side S2 are aligned in the first direction D1. Charge storage layer 118a may also have a top surface TS1 and a side surface S3 connected between side surface S1 and side surface S2. Charge storage layer 118a is, for example, a floating gate. Control gate 126a is disposed over select gate 112a and charge storage layer 118a in trench 106. The control gate 126a may cover the top surface TS1, the side surface S1, the side surface S2 and the side surface S3 of the charge storage layer 118 a. Dielectric layer 124 is disposed between control gate 126a and charge storage layer 118 a.
In addition, the nonvolatile memory structure 10 may further include at least one of the isolation structure 102, the doped region 108, the dielectric layer 110a, the dielectric layer 114, the charge storage layer 120a, the doped region 128, and the doped region 130. The select gate 112a, the charge storage layer 118a, the charge storage layer 120a, the control gate 126a and the substrate 100 may be electrically insulated from each other by the dielectric layer 110a, the dielectric layer 114 and the dielectric layer 124. The isolation structure 102 is disposed in the substrate 100. A doped region 108 is located in the substrate 100 below the trench 106. The dielectric layer 110a is disposed between the select gate 112a and the substrate 100. Dielectric layer 114 is disposed between charge storage layer 118a and substrate 100, and may be disposed between charge storage layer 120a and substrate 100. The charge storage layer 120a is disposed on the other sidewall of the trench 106. Charge storage layer 118a and charge storage layer 120a may be arranged in a second direction D2. The second direction D2 may intersect the first direction D1. The charge storage layer 120a may have a side S4 and a side S5 opposite to each other. The side S4 and the side S5 may be aligned in the first direction D1. The charge storage layer 120a may also have a top surface TS2 and a side surface S6 connected between the side surface S4 and the side surface S5. The charge storage layer 120a is, for example, a floating gate. The control gate 126a may cover the top surface TS2, the side surface S4, the side surface S5 and the side surface S6 of the charge storage layer 120 a. A dielectric layer 124 may be disposed between the control gate 126a and the charge storage layer 120 a. A doped region 128 is located in the substrate 100 on one side of the trench 106. A doped region 130 is located in the substrate 100 on the other side of the trench 106.
In addition, the materials, arrangement, conductive type, forming method and efficacy of the components of the nonvolatile memory structure 10 are described in detail in the above embodiments, and will not be repeated here.
Based on the above embodiments, in the nonvolatile memory structure 10 and the manufacturing method thereof, the control gate 126a is disposed on the charge storage layer 118a and covers the side S1 and the side S2 of the charge storage layer 118a, and the dielectric layer 124 is disposed between the control gate 126a and the charge storage layer 118 a. Thus, the control gate 126a and the charge storage layer 118a can be further coupled at the side S1 and the side S2 of the charge storage layer 118a, so that the coupling area between the control gate 126a and the charge storage layer 118a can be increased. As a result, the non-volatile memory structure 10 has a higher coupling ratio, and thus the electrical performance of the memory device can be effectively improved.
In some embodiments, the nonvolatile memory structure 10 may further include a charge storage layer 120 a. The control gate 126a is disposed on the charge storage layer 120a and covers the side S4 and the side S5 of the charge storage layer 120a, and the dielectric layer 124 is disposed between the control gate 126a and the charge storage layer 120 a. Thus, the control gate 126a and the charge storage layer 120a can be coupled at the side S4 and the side S5 of the charge storage layer 120a, so as to increase the coupling area between the control gate 126a and the charge storage layer 120 a. As a result, the non-volatile memory structure 10 has a higher coupling ratio, and thus the electrical performance of the memory device can be effectively improved.
In addition, since the non-volatile memory structure 10 has the vertical channel and the buried select gate 112a, short channel effect (short channel effect) and over-erase phenomenon (over-erase) can be prevented, and the cell density can be higher.
In summary, in the non-volatile memory structure and the manufacturing method thereof of the above embodiments, since the control gate and the charge storage layer can have a larger coupling area, the non-volatile memory structure can have a higher coupling ratio, and thus can have a better electrical performance.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (20)
1. A non-volatile memory structure, comprising:
a substrate having a trench therein extending along a first direction;
a select gate disposed in the trench;
a first charge storage layer disposed on a sidewall of the trench and having a first side and a second side opposite to each other, wherein the first side and the second side are arranged in the first direction;
a control gate disposed on the select gate and the first charge storage layer in the trench and covering the first side and the second side; and
a first dielectric layer disposed between the control gate and the first charge storage layer.
2. A non-volatile memory structure as in claim 1, wherein said select gate, said first charge storage layer, said control gate and said substrate are electrically insulated from each other.
3. A non-volatile memory structure as in claim 1, wherein said first charge storage layer comprises a floating gate.
4. A non-volatile memory structure as in claim 1, wherein said first charge storage layer further has a third side connected between said first side and said second side, and said control gate covers said third side.
5. A non-volatile memory structure as in claim 1, further comprising:
a second charge storage layer disposed on the other sidewall of the trench and having a fourth side and a fifth side opposite to each other, wherein the fourth side and the fifth side are arranged in the first direction, the control gate covers the fourth side and the fifth side, and the first dielectric layer is disposed between the control gate and the second charge storage layer.
6. A non-volatile memory structure as in claim 5, wherein said first charge storage layer and said second charge storage layer are aligned in a second direction, and said second direction intersects said first direction.
7. A non-volatile memory structure as in claim 5, wherein the second charge storage layer further has a sixth side connected between the fourth side and the fifth side, and the control gate covers the sixth side.
8. A non-volatile memory structure as in claim 1, further comprising:
a first doped region in the substrate below the trench; and
and the second doping area is positioned in the substrate at one side of the groove.
9. A non-volatile memory structure as in claim 8, further comprising:
and the third doped region is positioned in the substrate on the other side of the groove.
10. A non-volatile memory structure as in claim 1, further comprising:
a second dielectric layer disposed between the select gate and the substrate; and
a third dielectric layer disposed between the first charge storage layer and the substrate.
11. A method for manufacturing a non-volatile memory structure comprises the following steps:
forming a trench extending in a first direction in a substrate;
forming a selection gate in the trench;
forming a first charge storage layer on a sidewall of the trench, wherein the first charge storage layer has a first side and a second side opposite to each other, and the first side and the second side are arranged in the first direction;
forming a control gate on the select gate and the first charge storage layer in the trench, wherein the control gate covers the first side and the second side; and
a first dielectric layer is formed between the control gate and the first charge storage layer.
12. The method according to claim 11, wherein the select gate, the first charge storage layer, the control gate and the substrate are electrically insulated from each other.
13. The method according to claim 11, wherein the first charge storage layer further has a third side surface connected between the first side surface and the second side surface, and the control gate covers the third side surface.
14. The method according to claim 11, wherein the forming of the first charge storage layer and the first dielectric layer comprises:
forming a charge storage material layer conformally in the trench;
carrying out an etch-back manufacturing process on the charge storage material layer to form a charge storage gap wall on the side wall of the groove;
performing a patterning process on the charge storage spacer to form the first charge storage layer; and
after the first charge storage layer is formed, the first dielectric layer covering the first charge storage layer is formed.
15. A method of fabricating a non-volatile memory structure as in claim 11, further comprising:
forming a second charge storage layer on another sidewall of the trench, wherein the second charge storage layer has a fourth side and a fifth side opposite to each other, the fourth side and the fifth side are arranged in the first direction, the control gate covers the fourth side and the fifth side, and the first dielectric layer is disposed between the control gate and the second charge storage layer.
16. The method according to claim 15, wherein the first and second charge storage layers are aligned in a second direction, and the second direction intersects the first direction.
17. The method according to claim 15, wherein the second charge storage layer further has a sixth side connected between the fourth side and the fifth side, and the control gate covers the sixth side.
18. A method of fabricating a non-volatile memory structure as in claim 11, further comprising:
forming a first doped region in the substrate below the trench; and
a second doped region is formed in the substrate on one side of the trench.
19. A method of fabricating a non-volatile memory structure as in claim 18, further comprising:
a third doped region is formed in the substrate on the other side of the trench.
20. A method of fabricating a non-volatile memory structure as in claim 11, further comprising:
forming a second dielectric layer between the select gate and the substrate; and
a third dielectric layer is formed between the first charge storage layer and the substrate.
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| CN1917182A (en) * | 2005-08-19 | 2007-02-21 | 力晶半导体股份有限公司 | Nonvolatile memory unit, manufacturing method, and opertion method |
| CN1979810A (en) * | 2005-12-06 | 2007-06-13 | 力晶半导体股份有限公司 | Non-volatile memory and production method |
| CN101410962A (en) * | 2006-03-30 | 2009-04-15 | 飞思卡尔半导体公司 | Programmable structure including control gate overlying select gate formed in a trench |
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| US8630114B2 (en) * | 2011-01-19 | 2014-01-14 | Macronix International Co., Ltd. | Memory architecture of 3D NOR array |
| US8609492B2 (en) * | 2011-07-27 | 2013-12-17 | Micron Technology, Inc. | Vertical memory cell |
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| CN1917182A (en) * | 2005-08-19 | 2007-02-21 | 力晶半导体股份有限公司 | Nonvolatile memory unit, manufacturing method, and opertion method |
| CN1979810A (en) * | 2005-12-06 | 2007-06-13 | 力晶半导体股份有限公司 | Non-volatile memory and production method |
| CN101410962A (en) * | 2006-03-30 | 2009-04-15 | 飞思卡尔半导体公司 | Programmable structure including control gate overlying select gate formed in a trench |
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