KR20050094295A - Flash memory device and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a flash memory device and a method for manufacturing the same, wherein the gate polysilicon layer of the NMOS transistor included in the flash memory device is formed of polysilicon doped with n-type impurities, and the polysilicon layer for gate of the PMOS transistor is provided. Is formed of polysilicon doped with p-type impurities, and the PMOS transistor also operates in a surface channel manner in which a channel is formed on the surface of a semiconductor substrate by an electric field like an NMOS transistor. Eliminating difficulties in controlling the amount of current, minimizing the impact on subsequent thermal processes, and increasing the degree of integration can further improve process reliability and device electrical characteristics.

Description

Flash memory device and method of manufacturing the same

The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly to a flash memory device and a method of manufacturing the same that can increase the degree of integration.

In order to manufacture flash memory devices, memory cells, NMOS transistors, and PMOS transistors must be formed. In this case, as the gate is formed of the same material regardless of the type of the memory cell or the transistor, different types of channels are formed in the NMOS transistor or the PMOS transistor, thereby increasing the integration degree.

The channel of a transistor can be classified into two types. Specifically, a channel formed by collecting minority carriers on a surface by a voltage applied to a gate (hereinafter referred to as a 'surface channel') and an ion implantation process before forming a gate regardless of the voltage applied to the gate. Channels formed on the surface of the (hereinafter referred to as "filling channel") can be divided.

In general, in the NAND type flash memory device, since the gate is formed of polycrystalline silicon doped with n-type impurities, the channel of the PMOS transistor is formed as a buried channel in consideration of the electrical characteristics of the device such as a turn-on voltage. Thus, since the channel of the PMOS transistor is formed as a buried channel by an ion implantation process, the channel is not formed on the surface of the semiconductor substrate but is formed at a predetermined depth from the surface of the semiconductor substrate. Therefore, it is difficult to control the thickness of the channel, is affected by the subsequent thermal process, and the problem of difficult to control the amount of current occurs.

In order to solve this problem, it is necessary to increase the size of the transistor, and increasing the size of the transistor causes a problem of low integration.

In contrast, in the flash memory device and the method of manufacturing the same, the polysilicon layer for gate of the NMOS transistor included in the flash memory device is formed of polysilicon doped with n-type impurities, and the poly for gate of the PMOS transistor is used. The silicon layer is formed of polysilicon doped with p-type impurities, so that the PMOS transistor also operates in a surface channel manner in which a channel is formed on the surface of the semiconductor substrate by an electric field, like an NMOS transistor, thereby providing a channel of the PMOS transistor. Eliminating difficulties in controlling thickness or current, minimizing the impact on subsequent thermal processes, and increasing the degree of integration can further improve process reliability and device electrical characteristics.

A flash memory device according to an embodiment of the present invention includes a plurality of flash memory cells formed in a memory cell region, NMOS transistors formed in an NMOS transistor region and doped with n-type impurities in a gate, and formed in a PMOS transistor region. PMOS transistors doped with p-type impurities.

A method of manufacturing a flash memory device according to an embodiment of the present invention includes providing a semiconductor substrate having a device isolation layer formed in an isolation region, a tunnel oxide film and a first polysilicon layer formed over an active region, and a first polysilicon. Forming a second polysilicon layer doped with n-type impurity on the entire structure including the layer, and then patterning the second polysilicon layer in the cell region in a direction parallel to the device isolation layer, and forming the second polysilicon layer. Forming a dielectric film over the entire structure, removing the dielectric film and the second polysilicon layer formed in the PMOS transistor region, a third polysilicon layer doped with p-type impurities on the entire structure including the dielectric film; Forming a silicide layer in sequence, and forming a word line in the cell region by n-patterning and n-type in the NMOS transistor region Forming a gate in the second polysilicon layer, the impurity is doped, and the PMOS transistor area, forming a gate to the third polysilicon layer, the p-type impurity doped.

In the above, the first polysilicon layer may be formed of polysilicon that is not doped with impurities.

Before removing the dielectric film in the PMOS transistor region, a fourth polysilicon layer may be further formed to protect the dielectric film. In this case, the fourth polysilicon layer may be formed of polysilicon that is not doped with impurities or doped with p-type impurities.

Prior to forming the silicide layer, the method may further include removing the third polysilicon layer and the dielectric film of the NMOS transistor region such that the silicide layer is in contact with the second polysilicon layer.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a tunnel oxide layer 102a is formed in a cell region of a semiconductor substrate 101 in which a channel is formed in a well (not shown) and a cell region by an ion implantation process, and the cleaning process is completed, and an NMOS transistor region is formed. Gate oxide films 102b are formed in the and PMOS transistor regions, respectively. Subsequently, the first polysilicon layer 103 and the pad nitride film 104 are sequentially formed on the entire structure. In this case, the first polysilicon layer 103 may be formed of polysilicon that is not doped with impurities, and may be formed to a thickness of 20 nm to 60 nm. The pad nitride film 104 may be formed to a thickness of 50 nm to 100 nm.

Thereafter, the pad nitride film 104, the first polysilicon layer 103, the tunnel oxide film 102a, and the gate oxide film 102b of the device isolation region are sequentially etched. As a result, the device isolation region of the semiconductor substrate 101 is exposed.

Subsequently, after forming the trench by etching the device isolation region of the semiconductor substrate 101, the trench is filled with an insulating material to form the device isolation film 105. Hereinafter, a method of forming the device isolation layer 105 will be described in more detail. When the trench is formed in the isolation region of the semiconductor substrate 101, an insulating material layer (not shown) is formed on the entire structure so that the trench is completely filled. In this case, the insulating material layer may be formed of high density plasma (HDP) oxide. Subsequently, the insulating material layer on the pad nitride film 104 is removed by a chemical mechanical polishing process. Meanwhile, before forming the insulating material layer, the etching damage generated during the trench formation may be alleviated, or the interface property between the insulating material layer and the semiconductor substrate 101 may be improved, or the semiconductor substrate 101 at the upper corners of the trench may be sharply formed. In order to alleviate this, a sidewall oxidation process may be performed. In this case, an oxide film (not shown) is formed on the sidewalls and bottom of the trench, which oxide film is included in the device isolation film. As a result, the insulating material layer remains only in the trench of the device isolation region, and the surface of the pad nitride film 104 is exposed.

As such, the device isolation layer 105 is automatically isolated by the first polysilicon layer 103 and the pad nitride layer 104 formed in the active region and is formed only in the device isolation region, which is a self-aligned shallow trench isolation (SA-STI). It is called a process.

Referring to FIG. 1B, the pad nitride film (104 in FIG. 1A) is removed. As a result, the lower first polysilicon layer 103 is exposed. Subsequently, the second polysilicon layer 106 is formed on the entire structure including the first polysilicon layer 103. In this case, the second polysilicon layer 106 is formed of polysilicon doped with n-type impurities. On the other hand, in order to remove the natural oxide film that may be formed on the first polysilicon layer 103, it is preferable to first perform a cleaning process and then to form a second polysilicon layer 106.

Referring to FIG. 1C, after forming the second polysilicon layer 106, the second polysilicon layer 106 of the cell region is patterned in the same direction as the device isolation region through a conventional process. In this case, in order to increase the surface area of the floating gate, the edge of the second polysilicon layer 106 is patterned to overlap the device isolation layer 105.

Subsequently, a dielectric film 107 is formed over the entire structure. In this case, the dielectric film 107 may be formed in an oxide-nitride-oxide (ONO) structure. The third polysilicon layer 108 may be formed as a protective layer on the dielectric layer 107 in order to prevent etching damage from being generated by subsequent exposure and etching processes. This is optional. When the third polysilicon layer 108 is formed, it may be formed of polysilicon doped with impurities or polysilicon doped with p-type impurities, and may be formed with a thickness of 10 nm to 50 nm. Do.

Referring to FIG. 1D, the third polysilicon layer 108, the dielectric film 107, and the second polysilicon layer 106 formed in the PMOS transistor region are sequentially removed. As a result, only the gate oxide layer 102b and the first polysilicon layer 103 not doped with impurities remain in the PMOS transistor region.

Referring to FIG. 1E, the fourth polysilicon layer 109 and the silicide layer 110 are sequentially formed on the entire structure. Subsequently, an etching process using a hard mask (not shown) in which the word line of the cell region, the NMOS transistor, and the gate line of the PMOS transistor are defined as an etching mask and a self-aligning etching process are sequentially performed.

As a result, the control gate 111 including the silicide layer 110 and the fourth polysilicon layer 109 is formed in the cell region in a direction perpendicular to the device isolation layer 105, and the first polysilicon layer 103 is disposed under the control gate 111. And a floating gate 112 formed of a second polysilicon layer 106 and having a stacked structure of a control gate 111, a dielectric layer 107, a floating gate 112, and a tunnel oxide layer 102a. Transistors are formed.

In the NMOS transistor region, the silicide layer 110, the fourth polysilicon layer 109, the third polysilicon layer 108, the dielectric film 107, the second polysilicon layer 106, and the first polysilicon layer 103 and the gate oxide film 102b remain in a stacked structure. At this time, since the dielectric film 107 remains in the NMOS transistor region, the polysilicon layers 109 and 108 over the dielectric film 107 and the polysilicon layers 106 and 103 under the dielectric film 107 are electrically isolated. Thus, a contact (not shown) must be formed in the gate lie of the NMOS transistor region in a subsequent process to electrically connect them. By forming the contact, the gate 113 of the NMOS transistor is formed in a stacked structure of the first polysilicon layer 103 and the second polysilicon layer 106 doped with n-type impurities.

In the PMOS transistor region, the silicide layer 110, the fourth polysilicon layer 109 doped with p-type impurities, the first polysilicon layer 103 and the gate oxide film 102b remain in a stacked structure. The gate 114 of the PMOS transistor is formed in a stacked structure of.

Thus, the gate 113 of the NMOS transistor is formed of the second polysilicon layer 106 doped with n-type impurities, and the gate 114 of the PMOS transistor is doped with the fourth polysilicon layer 109 doped with p-type impurities In addition, the PMOS transistors as well as the NMOS transistors may be manufactured to be operated by surface channels in which minority carriers are collected and formed on the surface of the semiconductor substrate 101 according to the voltage applied to the gate 114.

Meanwhile, since the dielectric film 107 remains in the NMOS transistor region, the NMOS transistors 109 and 108 and the lower polysilicon layers 106 and 103 are electrically connected to each other. A contact (not shown) is formed in the gate line of the transistor region. However, although not shown in the drawing, in FIG. 1E, the fourth polysilicon layer 109, the third polysilicon layer 108, and the dielectric film 107 in the NMOS transistor region are also removed to remove the silicide layer 110 and the second. If the gate 113 is formed in a stacked structure of the polysilicon layer 106, the contact forming process may be omitted. In this case, the gate 113 of the NMOS transistor is formed in a laminated structure of the first polysilicon layer 103, the second polysilicon layer 106, the fourth polysilicon layer 109, and the silicide layer 110. .

As described above, the PMOS transistor also operates in a surface channel manner in which a channel is formed on the surface of the semiconductor substrate by an electric field, like the NMOS transistor, thereby eliminating difficulties in controlling channel thickness and current amount of the PMOS transistor. The impact on subsequent thermal processes can be minimized and integration can be further increased to improve process reliability and device electrical characteristics.

1A to 1E are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

101 semiconductor substrate 102a tunnel oxide film

102b: gate oxide film 103: first polysilicon layer

104: pad nitride film 105: device isolation film

106: second polysilicon layer 107: dielectric film

108: third polysilicon layer 109: fourth polysilicon layer

110: silicide layer 111: control gate

112: floating gate 113: gate of NMOS transistor

114: gate of a PMOS transistor

Claims (6)

A plurality of flash memory cells formed in the memory cell area; NMOS transistors formed in an NMOS transistor region and doped with n-type impurities in a gate thereof; And A flash memory device including PMOS transistors formed in a PMOS transistor region and doped with p-type impurities in a gate thereof. Providing a semiconductor substrate having a device isolation layer formed in the device isolation region, and a tunnel oxide film and a first polysilicon layer formed over the active region; Forming a second polysilicon layer doped with n-type impurities on the entire structure including the first polysilicon layer, and then patterning the second polysilicon layer in a cell region in a direction parallel to the device isolation layer; Forming a dielectric film on the entire structure including the second polysilicon layer; Removing the dielectric film and the second polysilicon layer formed in a PMOS transistor region; Sequentially forming a third polysilicon layer and a silicide layer doped with a p-type impurity on the entire structure including the dielectric film; And Forming a word line in the cell region, forming a gate as the second polysilicon layer doped with n-type impurities in the NMOS transistor region, and p-type impurity doped in the PMOS transistor region Forming a gate with a polysilicon layer. The method of claim 1, And the first polysilicon layer is formed of polysilicon that is not doped with impurities. The method of claim 2, before removing the dielectric film of the PMOS transistor region, And further forming a fourth polysilicon layer for protecting the dielectric film. The method of claim 4, wherein And the fourth polysilicon layer is formed of polysilicon doped with impurities or doped with p-type impurities. The method of claim 2, wherein before forming the silicide layer, Removing the third polysilicon layer and the dielectric film of the NMOS transistor region such that the silicide layer is in contact with the second polysilicon layer.