JP3764177B2

JP3764177B2 - Semiconductor memory device and manufacturing method thereof

Info

Publication number: JP3764177B2
Application number: JP07156394A
Authority: JP
Inventors: 徹丸山; ヘミンク・ゲルトヤン; 浩渡部; 誠一有留
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1994-03-16
Filing date: 1994-03-16
Publication date: 2006-04-05
Anticipated expiration: 2021-04-05
Also published as: JPH07254652A

Description

【０００１】
【産業上の利用分野】
本発明は、半導体記憶装置およびその製造方法に係わり、特にトレンチ構造による素子分離領域に対して電荷蓄積層やゲート電極などの電極を自己整合的に形成した半導体記憶装置およびその製造方法に関する。
【０００２】
【従来の技術】
近年、半導体記憶装置は高集積化の一途を辿っており、微細な半導体記憶装置の研究が盛んである。例えば各種半導体記憶装置のうち不揮発性メモリ素子はハードディスク装置の代替品として期待されており、さらなる高集積化が望まれている。
【０００３】
この不揮発性メモリ素子は、他の半導体記憶装置には見られない浮遊ゲートを用いる特殊な構造を有しており、素子微細化の上で、この浮遊ゲートを微細形成する技術が重要な要素の一つである。
【０００４】
浮遊ゲートは堆積した膜を分離して形成するが、シリコン半導体基板上に不揮発性メモリ素子を形成する場合には、この浮遊ゲート分離に写真触刻法が用いられる。しかしながら、写真触刻法では、最新の技術を用いても０．４μｍ以下の幅（スリット）で浮遊ゲートの分離を行うことは極めて困難である。
【０００５】
さらに、写真触刻法を用いた場合、合わせずれが生じてしまうため、６４Ｍ以降の高密度素子では、素子上で浮遊ゲート分離を行うおそれが生ずる。この場合、トンネル酸化膜上に直接制御ゲートが形成されるため、素子動作時にトンネル酸化膜の絶縁破壊を起こすので、素子動作に致命的な影響を与えてしまう。また、これを回避しようとすると、素子形成領域を大きくせざるを得ない。
【０００６】
【発明が解決しようとする課題】
以上のように、従来の不揮発性メモリ素子において浮遊ゲートを分離・形成する方法では、微細な幅で浮遊ゲートの分離を行うことは極めて困難であった。また、該方法における写真触刻工程時の合わせずれにより、素子形状や素子動作特性の変動を生じる問題があった。
【０００７】
本発明は、上記事情を考慮してなされたもので、素子動作特性に変動を与えることのない、微細に分離された電極を備えた半導体記憶装置を提供することを目的とする。
【０００８】
【課題を解決するための手段】
本発明の半導体記憶装置の態様は、半導体基板表面に設けた溝と、前記溝を絶縁物で埋め込んで形成され、前記溝の側壁部分の第１の部分と溝の残り部分の第２の部分を有する素子分離領域と、前記素子分離領域により互いに分離された素子領域と、前記素子領域上に形成された第１のゲート絶縁膜と、前記第１のゲート絶縁膜上に形成され、一部分が前記素子分離領域の前記第１の部分上にオーバーラップし、前記素子分離領域の前記第２の部分と自己整合的に形成された電荷蓄積層と、前記電荷蓄積層の上面、側面及び前記素子分離領域の前記第２の部分上に形成された第２のゲート絶縁膜と、前記第２のゲート絶縁膜上に形成された制御ゲート電極とを具備し、前記素子分離領域は、互いに選択的にエッチングできる２種類の絶縁物で前記溝を順次埋め込んで形成されていることを特徴とする。
【０００９】
また、好ましくは、前記素子分離領域は、互いに選択的にエッチングできる２種類の絶縁物で前記溝を順次埋め込んで形成すると良い。この場合、前記素子分離領域は、前記溝の側壁部分に形成された第１の絶縁膜と、該溝の残りの部分を埋め込んだ、該第１の絶縁膜とは異なる材料からなる第２の絶縁膜から構成され、前記溝の下部には、前記第１の絶縁膜に対して自己整合的に拡散層が形成されているようにしても良い。
【００１０】
また、前記素子分離領域は、前記溝を１種類の絶縁物で埋め込んで形成しても良い。
【００１１】
また、本発明の半導体記憶装置の態様は、半導体基板表面に設けた溝と、前記溝を絶縁物で埋め込んで形成され、前記溝の側壁部分で溝の上部と一致された第１の部分及び前記溝の残りの部分で前記溝より突出した前記第１の部分とは異なる材料からなる第２の部分を有する素子分離領域と、前記素子分離領域により互いに分離された素子領域と、前記素子領域上に形成された第１のゲート絶縁膜と、前記第１のゲート絶縁膜上に形成され、一部分が前記素子分離領域の前記第１の部分上にオーバーラップして前記第２の部分と自己整合的に形成され、前記素子分離領域の前記第２の部分の上面と一致された全体が平坦な上面を有する電荷蓄積層と、前記電荷蓄積層の上面、及び前記素子分離領域の上面に形成された第２のゲート絶縁膜と、前記第２のゲート絶縁膜上に形成された制御ゲート電極とを具備することを特徴とする。
【００１２】
また、本発明の半導体記憶装置の製造方法の態様は、半導体基板表面に、熱酸化膜、所定の材料からなる第１のマスク層、該第１のマスク層に対して選択的に除去することが可能な他の材料からなる第２のマスク層を順次形成する第１の工程と、素子形成領域以外の前記熱酸化膜、前記第１のマスク層および前記第２のマスク層を除去する第２の工程と、前記素子形成領域上に残った第２のマスク層をマスクとし、前記第２の工程によって露出された半導体基板表面をエッチングして溝を形成する第３の工程と、この溝の内壁に該溝を埋め尽くさない程度に第１の絶縁膜を形成する第４の工程と、前記第１の絶縁膜に対して選択的に除去することが可能な第２の絶縁膜を、前記溝に形成された第１の絶縁膜上から前記第２のマスク層上に形成された第１の絶縁膜の上方まで堆積し、前記溝を前記第２の絶縁膜で埋め込む第５の工程と、前記第１のマスク層の上端部と同じ高さになるまで、前記第２の絶縁膜を除去する第６の工程と、前記第２のマスク層および前記第１の絶縁膜を、前記第１のマスク層の上端部が露出するまで除去する第７の工程と、前記溝から突出した第１の絶縁膜および第２の絶縁膜の部分を残すように、前記第１のマスク層を選択的に除去する第８の工程と、前記第１の絶縁膜を、第２の絶縁膜はエッチングされない条件で、前記溝の上端面まで選択的に除去する第９の工程と、第１の伝導性膜を成膜する第１０の工程と、前記第１の伝導性膜を、前記第２の絶縁膜の上端面が露出するまで除去する第１１の工程と前記第１の伝導性膜の側壁に位置する前記第２の絶縁膜を除去し、前記第１の伝導性膜の側壁を露出させる第１２の工程と、前記第１の伝導性膜の上面、側壁、及び前記第２の絶縁膜の上面に第３の絶縁膜を形成する第１３の工程と、前記第３の絶縁膜の上面に第２の伝導性膜を形成する第１４の工程とを備えたことを特徴とする。
【００１３】
さらに、本発明の半導体記憶装置の製造方法の態様は、半導体基板表面に、熱酸化膜、所定の材料からなる第１のマスク層、該第１のマスク層に対して選択的に除去することが可能な他の材料からなる第２のマスク層を順次形成する第１の工程と、素子形成領域以外の前記熱酸化膜、前記第１のマスク層および前記第２のマスク層を除去する第２の工程と、前記素子形成領域上に残った第２のマスク層をマスクとし、前記第２の工程によって露出された半導体基板表面をエッチングして溝を形成する第３の工程と、この溝の内壁に該溝を埋め尽くさない程度に第１の絶縁膜を形成する第４の工程と、前記第１の絶縁膜に対して選択的に除去することが可能な第２の絶縁膜を、前記溝に形成された第１の絶縁膜上から前記第２のマスク層上に形成された第１の絶縁膜の上方まで堆積し、前記溝を前記第２の絶縁膜で埋め込む第５の工程と、前記第１のマスク層の上端部と同じ高さになるまで、前記第２の絶縁膜を除去する第６の工程と、前記第２のマスク層および前記第１の絶縁膜を、前記第１のマスク層の上端部が露出するまで除去する第７の工程と、前記溝から突出した第１の絶縁膜および第２の絶縁膜の部分を残すように、前記第１のマスク層を選択的に除去する第８の工程と、前記第１の絶縁膜を、第２の絶縁膜はエッチングされない条件で、前記溝の上端面まで選択的に除去する第９の工程と、第１の伝導性膜を成膜する第１０の工程と、前記第１の伝導性膜を、前記第２の絶縁膜の上端面が露出するまで研磨することにより、前記第１の伝導性膜の上面全体が平坦な上面となるように平坦化する第１１の工程と、前記第１の伝導性膜の上面、及び前記第２の絶縁膜の上面に第３の絶縁膜を形成する第１２の工程と、前記第３の絶縁膜の上面に第２の伝導性膜を形成する第１３の工程とを備えたことを特徴とする。
また、本発明の半導体記憶装置の製造方法の態様は、半導体基板表面に、熱酸化膜、所定の材料からなる第１のマスク層、該第１のマスク層に対して選択的に除去することが可能な他の材料からなる第２のマスク層を順次形成する第１の工程と、素子形成領域以外の前記熱酸化膜、前記第１のマスク層および前記第２のマスク層を除去する第２の工程と、前記素子形成領域上に残った第２のマスク層をマスクとし、前記第２の工程によって露出された半導体基板表面をエッチングして溝を形成する第３の工程と、この溝の内壁に該溝を埋め尽くさない程度に第１の絶縁膜を形成する第４の工程と、前記第１の絶縁膜に対して選択的に除去することが可能な第２の絶縁膜を、前記溝に形成された第１の絶縁膜上から前記第２のマスク層上に形成された第１の絶縁膜の上方まで堆積し、前記溝を前記第２の絶縁膜で埋め込む第５の工程と、前記第１のマスク層の上端部と同じ高さになるまで、前記第２の絶縁膜を除去する第６の工程と、前記第２のマスク層および前記第１の絶縁膜を、前記第１のマスク層の上端部が露出するまで除去する第７の工程と、前記溝から突出した第１の絶縁膜および第２の絶縁膜の部分を残すように、前記第１のマスク層を選択的に除去する第８の工程と、前記第１の絶縁膜を、第２の絶縁膜はエッチングされない条件で、前記溝の上端面まで選択的に除去する第９の工程と、第１の伝導性膜を成膜する第１０の工程と、前記第１の伝導性膜を、前記第２の絶縁膜の上端面が露出するまで除去する第１１の工程と前記第１の伝導性膜の側壁に位置する前記第２の絶縁膜を除去し、前記第１の伝導性膜の側壁を露出させる第１２の工程と、前記第１の伝導性膜の上面、側壁、及び前記第２の絶縁膜の上面に第３の絶縁膜を形成する第１３の工程と、前記第３の絶縁膜の上面に第２の伝導性膜を形成する第１４の工程とを備え、前記第６、第７の工程を同時に行なうことを特徴とする。
【００１５】
好ましくは、前記マスク層にはシリコン窒化膜を、前記絶縁膜にはＣＶＤ法により形成されたシリコン酸化膜を、前記伝導性膜には伝導性多結晶シリコン膜をそれぞれ用いても良い。
【００１６】
【作用】
本発明によれば、電極を隣り合う素子分離領域間に自己整合的に形成するので、極めて微細に分離・形成された電極を得ることができるとともに、従来問題であった写真触刻時の合わせずれ等による素子形状の変動を生じることなく動作特性の変動も完全になくすことができる。
【００１７】
本発明によれば、半導体基板上に形成された溝および第１のマスク層を第１の絶縁膜および第２の絶縁膜で埋め込み、その後第１の絶縁膜および第１のマスク層を取り除いた箇所（隣り合う第２の絶縁膜の間）に、電極を形成するので、電極を隣り合う素子分離領域間に自己整合的に形成することができる。
【００１８】
この結果、極めて微細に分離・形成された電極を得ることができるとともに、写真触刻時の合わせずれ等による素子形状および動作特性の変動の回避を完全になくすことができる。
【００１９】
また、電極間のスリット幅は、第１の絶縁膜および第２の絶縁膜の膜厚を制御することで、極めて制御性良く形成できる。
【００２０】
さらに、写真触刻工程数の減少をも図ることができる。
【００２５】
【実施例】
以下、図面を参照しながら本発明の実施例を説明する。
【００２６】
（第１の実施例）
図１に、本発明の第１の実施例に係るＮＡＮＤ型ＥＥＰＲＯＭの平面図を示す。また、図２および図３にはそれぞれ、図１のＮＡＮＤ型ＥＥＰＲＯＭのＡ−Ａ´断面図およびＢ−Ｂ´断面図を示す。
【００２７】
図１および２のように、このＮＡＮＤ型ＥＥＰＲＯＭでは、複数のコントロール・ゲート９と複数の活性層３０が直交配列され、両者が交差する部分にトンネル酸化膜２２とＯＮＯ膜８を介してフローティング・ゲート７が挟まれた形で設けられており、各交差部分が記憶ノードを形成している。
【００２８】
また、本実施例では、図１および図３のように、素子分離領域３１は、半導体基板１の表面に設けた溝１２を上端面まで２種類の絶縁膜５，６で埋め込んで形成するとともに、隣り合う素子分離領域３１間に浮遊ゲート電極７が自己整合的に形成されている。なお、本実施例では、浮遊ゲート電極７が素子分離領域３１の第１の絶縁膜５にオーバーラップしたウイング型の構造になっている。
【００２９】
本実施例では、浮遊ゲート電極を隣り合う素子分離領域間に自己整合的に形成するので、極めて微細に分離・形成された浮遊ゲート電極を得ることができるとともに、従来問題であった写真触刻時の合わせずれ等による素子形状の変動を生じることなく動作特性の変動も完全になくすことができる。
【００３０】
なお、本実施例では、浮遊ゲート電極をウイング型の構造にするので、コントロール・ゲート電極との間の容量を大きく設けることができる。また本実施例では、図３のように浮遊ゲート電極側壁部と浮遊ゲート電極側壁間に形成されたコントロール・ゲート電極との間にも容量が形成されるので、さらなる容量の増加を図ることができる。
【００３１】
以下、図３のような構造を有するＥＥＰＲＯＭを得るための製造工程について説明する。
【００３２】
まず、例えば面方位（１００）、比抵抗５〜５０Ω・ｃｍのＮ型シリコン基板１上に、Ｐ型ウェルを形成し、例えば厚さ２５ｎｍの熱酸化膜２をＨＣｌ雰囲気中で成膜し、さらに多結晶シリコンを４００ｎｍ程度形成して第一マスク層３とし、ＣＶＤ法で酸化シリコン膜を５００ｎｍ程度形成して第二マスク層４とする。
【００３３】
その後、写真触刻法で、選択的にレジスト膜（図示せず）で覆い、これをマスクとして使用し、ＣＶＤ酸化シリコン膜４をエッチングし、その後レジストを剥離する。そして、このＣＶＤ酸化シリコン膜４をマスクにして、先の工程によって露出した第一マスク層である多結晶シリコン膜３をエッチングし、さらに下の熱酸化膜２をエッチングする。
【００３４】
次に、残ったＣＶＤシリコン酸化膜４および多結晶シリコン膜３をマスクにして、露出したシリコン基板１の表面を例えばＨＢｒ／ＳｉＦ₄／Ｏ₂雰囲気中でエッチングし、深さ０．５μｍ程度、幅０．４μｍ程度の溝１２を形成する。
【００３５】
そして、フィールドＩ／Ｉを行った後、トレンチを埋め込む第一の素子分離絶縁膜５として、例えばＣＶＤ法で成膜したシリコン酸化膜を１００ｎｍ成膜する。このシリコン酸化膜５は、膜質を向上させるために、例えばＮ₂雰囲気中において１０００℃前後で焼き固めるのが好ましい。
【００３６】
上記までの工程が完了した時点での半導体装置の概略断面図を図４に示す。なお、後に示す図４〜図１１においては、ｐ⁺型層２０を省略した。
【００３７】
次に、シリコン窒化膜６を２００ｎｍ程度成膜し、図５のように溝１２を完全に埋め込む。この時、シリコン窒化膜６をボイドが発生しない様に埋め込むことが望ましい。
【００３８】
さらに、シリコン窒化膜６をＣＤＥ（ケミカル・ドライ・エッチング）法などによりエッチバックし、第一マスク層である多結晶シリコン層３に挟まれた部分およびシリコン基板１表面に形成された溝１２の中に成膜された部分のみを残すようにする（図６）。
【００３９】
この後、ＣＶＤ法により成膜したシリコン酸化膜である第一絶縁膜５および同様に成膜したシリコン酸化膜である第二マスク層４を例えばＲＩＥ法などにより選択的にエッチングすることにより、第一マスク層である多結晶シリコン層３および第二絶縁膜であるシリコン窒素化膜６はエッチングされないようにし、第一マスク層である多結晶シリコン層３の上端部まで、第一絶縁膜であるＣＶＤシリコン酸化膜５と第二絶縁膜であるシリコン窒化膜６により埋め込まれているようにする（図７）。
【００４０】
この後、例えばＣＤＥ法等により第一マスク層である多結晶シリコン層３を除去し、さらに例えばフッ化アンモニウム等の溶液でエッチングすることにより、シリコン基板１上に形成されている熱酸化膜２および第一絶縁膜であるＣＶＤシリコン酸化膜５のうちシリコン基板１に形成された溝１２に埋め込まれた部分以外は除去する。その後、ゲート酸化膜２２を形成する（図８）。
【００４１】
次に、リンをドープした多結晶シリコン膜７を形成し（図９）、表面を例えばＣＭＰ（ケミカル・メカニカル・ポリッシング）法により平坦化する（図１０）。これにより、浮遊ゲート電極７を形成すると同時に、浮遊ゲート電極７間の分離を、第二絶縁膜のシリコン窒化膜６により自己整合的に行うことが可能である。
【００４２】
この後、例えばＣＤＥ法により浮遊ゲート側壁部のシリコン窒素化膜６をエッチングし（図１１）、ＯＮＯ膜８を形成した後に、制御ゲート電極９を形成し、ＣＶＤ絶縁膜１０を堆積して、素子形成を完了する（図３）。
【００４３】
以上説明した実施例によれば、半導体基板上に形成された溝および第１のマスク層を第１の絶縁膜および第２の絶縁膜で埋め込み、その後第１の絶縁膜および第１のマスク層を取り除いた箇所（隣り合う第２の絶縁膜の間）に、電極を形成するので、電極を隣り合う素子分離領域間に自己整合的に形成することができる。この結果、極めて微細に分離・形成された電極を得ることができるとともに、写真触刻時の合わせずれ等による素子形状および動作特性の変動の回避を完全になくすことができる。
【００４４】
また、電極間のスリット幅は、第１の絶縁膜および第２の絶縁膜の膜厚を制御することで、極めて制御性良く形成できる。
【００４５】
さらに、写真触刻工程数の減少をも図ることができる。
【００４６】
＜変形例１＞
ここで、上記製造方法において、図５までの工程を上記実施例と同様に行った後、第二マスク層であるシリコン酸化膜４、第一絶縁膜であるＣＶＤシリコン酸化膜５と第二絶縁膜であるシリコン窒化膜６が同一のエッチングレートになる条件で、第一マスク層である多結晶シリコン層３の上端部において終了するようにエッチングを行った後、図６に示される工程を省略し、図７の以下の工程を進めることが可能である。
【００４７】
この場合、上述した実施例の利点に加え、プロセスを簡略化することができる利点がある。
【００４８】
＜変形例２＞
ここで、第１の実施例に係る製造方法においては、図４に示すように第一絶縁膜５を形成する前にフィールドＩ／Ｉを行ったが、その代りに先に第一絶縁膜５を形成し、溝１２の底部が露出するように軽くエッチングした後、フィールドＩ／Ｉを行い（図１２）、第二絶縁膜６を形成しても良い（図１３）。
【００４９】
このようにすれば、上記実施例に比較してｐ^＋型層２１の領域を小さく設けることができるので、ｐ^＋型層２１と図１に示すｎ^＋型層１９との間でのジャンクション・ブレークダウンを発生し難くすることができる。もちろん、上述した実施例の利点も同時に得られる。
【００５０】
＜変形例３＞
浮遊ゲート電極７間（浮遊ゲート側壁部）のシリコン窒化膜６をエッチングせずに、図１０の構造の上にＯＮＯ膜８を形成しても良い(図１４)。
【００５１】
このようにすれば、さらに工程を簡略化することができる。
【００５２】
（参考例）
図２２に、本発明の参考例に係るＮＡＮＤ型ＥＥＰＲＯＭの断面図を示す。本参考例は、第１の実施例に比較して工程をさらに簡略化したものである。
【００５３】
図２２のように本参考例において、素子分離領域は、半導体基板１の表面に設けた溝１２を絶縁膜１６で埋め込んで形成するとともに、隣り合う素子分離領域間にゲート電極７が自己整合的に形成されている。なお、本参考例では、ゲート電極７が素子分離領域３１の第１の絶縁膜５にオーバーラップしていない非ウイング型の構造になっている。
【００５４】
本参考例では、浮遊ゲート電極を隣り合う素子分離領域間に自己整合的に形成するので、極めて微細に分離・形成された浮遊ゲート電極を得ることができるとともに、従来問題であった写真触刻時の合わせずれ等による素子形状の変動を生じることなく動作特性の変動も完全になくすことができる。
【００５５】
以下、図２２のような構造を有するＥＥＰＲＯＭを得るための製造工程について説明する。
【００５６】
まず、例えば面方位（１００）、比抵抗５〜５０Ω・ｃｍのＰ型シリコン基板１上に例えば厚さ２５ｎｍの熱酸化膜２をＨＣｌ雰囲気中で成膜し、さらにシリコン窒素化膜１４を４００ｎｍ程度形成してマスク層とする。
【００５７】
その後、写真触刻法で、選択的にレジスト膜４０で覆う（図１５）。
【００５８】
これをマスクとして使用し、シリコン窒化膜１４と下の熱酸化膜２を順次エッチングする（図１６）。その後、レジスト４０を剥離する。
【００５９】
次に、残ったシリコン窒化膜１４をマスクにして、露出したシリコン基板１表面を例えばＨＢｒ／ＳｉＦ₄／Ｏ₂雰囲気中でエッチングし、深さ０．５μｍ程度、幅０．４μｍ程度の溝１２を形成する。そして、フィールドＩ／Ｉを行う（図１７）。
【００６０】
次に、トレンチを埋め込む素子分離絶縁膜１６として、例えばＣＶＤ法で成膜したシリコン酸化膜を１０００ｎｍ程度成膜し、溝１２の底面からシリコン窒化膜からなるマスク層１４の上方まで完全に埋め込む。
【００６１】
さらに、ＣＶＤ法により成膜したＣＶＤシリコン酸化膜１６のうち、マスク層であるシリコン窒化膜１４に挟まれた部分およびシリコン基板１により形成された溝１２の中に成膜された部分のみを残すようにＣＶＤエッチバックを行う（図１８）。
【００６２】
この後、例えばＣＤＥ法等によりマスク層であるシリコン窒素化膜１４を除去する（図１９）。
【００６３】
さらに、フッ化アンモニウム等の溶液でエッチングすることにより、シリコン基板１上に形成されている熱酸化膜２を除去する。そして、ダミー酸化、チャネルＩ／Ｉ、ダミー酸化剥離を順次行う（図２０）。
【００６４】
そして、トンネル酸化膜２２を形成した後、リンをドープした多結晶シリコン膜７を形成し、表面を例えばＣＭＰ（ケミカル・メカニカル・ポリッシング）法により平坦化する（図２１）。
【００６５】
これにより、浮遊ゲート電極７を形成すると同時に、浮遊ゲート電極７間の分離を、絶縁膜であるＣＶＤシリコン酸化膜１６により自己整合的に行うことが可能である。
【００６６】
この後、ＯＮＯ膜８を形成した後に、制御ゲート電極９を形成し、後酸化を行い、ＣＶＤ絶縁膜１４を堆積して素子形成を完了する（図２２）。
【００６７】
＜変形例＞
ここで、図２１の構造において、例えばＣＤＥ法により浮遊ゲート７側壁部のＣＶＤシリコン酸化膜１６をエッチングし、ＯＮＯ膜８を形成した後に、コントロール・ゲート電極９を形成しても良い（図２３）。
【００６８】
このようにすれば、浮遊ゲート電極側壁部と浮遊ゲート電極側壁間に形成されたコントロール・ゲート電極との間に容量が形成されるので、容量の増加を図ることができる。この場合、マスク層を厚く積むと、その後に形成する浮遊ゲート電極側壁がより高くなり、容量がより大きくなるので好ましい。
【００６９】
もちろん、上述した実施例の利点も同時に得られる。
【００７０】
なお、本実施例では、本発明をＥＥＰＲＯＭ（浮遊ゲート）に適用した例について説明したが、ＭＩＳトランジスタのゲート電極にも適用することが可能である。
【００７１】
また、本発明は上述した各実施例に限定されるものではなく、その要旨を逸脱しない範囲で、種々変形して実施することができる。
【００７２】
【発明の効果】
本発明によれば、電極を隣り合う素子分離領域間に自己整合的に形成するので、極めて微細に分離・形成された電極を得ることができるとともに、従来問題であった写真触刻時の合わせずれ等による素子形状の変動を生じることなく動作特性の変動も完全になくすことができる。
【図面の簡単な説明】
【図１】本発明の第１の実施例に係るＥＥＰＲＯＭの平面図
【図２】同実施例に係るＥＥＰＲＯＭのＡ−Ａ´断面図
【図３】同実施例に係るＥＥＰＲＯＭのＢ−Ｂ´断面図
【図４】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図５】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図６】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図７】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図８】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図９】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１０】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１１】同実施例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１２】同実施例の一変形例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１３】同実施例の一変形例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１４】同実施例の他の変形例に係るＥＥＰＲＯＭの断面図
【図１５】本発明の参考例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１６】同参考例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１７】同参考例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１８】同参考例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図１９】同参考例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図２０】同参考例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図２１】同参考例に係るＥＥＰＲＯＭの製造方法を示す工程断面図
【図２２】同参考例に係るＥＥＰＲＯＭの断面図
【図２３】同参考例の一変形例に係るＥＥＰＲＯＭの断面図
【符号の説明】
１…シリコン基板、２…熱酸化膜、３…第一マスク層、４…第二マスク層、５…第１の素子分離絶縁膜、６…第２の素子分離絶縁膜、７…フローティング・ゲート、８…ＯＮＯ膜、９…コントロール・ゲート、１０…ＣＶＤ絶縁膜、１２…溝、１３…酸化膜、１４…ＣＶＤ絶縁膜、１６…素子分離絶縁膜、１９…ｎ⁺型層、２０，２１，２３…ｐ⁺型層、２２…トンネル酸化膜、３０…素子分離領域、３１…素子形成領域、３２…コンタクト・ホール、４０…レジスト膜。 [0001]
[Industrial application fields]
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly to a semiconductor memory device in which electrodes such as a charge storage layer and a gate electrode are formed in a self-aligned manner with respect to an element isolation region having a trench structure.
[0002]
[Prior art]
In recent years, semiconductor memory devices have been highly integrated, and research on fine semiconductor memory devices has been actively conducted. For example, a nonvolatile memory element is expected as an alternative to a hard disk device among various semiconductor memory devices, and further higher integration is desired.
[0003]
This non-volatile memory element has a special structure using a floating gate that is not found in other semiconductor memory devices, and the technology for finely forming the floating gate is an important element in element miniaturization. One.
[0004]
The floating gate is formed by separating the deposited film. When a nonvolatile memory element is formed on a silicon semiconductor substrate, a photolithography method is used for the floating gate separation. However, it is extremely difficult to separate floating gates with a width (slit) of 0.4 μm or less even with the latest technology using the photographic contact method.
[0005]
Further, when using the photo-engraving method, misalignment occurs, and therefore, in a high-density element of 64M or later, there is a risk of performing floating gate isolation on the element. In this case, since the control gate is directly formed on the tunnel oxide film, the dielectric breakdown of the tunnel oxide film occurs during the operation of the element, which has a fatal effect on the element operation. In order to avoid this, the element formation region must be enlarged.
[0006]
[Problems to be solved by the invention]
As described above, in the conventional method of separating and forming the floating gate in the nonvolatile memory element, it is extremely difficult to separate the floating gate with a fine width. In addition, there is a problem in that variations in element shape and element operation characteristics occur due to misalignment during the photolithography process in the method.
[0007]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device including finely separated electrodes that does not change the element operating characteristics.
[0008]
[Means for Solving the Problems]
According to an aspect of the semiconductor memory device of the present invention, a groove provided on the surface of a semiconductor substrate, the groove is filled with an insulator, a first portion of the sidewall portion of the groove, and a second portion of the remaining portion of the groove. An element isolation region having the element isolation region, an element region isolated from the element isolation region, a first gate insulating film formed on the element region, and a portion formed on the first gate insulating film. A charge storage layer overlapping the first portion of the element isolation region and formed in self-alignment with the second portion of the element isolation region; an upper surface, a side surface of the charge storage layer; and the element A second gate insulating film formed on the second portion of the isolation region; and a control gate electrode formed on the second gate insulating film , wherein the element isolation regions are mutually selective Two kinds of insulators that can be etched Characterized in that it is sequentially embedded form Kimizo.
[0009]
Preferably, the element isolation region is formed by sequentially filling the groove with two kinds of insulators that can be selectively etched with each other. In this case, the element isolation region includes a first insulating film formed on a side wall portion of the groove and a second material made of a material different from that of the first insulating film embedded in the remaining portion of the groove. It may be made of an insulating film, and a diffusion layer may be formed below the trench in a self-aligned manner with respect to the first insulating film.
[0010]
The element isolation region may be formed by embedding the groove with one kind of insulator.
[0011]
According to another aspect of the semiconductor memory device of the present invention, a groove provided on a surface of a semiconductor substrate, a first portion formed by embedding the groove with an insulator, and aligned with an upper portion of the groove at a side wall portion of the groove, and An element isolation region having a second portion made of a material different from the first portion protruding from the groove in the remaining portion of the groove, an element region separated from each other by the element isolation region, and the element region A first gate insulating film formed on the first gate insulating film; and a portion of the first gate insulating film overlaps the first portion of the element isolation region to self-adhere to the second portion. alignment manner is formed, formed on the upper surface of the charge storage layer which is entirely having a flat top surface of the upper surface and is matched to the second portion, the upper surface of the charge storage layer, and the isolation region of the isolation region A second gate insulating film formed; Characterized by comprising a serial second control gate electrode formed on the gate insulating film of.
[0012]
In the semiconductor memory device manufacturing method according to the present invention, the thermal oxide film, the first mask layer made of a predetermined material, and the first mask layer are selectively removed from the surface of the semiconductor substrate. A first step of sequentially forming a second mask layer made of another material capable of being removed, and a first step of removing the thermal oxide film, the first mask layer, and the second mask layer other than the element formation region And a third step of forming a groove by etching the surface of the semiconductor substrate exposed by the second step, using the second mask layer remaining on the element formation region as a mask. A fourth step of forming the first insulating film to such an extent that the groove is not filled in the inner wall of the first insulating film, and a second insulating film that can be selectively removed with respect to the first insulating film, Formed on the second mask layer from the first insulating film formed in the trench Deposited to above the first insulating film, a fifth step of filling the groove with the second insulating film, until it is flush with the upper end portion of the first mask layer, said second of a sixth step of removing the insulating film, the second mask layer and said first insulating film, and a seventh step of removing to the upper end portion of the first mask layer is exposed, said groove An eighth step of selectively removing the first mask layer so as to leave portions of the first insulating film and the second insulating film projecting from the first insulating film; and The ninth step of selectively removing the insulating film up to the upper end surface of the groove under the condition that the insulating film is not etched, the tenth step of forming the first conductive film, and the first conductive film, the position on the side wall of the eleventh step and the first conductive film to be removed to the upper end surface of the second insulating film is exposed first Insulating film is removed, and a twelfth step of exposing the sidewalls of the first conductive film, the upper surface of the first conductive film, side walls, and a third on the upper surface of the second insulating film A thirteenth step of forming an insulating film and a fourteenth step of forming a second conductive film on the upper surface of the third insulating film are provided.
[0013]
Furthermore, according to the aspect of the method for manufacturing a semiconductor memory device of the present invention, the thermal oxide film, the first mask layer made of a predetermined material, and the first mask layer are selectively removed from the surface of the semiconductor substrate. A first step of sequentially forming a second mask layer made of another material capable of being removed, and a first step of removing the thermal oxide film, the first mask layer, and the second mask layer other than the element formation region And a third step of forming a groove by etching the surface of the semiconductor substrate exposed by the second step, using the second mask layer remaining on the element formation region as a mask. A fourth step of forming the first insulating film to such an extent that the groove is not filled in the inner wall of the first insulating film, and a second insulating film that can be selectively removed with respect to the first insulating film, Formed on the second mask layer from the first insulating film formed in the trench. Deposited to above the first insulating film, a fifth step of filling the groove with the second insulating film, until it is flush with the upper end portion of the first mask layer, said second of a sixth step of removing the insulating film, the second mask layer and said first insulating film, and a seventh step of removing to the upper end portion of the first mask layer is exposed, said groove An eighth step of selectively removing the first mask layer so as to leave portions of the first insulating film and the second insulating film projecting from the first insulating film; and insulating film under a condition that is not etched, a ninth step of selectively removing to the upper end surface of the groove, a tenth step of forming a film of the first conductive film, the first conductive film, wherein by the upper end surface of the second insulating film is polished to expose the upper surface entirely flat upper surface of the first conductive film A eleventh step of planarizing so, the upper surface of the first conductive film, and a twelfth step of forming a third insulating film on the upper surface of the second insulating film, the third And a thirteenth step of forming a second conductive film on the upper surface of the insulating film.
In the semiconductor memory device manufacturing method according to the present invention , the thermal oxide film, the first mask layer made of a predetermined material, and the first mask layer are selectively removed from the surface of the semiconductor substrate. A first step of sequentially forming a second mask layer made of another material capable of being removed, and a first step of removing the thermal oxide film, the first mask layer, and the second mask layer other than the element formation region And a third step of forming a groove by etching the surface of the semiconductor substrate exposed by the second step, using the second mask layer remaining on the element formation region as a mask. A fourth step of forming the first insulating film to such an extent that the groove is not filled in the inner wall of the first insulating film, and a second insulating film that can be selectively removed with respect to the first insulating film, Formed on the second mask layer from the first insulating film formed in the trench A second step of depositing the upper portion of the first insulating film and filling the groove with the second insulating film until the height of the second step is the same as the upper end of the first mask layer. A sixth step of removing the insulating film; a seventh step of removing the second mask layer and the first insulating film until an upper end portion of the first mask layer is exposed; and the groove An eighth step of selectively removing the first mask layer so as to leave portions of the first insulating film and the second insulating film projecting from the first insulating film; and The ninth step of selectively removing the insulating film up to the upper end surface of the groove under the condition that the insulating film is not etched, the tenth step of forming the first conductive film, and the first conductive film, An eleventh step of removing until the upper end surface of the second insulating film is exposed; and the first step located on a sidewall of the first conductive film. A twelfth step of removing the insulating film and exposing a side wall of the first conductive film; and a third step on the upper surface, the side wall, and the upper surface of the second insulating film of the first conductive film. A thirteenth step of forming an insulating film; and a fourteenth step of forming a second conductive film on the upper surface of the third insulating film, wherein the sixth and seventh steps are performed simultaneously. Features.
[0015]
Preferably, a silicon nitride film may be used for the mask layer, a silicon oxide film formed by a CVD method may be used for the insulating film, and a conductive polycrystalline silicon film may be used for the conductive film.
[0016]
[Action]
By the present invention lever, since the self-aligned manner between the device isolation regions adjacent the electrodes, it is possible to obtain is very finely divided, forming electrodes, problems in a photographic tactile clocking conventional Variations in operating characteristics can be completely eliminated without causing variations in element shape due to misalignment or the like.
[0017]
According to the onset bright, the grooves and the first mask layer formed on the semiconductor substrate embedded in the first insulating film and the second insulating film, removing the subsequent first insulating film and the first mask layer Since the electrodes are formed at the locations (between adjacent second insulating films), the electrodes can be formed in a self-aligned manner between the adjacent element isolation regions.
[0018]
As a result, it is possible to obtain electrodes that are separated and formed extremely finely, and it is possible to completely eliminate variations in element shape and operating characteristics due to misalignment during photo-engraving.
[0019]
Further, the slit width between the electrodes can be formed with extremely good controllability by controlling the film thicknesses of the first insulating film and the second insulating film.
[0020]
In addition, the number of photo-engraving steps can be reduced.
[0025]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
[0026]
(First embodiment)
FIG. 1 is a plan view of a NAND type EEPROM according to the first embodiment of the present invention. 2 and FIG. 3 show an AA ′ sectional view and a BB ′ sectional view of the NAND type EEPROM of FIG. 1, respectively.
[0027]
As shown in FIGS. 1 and 2, in this NAND type EEPROM, a plurality of control gates 9 and a plurality of active layers 30 are arranged in an orthogonal arrangement, and a floating oxide film 22 and an ONO film 8 are interposed at the intersection of the two. Gates 7 are provided in a sandwiched manner, and each intersection forms a storage node.
[0028]
Further, in this embodiment, as shown in FIGS. 1 and 3, the element isolation region 31 is formed by embedding the groove 12 provided on the surface of the semiconductor substrate 1 with two kinds of insulating films 5 and 6 up to the upper end surface. The floating gate electrode 7 is formed in a self-aligned manner between the adjacent element isolation regions 31. In this embodiment, the floating gate electrode 7 has a wing type structure in which the first insulating film 5 in the element isolation region 31 is overlapped.
[0029]
In this embodiment, since the floating gate electrode is formed in a self-aligned manner between the adjacent element isolation regions, it is possible to obtain a floating gate electrode that is extremely finely separated and formed, and at the same time, a photographic contact that has been a problem in the past. It is possible to completely eliminate fluctuations in operating characteristics without causing fluctuations in the element shape due to misalignment of time.
[0030]
In this embodiment, since the floating gate electrode has a wing structure, a large capacitance can be provided between the control gate electrode and the floating gate electrode. Further, in this embodiment, as shown in FIG. 3, a capacitance is also formed between the side wall of the floating gate electrode and the control gate electrode formed between the side walls of the floating gate electrode, so that the capacitance can be further increased. it can.
[0031]
A manufacturing process for obtaining an EEPROM having the structure as shown in FIG. 3 will be described below.
[0032]
First, for example, a P-type well is formed on an N-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 5 to 50 Ω · cm. For example, a thermal oxide film 2 having a thickness of 25 nm is formed in an HCl atmosphere. Further, polycrystalline silicon is formed to a thickness of about 400 nm to form the first mask layer 3, and a silicon oxide film is formed to a thickness of about 500 nm by the CVD method to form the second mask layer 4.
[0033]
Thereafter, it is selectively covered with a resist film (not shown) by photolithography, and this is used as a mask, the CVD silicon oxide film 4 is etched, and then the resist is peeled off. Then, using this CVD silicon oxide film 4 as a mask, the polycrystalline silicon film 3 which is the first mask layer exposed by the previous process is etched, and the thermal oxide film 2 below is further etched.
[0034]
Next, using the remaining CVD silicon oxide film 4 and polycrystalline silicon film 3 as a mask, the exposed surface of the silicon substrate 1 is etched, for example, in an HBr / SiF ₄ / O ₂ atmosphere, and the depth is about 0.5 μm. A groove 12 having a width of about 0.4 μm is formed.
[0035]
Then, after performing the field I / I, as the first element isolation insulating film 5 for burying the trench, a silicon oxide film formed by, for example, a CVD method is formed to a thickness of 100 nm. In order to improve the film quality, this silicon oxide film 5 is preferably baked and hardened at about 1000 ° C. in an N ₂ atmosphere, for example.
[0036]
FIG. 4 is a schematic cross-sectional view of the semiconductor device at the time when the above steps are completed. 4 to 11 described later, the p ⁺ type layer 20 is omitted.
[0037]
Next, a silicon nitride film 6 is formed to a thickness of about 200 nm, and the groove 12 is completely buried as shown in FIG. At this time, it is desirable to bury the silicon nitride film 6 so as not to generate voids.
[0038]
Further, the silicon nitride film 6 is etched back by a CDE (Chemical Dry Etching) method or the like, and a portion sandwiched between the polycrystalline silicon layers 3 as the first mask layer and the grooves 12 formed on the surface of the silicon substrate 1 are formed. Only the film-formed part is left inside (FIG. 6).
[0039]
Thereafter, the first insulating film 5 which is a silicon oxide film formed by the CVD method and the second mask layer 4 which is a silicon oxide film similarly formed are selectively etched by, for example, the RIE method, so that the first The polycrystalline silicon layer 3 as one mask layer and the silicon nitride film 6 as the second insulating film are not etched, and are the first insulating film up to the upper end portion of the polycrystalline silicon layer 3 as the first mask layer. It is embedded with the CVD silicon oxide film 5 and the silicon nitride film 6 as the second insulating film (FIG. 7).
[0040]
Thereafter, the polycrystalline silicon layer 3 which is the first mask layer is removed by, for example, the CDE method, and further etched by a solution such as ammonium fluoride, for example, to thereby form the thermal oxide film 2 formed on the silicon substrate 1. The portions other than the portion embedded in the trench 12 formed in the silicon substrate 1 are removed from the CVD silicon oxide film 5 as the first insulating film. Thereafter, a gate oxide film 22 is formed (FIG. 8).
[0041]
Next, a polycrystalline silicon film 7 doped with phosphorus is formed (FIG. 9), and the surface is planarized by, for example, a CMP (Chemical Mechanical Polishing) method (FIG. 10). Thereby, at the same time as forming the floating gate electrode 7, it is possible to perform the separation between the floating gate electrodes 7 in a self-aligned manner by the silicon nitride film 6 as the second insulating film.
[0042]
Thereafter, the silicon nitride film 6 on the sidewall of the floating gate is etched by, for example, the CDE method (FIG. 11), the ONO film 8 is formed, the control gate electrode 9 is formed, the CVD insulating film 10 is deposited, The element formation is completed (FIG. 3).
[0043]
According to the embodiment described above, the trench and the first mask layer formed on the semiconductor substrate are filled with the first insulating film and the second insulating film, and then the first insulating film and the first mask layer are formed. Since the electrode is formed at a place where the electrode is removed (between adjacent second insulating films), the electrode can be formed in a self-aligned manner between the adjacent element isolation regions. As a result, it is possible to obtain electrodes that are separated and formed extremely finely, and it is possible to completely eliminate variations in element shape and operating characteristics due to misalignment during photo-engraving.
[0044]
Further, the slit width between the electrodes can be formed with extremely good controllability by controlling the film thicknesses of the first insulating film and the second insulating film.
[0045]
In addition, the number of photo-engraving steps can be reduced.
[0046]
<Modification 1>
Here, in the above manufacturing method, after performing the steps up to FIG. 5 in the same manner as in the above embodiment, the silicon oxide film 4 as the second mask layer, the CVD silicon oxide film 5 as the first insulating film, and the second insulating film. Etching is performed so that the upper end portion of the polycrystalline silicon layer 3 as the first mask layer is finished under the condition that the silicon nitride film 6 as the film has the same etching rate, and then the step shown in FIG. 6 is omitted. However, it is possible to proceed with the following steps of FIG.
[0047]
In this case, in addition to the advantages of the above-described embodiments, there is an advantage that the process can be simplified.
[0048]
<Modification 2>
Here, in the manufacturing method according to the first embodiment, the field I / I is performed before the first insulating film 5 is formed as shown in FIG. Then, light etching is performed so that the bottom of the trench 12 is exposed, and then field I / I is performed (FIG. 12) to form the second insulating film 6 (FIG. 13).
[0049]
Thus, it is possible to provide small area of the p ⁺ -type layer 21 as compared to the above embodiment, junction between the n ⁺ -type layer 19 shown in the p ⁺ -type layer 21 and Figure 1 Breakdown can be made difficult to occur. Of course, the advantages of the above-described embodiment can be obtained at the same time.
[0050]
<Modification 3>
The ONO film 8 may be formed on the structure of FIG. 10 without etching the silicon nitride film 6 between the floating gate electrodes 7 (floating gate sidewalls) (FIG. 14).
[0051]
In this way, the process can be further simplified.
[0052]
(Reference example)
FIG. 22 is a sectional view of a NAND type EEPROM according to a reference example of the present invention. In this reference example , the process is further simplified as compared with the first embodiment.
[0053]
As shown in FIG. 22, in this reference example, the element isolation region is formed by embedding the groove 12 provided on the surface of the semiconductor substrate 1 with the insulating film 16, and the gate electrode 7 is self-aligned between adjacent element isolation regions. Is formed. In this reference example, the gate electrode 7 has a non-wing structure in which it does not overlap the first insulating film 5 in the element isolation region 31.
[0054]
In this reference example, the floating gate electrode is formed in a self-aligned manner between adjacent element isolation regions, so that it is possible to obtain a floating gate electrode that is extremely finely separated and formed, and at the same time, a photographic contact that has been a problem in the past. It is possible to completely eliminate fluctuations in operating characteristics without causing fluctuations in the element shape due to misalignment of time.
[0055]
Hereinafter, a manufacturing process for obtaining an EEPROM having the structure as shown in FIG. 22 will be described.
[0056]
First, for example, a thermal oxide film 2 having a thickness of, for example, 25 nm is formed in a HCl atmosphere on a P-type silicon substrate 1 having, for example, a plane orientation (100) and a specific resistance of 5 to 50 Ω · cm, and further a silicon nitride film 14 having a thickness of 400 nm. A mask layer is formed to some extent.
[0057]
Thereafter, it is selectively covered with a resist film 40 by photolithography (FIG. 15).
[0058]
Using this as a mask, the silicon nitride film 14 and the underlying thermal oxide film 2 are sequentially etched (FIG. 16). Thereafter, the resist 40 is peeled off.
[0059]
Next, using the remaining silicon nitride film 14 as a mask, the exposed surface of the silicon substrate 1 is etched in, for example, an HBr / SiF ₄ / O ₂ atmosphere to form a groove 12 having a depth of about 0.5 μm and a width of about 0.4 μm. Form. Then, field I / I is performed (FIG. 17).
[0060]
Next, as the element isolation insulating film 16 for burying the trench, for example, a silicon oxide film formed by the CVD method is formed to a thickness of about 1000 nm and completely buried from the bottom surface of the groove 12 to above the mask layer 14 made of a silicon nitride film.
[0061]
Further, of the CVD silicon oxide film 16 formed by the CVD method, only a portion sandwiched between the silicon nitride films 14 which are mask layers and a portion formed in the groove 12 formed by the silicon substrate 1 are left. As shown in FIG. 18, CVD etch back is performed.
[0062]
Thereafter, the silicon nitride film 14 as a mask layer is removed by, for example, the CDE method (FIG. 19).
[0063]
Further, the thermal oxide film 2 formed on the silicon substrate 1 is removed by etching with a solution such as ammonium fluoride. Then, dummy oxidation, channel I / I, and dummy oxidation peeling are sequentially performed (FIG. 20).
[0064]
Then, after forming the tunnel oxide film 22, a polycrystalline silicon film 7 doped with phosphorus is formed, and the surface is planarized by, for example, a CMP (Chemical Mechanical Polishing) method (FIG. 21).
[0065]
As a result, the floating gate electrodes 7 can be formed, and at the same time, the separation between the floating gate electrodes 7 can be performed in a self-aligned manner by the CVD silicon oxide film 16 which is an insulating film.
[0066]
Thereafter, after the ONO film 8 is formed, the control gate electrode 9 is formed, post-oxidation is performed, and the CVD insulating film 14 is deposited to complete the element formation (FIG. 22).
[0067]
<Modification>
In the structure shown in FIG. 21, the control gate electrode 9 may be formed after the ONO film 8 is formed by etching the CVD silicon oxide film 16 on the sidewall of the floating gate 7 by, for example, the CDE method (FIG. 23). ).
[0068]
In this way, the capacitance is formed between the floating gate electrode sidewall and the control gate electrode formed between the floating gate electrode sidewalls, so that the capacitance can be increased. In this case, it is preferable that the mask layer is stacked thick because the side wall of the floating gate electrode to be formed later becomes higher and the capacitance becomes larger.
[0069]
Of course, the advantages of the above-described embodiment can be obtained at the same time.
[0070]
In this embodiment, an example in which the present invention is applied to an EEPROM (floating gate) has been described. However, the present invention can also be applied to a gate electrode of a MIS transistor.
[0071]
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the invention.
[0072]
【The invention's effect】
According to the onset bright, since the self-aligned manner between the device isolation regions adjacent the electrodes, it is possible to obtain is very finely divided, forming electrodes, problems in a photographic tactile clocking conventional Variations in operating characteristics can be completely eliminated without causing variations in element shape due to misalignment or the like.
[Brief description of the drawings]
FIG. 1 is a plan view of an EEPROM according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view of the EEPROM according to the embodiment. Sectional view [FIG. 4] Cross-sectional view of a process showing the manufacturing method of the EEPROM according to the embodiment. [FIG. 5] Cross-sectional view of the process showing a manufacturing method of the EEPROM according to the embodiment. FIG. 7 is a process cross-sectional view showing a method for manufacturing an EEPROM according to the embodiment. FIG. 8 is a process cross-sectional view showing a method for manufacturing an EEPROM according to the embodiment. FIG. 10 is a process cross-sectional view showing a method for manufacturing an EEPROM according to the same embodiment. FIG. 11 is a process cross-sectional view showing a method for manufacturing the EEPROM according to the same embodiment. One of the examples Process sectional view showing a method for manufacturing an EEPROM according to a modification. FIG. 13 is a process sectional view showing a method for manufacturing an EEPROM according to a modification of the embodiment. FIG. 14 is an EEPROM according to another modification of the embodiment. according to process cross-sectional view and FIG. 17 the reference example illustrating the method of manufacturing the EEPROM of the cross-sectional views [16] the reference example illustrating the method of manufacturing the EEPROM according to a reference example of a cross-sectional view and FIG. 15 the present invention Process cross-sectional view showing an EEPROM manufacturing method [FIG. 18] Process cross-sectional view showing an EEPROM manufacturing method according to the same reference example [FIG. 19] Process cross-sectional view showing an EEPROM manufacturing method according to the same reference example [FIG. section of EEPROM according to the reference example cross sectional views FIG. 22 showing a manufacturing process of an EEPROM according to the process cross-sectional view and FIG. 21 the reference example illustrating the method of manufacturing the EEPROM according to a reference example FIG. 23 is a sectional view of an EEPROM according to a modification of the reference example.
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Thermal oxide film, 3 ... 1st mask layer, 4 ... 2nd mask layer, 5 ... 1st element isolation insulating film, 6 ... 2nd element isolation insulating film, 7 ... Floating gate 8 ... ONO film, 9 ... control gate, 10 ... CVD insulating film, 12 ... groove, 13 ... oxide film, 14 ... CVD insulating film, 16 ... element isolation insulating film, 19 ... n ⁺ type layer, 20, 21 , 23 ... p ⁺ -type layer, 22 ... tunnel oxide film, 30 ... element isolation region, 31 ... element formation region, 32 ... contact hole, 40 ... resist film .

Claims

A groove provided on the surface of the semiconductor substrate;
An isolation region formed by embedding the trench with an insulator, and having a first portion of the sidewall portion of the trench and a second portion of the remaining portion of the trench;
Element regions separated from each other by the element isolation region;
A first gate insulating film formed on the element region;
Charge storage formed on the first gate insulating film, partly overlapping the first portion of the element isolation region, and formed in a self-aligned manner with the second portion of the element isolation region Layers,
A second gate insulating film formed on an upper surface and side surfaces of the charge storage layer and the second portion of the element isolation region;
A control gate electrode formed on the second gate insulating film,
2. The semiconductor memory device according to claim 1, wherein the element isolation region is formed by sequentially filling the groove with two kinds of insulators that can be selectively etched.

The element isolation region includes a first insulating film formed on a side wall portion of the groove, and a second insulating film made of a material different from the first insulating film embedded in the remaining portion of the groove. Configured,
2. The semiconductor memory device according to claim 1, wherein a diffusion layer is formed below the groove in a self-aligned manner with respect to the first insulating film.

2. The semiconductor memory device according to claim 1, wherein the width of the charge storage layer overlapping the element isolation region is effectively the same on both sides of the element region.

A groove provided on the surface of the semiconductor substrate;
A material that is formed by embedding the groove with an insulator, and is different from the first part that protrudes from the groove in the remaining part of the groove and the first part that coincides with the upper part of the groove in the side wall part of the groove An element isolation region having a second portion consisting of:
Element regions separated from each other by the element isolation region;
A first gate insulating film formed on the element region;
Formed on the first gate insulating film, partially overlapping the first portion of the element isolation region and formed in a self-aligned manner with the second portion; A charge storage layer having a generally flat top surface coincident with the top surface of the two portions;
A second gate insulating film formed on the upper surface of the charge storage layer and the upper surface of the element isolation region;
And a control gate electrode formed on the second gate insulating film.

A thermal oxide film, a first mask layer made of a predetermined material, and a second mask layer made of another material that can be selectively removed with respect to the first mask layer are sequentially formed on the surface of the semiconductor substrate. A first step of forming;
A second step of removing the thermal oxide film other than the element formation region, the first mask layer, and the second mask layer;
A third step of forming a groove by etching the surface of the semiconductor substrate exposed in the second step using the second mask layer remaining on the element formation region as a mask;
A fourth step of forming the first insulating film to such an extent that the groove does not fill the inner wall of the groove;
A second insulating film that can be selectively removed with respect to the first insulating film is formed on the second mask layer from the first insulating film formed in the trench. Depositing the upper part of the first insulating film and filling the groove with the second insulating film ;
A sixth step of removing the second insulating film until the same height as the upper end of the first mask layer ;
A seventh step of removing the second mask layer and the first insulating film until an upper end portion of the first mask layer is exposed;
An eighth step of selectively removing the first mask layer so as to leave portions of the first insulating film and the second insulating film protruding from the groove;
A ninth step of selectively removing the first insulating film up to an upper end surface of the groove under a condition that the second insulating film is not etched;
A tenth step of forming a first conductive film;
An eleventh step of removing the first conductive film until an upper end surface of the second insulating film is exposed; and removing the second insulating film located on a side wall of the first conductive film. A twelfth step of exposing a sidewall of the first conductive film;
A thirteenth step of forming a third insulating film on an upper surface, a sidewall, and an upper surface of the second insulating film of the first conductive film;
And a fourteenth step of forming a second conductive film on the upper surface of the third insulating film.

A thermal oxide film, a first mask layer made of a predetermined material, and a second mask layer made of another material that can be selectively removed with respect to the first mask layer are sequentially formed on the surface of the semiconductor substrate. A first step of forming;
A second step of removing the thermal oxide film other than the element formation region, the first mask layer, and the second mask layer;
A third step of forming a groove by etching the surface of the semiconductor substrate exposed in the second step using the second mask layer remaining on the element formation region as a mask;
A fourth step of forming the first insulating film to such an extent that the groove does not fill the inner wall of the groove;
A second insulating film that can be selectively removed with respect to the first insulating film is formed on the second mask layer from the first insulating film formed in the trench. Depositing the upper part of the first insulating film and filling the groove with the second insulating film ;
A sixth step of removing the second insulating film until the same height as the upper end of the first mask layer;
A seventh step of removing the second mask layer and the first insulating film until an upper end portion of the first mask layer is exposed;
An eighth step of selectively removing the first mask layer so as to leave portions of the first insulating film and the second insulating film protruding from the groove;
A ninth step of selectively removing the first insulating film up to an upper end surface of the groove under a condition that the second insulating film is not etched;
A tenth step of forming a film of the first conductive film,
Said first conductive film, by the upper end surface of the second insulating film is polished to expose, eleventh entire top surface of the first conductive film is planarized such that the flat top surface And the process of
A twelfth step of forming a third insulating film on the upper surface of the first conductive film and the upper surface of the second insulating film;
And a thirteenth step of forming a second conductive film on the upper surface of the third insulating film.

A thermal oxide film, a first mask layer made of a predetermined material, and a second mask layer made of another material that can be selectively removed with respect to the first mask layer are sequentially formed on the surface of the semiconductor substrate. A first step of forming;
A second step of removing the thermal oxide film other than the element formation region, the first mask layer, and the second mask layer;
Using the second mask layer remaining on the element formation region as a mask, exposure is performed in the second step. A third step of etching the exposed semiconductor substrate surface to form a groove;
A fourth step of forming the first insulating film to such an extent that the groove does not fill the inner wall of the groove;
A second insulating film that can be selectively removed with respect to the first insulating film is formed on the second mask layer from the first insulating film formed in the trench. Depositing the upper part of the first insulating film and filling the groove with the second insulating film;
A sixth step of removing the second insulating film until the same height as the upper end of the first mask layer;
A seventh step of removing the second mask layer and the first insulating film until an upper end portion of the first mask layer is exposed;
An eighth step of selectively removing the first mask layer so as to leave portions of the first insulating film and the second insulating film protruding from the groove;
A ninth step of selectively removing the first insulating film up to an upper end surface of the groove under a condition that the second insulating film is not etched;
A tenth step of forming a first conductive film;
An eleventh step of removing the first conductive film until an upper end surface of the second insulating film is exposed;
A twelfth step of removing the second insulating film located on the side wall of the first conductive film and exposing the side wall of the first conductive film;
A thirteenth step of forming a third insulating film on an upper surface, a sidewall, and an upper surface of the second insulating film of the first conductive film;
A fourteenth step of forming a second conductive film on the upper surface of the third insulating film;
With
A method of manufacturing a semiconductor memory device, wherein the sixth and seventh steps are simultaneously performed.