JPH08204038A - Semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE: To provide an EEPROM which is excellent in the controllability of the region of a tunnel insulating film and in which a charge injection amount into a floating gate is stable and to provide its manufacturing method. CONSTITUTION: An Si nitride film 35 is deposited on a gate oxide film 34, and a high-temperature oxide film 36 is formed on it. An opening is formed in a region in which a floating gate is to be formed on the high-temperature oxide film, a poly-Si film is deposited so as to be etched back, and a poly-Si sidewall 38 is formed on the sidewall of the opening. A resist pattern 39 which comprises an opening having a size L2 smaller than the bottom face of an opening formed inside the opening which comprises the sidewall 38 having a size L1 larger than the bottom size of the opening in the high-temperature oxide film 36 and which is narrowed by the sidewall in the extension direction of a control gate to be formed later. By making use of the pattern as a mask, the Si nitride film 35 and the Si oxide film 34 in the opening part are removed, a substrate is exposed, and a tunnel oxide film is formed by a thermal oxidation method in the exposed part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has an electrically rewritable EEPRO having a tunnel insulating film having a thinner film thickness than the gate insulating film in a part of a channel region.
It is related to M.

[0002]

2. Description of the Related Art FIG. 1 schematically shows an EEPROM. A tunnel region 13 formed by a diffusion layer is formed in a part of the channel region sandwiched by the drain region 2 and the source region 3 of the silicon substrate 1.
Are formed. Gate insulating film 1 on the channel region
2 is formed, and the tunnel insulating film 1 having a smaller film thickness than the gate insulating film is formed on a part of the tunnel region 13 in the channel region.
6 is formed. A floating gate 17 for accumulating charges is formed on the channel region, and a control gate 19 common to a plurality of memory transistors is formed on the floating gate 17 via an insulating film 18.

In this EEPROM, writing is performed by applying a high voltage to the control gate 19 or the drain 2 to inject charges into the floating gate 17 through the tunnel insulating film 16, and the floating gate 17 is written in the same manner. Erasure is performed by discharging electric charges from the through the tunnel insulating film 16.

FIG. 2 shows a method of manufacturing the EEPROM of FIG. 1 in the order of steps. (A) to (D) shown in the left column of the drawing are cross-sectional views corresponding to FIG. 1, and (a) to (d) shown in the right column are XX ′ line positions in FIG. 1. It is what showed the cut cross section. (A) A field oxide film 14 for element isolation is formed on a silicon substrate 1, and an impurity having a conductivity type opposite to that of the substrate is injected by ion implantation into only a tunnel region including a region where a tunnel oxide film is formed to form a diffusion layer. The tunnel region 16 is formed. After that, the gate oxide film 12 is formed in the element region surrounded by the field oxide film 14.

(B) A photoresist pattern 15 having an opening in the tunnel region is formed by lithography.
The opening has a larger opening dimension than the space between the field oxide films 14 as shown in FIG. 7B in the direction of extension of the control gate to be formed later, and is shown in FIG. The opening is designed to have a size smaller than that of the tunnel region 13 with respect to the direction.
The gate oxide film 12 in the opening is removed by wet etching using the resist pattern 15 as a mask. The wet etching is performed here to reduce damage to the substrate.

(C) After removing the photoresist pattern 15, a tunnel oxide film 16 thinner than the gate oxide film 12 is formed on the substrate 1 exposed by removing the gate oxide film. A floating gate 17 is formed by depositing a polysilicon film on the gate oxide film 12 and the tunnel oxide film 16 and patterning each memory transistor by photolithography and dry etching.

(D) After that, the floating gate 17
An insulating film 18 is formed thereon, a polysilicon film is deposited thereon, and patterned by photolithography and dry etching to form a control gate 19 common to a plurality of memory transistors. Then, using the floating gate 19 as a mask, impurities for source / drain are implanted into the substrate 1.

[0008]

In the EEPROM, it is important to control the area of the tunnel oxide film 16. If this area varies, the amount of charges injected into the floating gate 17 or the amount of charges discharged from the floating gate 17 will vary. In the structure of the conventional EEPROM, the variation in the area of the tunnel oxide film is almost determined by the accuracy in the direction in which the control gate 19 extends (the direction perpendicular to the paper surface in FIG. 2D and the in-plane direction in FIG. 2D). . The variations mainly consist of the following three.

(1) Variation in width of the tunnel region 13, which is ± 0.1 to 0.2 μm. (2) In the step of forming the field oxide film 14, the element region is covered with the silicon nitride film via the buffer oxide film, and the substrate 1 is oxidized to form the field oxide film 14. After that, when the silicon nitride film is removed and the buffer oxide film is removed by wet etching, the field oxide film 1 is removed.
4 is also partially etched, so that the space between the field oxide films 14 varies. This means that when the tunnel oxide film is formed later, the dimension in the extending direction of the control gate varies. This variation is ± 0
It is 0.1 μm.

(3) As shown in FIG. 2B, when the gate oxide film in the region where the tunnel oxide film is formed is removed, field oxidation is performed in the direction in which the control gate extends as shown in (b). Since the dimension of the tunnel oxide film is defined by the distance between the films, the field oxide film is also partially etched when the gate oxide film is removed, and the distance between the field oxide films varies. This variation is ± 0
It is 0.1 μm. Thus, the EE having the conventional structure
In the PROM, the tunnel region 13 is used in the manufacturing process.
Also, there are mainly three factors that cause the dimension of the tunnel oxide film 16 to vary, which makes it difficult to control the characteristics of charge injection into and discharge from the floating gate 17.

Therefore, it is an object of the present invention to provide an EEPROM structure which is excellent in controllability of the tunnel insulating film region and therefore has a stable charge injection amount and discharge amount to the floating gate, and a manufacturing method thereof. .

[0012]

In the EEPROM of the present invention, as shown in FIG. 3 showing an embodiment, the floating gate 43 has a conductor portion 41 in contact with the tunnel insulating film 40, and the conductor portion 41. And another conductor portion 38 surrounding the side of the.

The manufacturing method of the present invention includes the following steps (A) to (L) as shown in FIGS. 4 and 5 showing the manufacturing method of one embodiment. (A) An element isolation insulating film 32 is formed on the surface of a semiconductor substrate 31 of the first conductivity type, and a second conductivity type is formed on a portion of the island-shaped element region surface separated by the insulating film 32 where a tunnel insulating film is to be formed. Of the diffusion layer 33, (B) a step of forming a first insulating film 34 serving as a gate insulating film on the surface of the element region, and (C) a step of forming the first insulating film 34 from above the first insulating film 34. Is a step of forming a different second insulating film 35 on the entire surface, and (D) forming a third insulating film 36 having a different selectivity for dry etching from the second insulating film 35 on the second insulating film 35. Step (E) Step of removing a portion of the third insulating film 36 in the floating gate region by lithography and dry etching to provide an opening in the third insulating film 36, (F) Third insulating film 3
6, a step of depositing a first conductor film from above and performing etching back to form a side wall 38 of the first conductor on the side surface of the opening of the third insulating film 36, which is formed later (G). The side wall 38 is included with a dimension larger than the bottom dimension of the opening of the third insulating film 36 narrowed by the side wall 38 in the direction in which the control gate extends, and by the side wall 38 in the direction orthogonal thereto. A resist pattern 39 of an opening having a dimension smaller than the bottom dimension of the opening is formed in the narrowed opening of the third insulating film 36, and the resist pattern 39 and the sidewall 38 of the first conductor are used as a mask to form the resist. The second insulating film 35 and the first insulating film 34 inside the opening of the pattern 39 and the side wall 38 are removed to expose the surface of the semiconductor substrate to the inside of the opening and the side wall 38 of the resist pattern 39. Step of, (H) After removing the resist pattern 39, the step of forming the insulating film 40 on the exposed surface of the semiconductor substrate serving as a tunnel insulating film, (I)
Third insulating film 36 having side wall 38 of the first conductor inside
Filling the inside of the opening with the second conductor 41, (J) removing the third insulating film 36 to form the floating gate 43 by the first conductor 38 and the second conductor 41, ( K) A step of forming an insulating film 44 on the floating gate 43 and forming a control gate 47 common to a plurality of memory transistors on the insulating film 44, (L) Using the control gate 47 as a mask, the semiconductor substrate 31 in the element region A step of implanting a second conductivity type impurity into the substrate and forming a diffusion layer 48 for source / drain.

Step of embedding the second conductor 41 (I)
Is performed by depositing the second conductor 41 thick enough to eliminate the dents on the surface and then performing etch back to leave the second conductor only in the opening of the third insulating film 36. Alternatively, after depositing the second conductor 41 to a thickness such that a recess remains on the surface, a fourth conductive film 42 is embedded in the recess and the fourth insulating film 42 is used as a mask for the second conductivity. By etching back the body 41, the third
It is preferable to leave the second conductor only in the opening of the insulating film 36.

In step (G), the opening of the resist pattern 39 and the first insulating film 34 inside the side wall 38 of the first conductor are formed.
The etching method for removing the
Is dry-etched to the place where
After that, it is preferable to perform wet etching until the semiconductor substrate is exposed, whereby damage to the semiconductor substrate can be reduced while maintaining the dimensional accuracy of the tunnel insulating film region. After the second conductor 41 is buried in the step (I), impurities are ion-implanted from above the second conductor 41 to form the first conductor 38 and the second conductor 41.
It is preferable that the method further includes a step of electrically connecting the conductor 41 of FIG.

[0016]

EXAMPLE FIG. 3 shows an example. (A)
Is a cross-sectional view taken in a direction crossing the control gate, and (B) is a cross-sectional view in a direction orthogonal to the control gate, that is, a direction in which the control gate extends, taken along line YY 'in (A). is there.

A tunnel region 33 made of an N-type diffusion layer is formed in a part of a channel region sandwiched by a source region and a drain region 48 made of the N-type diffusion layer of the P-type silicon substrate 31, and one surface of the tunnel region 33 is formed. A tunnel oxide film 40 is formed on the gate oxide film 40, and a gate oxide film 34 is formed on the substrate surface of the other part of the channel region.
A floating gate 43 is formed for each memory transistor on the tunnel oxide film 40, and a control gate 47 common to a plurality of memory transistors is formed on the floating gate 43 via an insulating film 44.
Are formed. In this example, floating gate 4
3 as the insulating film 44 between the control gate 47 and
100-400Å thick silicon oxide film 44-
1. Silicon nitride film 4 with a thickness of 50-200Å on it
4-2 and an ONO film in which a silicon oxide film 44-3 having a thickness of 20 to 70 Å is further laminated thereon is used. 49 is an interlayer insulating film, and 50 is a metal wiring connected to the source / drain 48 via a contact hole formed in the interlayer insulating film 49. Floating gate 4
Reference numeral 3 includes a conductor portion 41 in contact with the tunnel insulating film 40, and another conductor portion 38 surrounding the conductor portion 41 laterally with the boundary layer 38a interposed therebetween. Boundary layer 38a
Is a thin oxide film, but has been transformed into a film that is easily electrically conducted due to ion implantation of impurities.

The manufacturing method of this embodiment will be described with reference to FIGS. (A) to (G) shown in the left column of the drawing are sectional views corresponding to FIG. 3 (A), and (a) to (g) shown in the right column correspond to FIG. 3 (B). FIG. (A) After the element isolation field oxide film 32 is selectively formed on the surface portion of the P-type silicon substrate 31, phosphorus or arsenic is formed in the tunnel oxide film formation planned portion in the element region surrounded by the field oxide film 32. Is introduced by an ion implantation method to form an N-type tunnel region 33. The ion implantation conditions at this time are 1 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² at an energy of 50 KeV when arsenic is implanted, for example.
Then, the gate oxide film 34 is formed on the substrate surface by thermal oxidation.
The silicon nitride film 35 is formed to a thickness of 0 to 500Å and the silicon nitride film 35 is formed to 100 to 300Å on the gate oxide film 34 by the CVD method.
Of the high temperature oxide film 3 on the silicon nitride film 35.
6 is deposited to a thickness of 3000 to 6000Å by the CVD method.

(B) A resist pattern 37 having an opening in a region where a floating gate is formed is formed on the high temperature oxide film 36 by photolithography. The high temperature oxide film 36 is dry-etched using the resist pattern 37 as a mask to remove the high temperature oxide film 36 in the opening of the resist pattern.

(C) After removing the resist 37, a polysilicon film is removed from the high temperature oxide film 36 by 1000 to 3000 Å.
Deposited to a thickness of The polysilicon film is etched back by a dry etching method to form a sidewall 38 of polysilicon on the side surface of the opening of the high temperature oxide film 36.

(D) A resist pattern 39 is formed by photolithography. This resist pattern 39
Is larger than the bottom dimension of the opening of the high temperature oxide film 36 narrowed by the side wall 38 in the extending direction of the control gate to be formed later (the direction perpendicular to the paper surface in FIG. (D) and the in-plane direction in (d)). Also has a large dimension L ₁ on its side wall 3
8 and its side wall 38 in the direction orthogonal thereto.
In the opening of the high temperature oxide film 36 which has become narrower due to the above, there is an opening having a dimension L ₂ smaller than the bottom dimension of the opening.

Using the resist pattern 39 as a mask, the silicon nitride film 35 and the silicon oxide film 34 in the opening are removed to expose the surface of the substrate. At this time, the silicon nitride film 35 is removed by dry etching, and the silicon oxide film 34 is etched until the oxide film 34 has a thickness of several tens of Å. After that, 50: 1 BHF (buffered fluoride) is used. Acid) switching to wet etching using an etching solution, and etching is continued until the substrate surface is exposed. This is because if the etching is performed until the substrate surface is exposed only by dry etching, the substrate will be damaged. on the other hand,
The poor controllability of etching when the silicon oxide film 34 is etched by wet etching from the beginning is suppressed.

(E) After removing the photoresist 39,
The silicon nitride film 35 exposed inside the polysilicon side wall 38 is removed by wet etching. Then, a tunnel oxide film 40 is formed in a thickness of 60 to 100Å on the exposed portion of the substrate by a thermal oxidation method. When the tunnel oxide film 40 is formed, the surface of the polysilicon side wall 38 is also oxidized to form an oxide film 38a. Tunnel oxide film 4
Instead of 0, a tunnel insulating film made of an oxynitride film may be used. In order to change the oxide film into an oxynitride film, after forming the oxide film, annealing may be performed in an ammonia atmosphere or a nitrogen atmosphere.

Thereafter, a polysilicon film 41 is deposited by the CVD method to a thickness of 3000 to 5000Å. In the polysilicon film 41 having such a thickness, a recess is formed in the opening of the high temperature oxide film 36. Next, an SOG film (spin-on-glass film) 42 is applied and baked, and then the SOG film 42 is etched back until a part of the SOG film 42 remains in the step portion of the polysilicon film 41. .

(F) Using the SOG film 42 as a mask, the polysilicon film 41 is etched back until the high temperature oxide film 36 is exposed. After that, the SOG film 42 is removed. next,
Impurity phosphorus or arsenic is ion-implanted at 30 to 50 Ke.
V is introduced into the polysilicon films 41 and 38 at 1 × 10 ^{15 to} 2 × 10 ¹⁶ / cm ² . At this time, the polysilicon film 38
Oxide film 38a existing on the boundary between and 41 becomes electrically conductive due to the impurity ion implantation, and at the same time, the conductivity of polysilicon 41 is increased.

(G) Then, the silicon nitride film 35 exposed by removing the high temperature oxide film 36 is removed by a wet etching method. Then, the polysilicon films 38 and 41 are oxidized by a thermal oxidation method to form a silicon oxide film 44-1 having a film thickness of 100 to 400 Å, and then a silicon nitride film 44-having a film thickness of 50 to 200 Å by a CVD method. Deposit 2
The surface of the silicon nitride film 44-2 is oxidized by a thermal oxidation method to form a silicon oxide film 44-3 having a film thickness of 20 to 70Å, and an ONO three-layer insulating film 44 is formed.

Then, a polysilicon film is deposited on the entire surface of the insulating film 44 by the CVD method, and phosphorus is introduced by the thermal diffusion method to reduce the resistance. Then, the polysilicon film and the insulating film 44 are patterned by photolithography and etching to form the control gate 47 and the insulating film 44 between the control gate and the floating gate. Arsenic is ion-implanted into the substrate 31 by using the control gate 47 as a mask at 1 × 10 ¹⁵ to 50-80 KeV.
Introducing 1 × 10 ¹⁶ / cm ² to form source / drain regions 48 of N-type diffusion layers. After that, the interlayer insulating film 4
9 is formed, a contact hole is opened, and a metal electrode 50 connected to the source / drain region 48 is formed.

In the embodiment corresponding to the manufacturing method of the third aspect, the polysilicon film 41 in FIG.
Deposited as thick as 000Å, without forming the SOG film 42,
The polysilicon film 41 is etched back until the high temperature oxide film 36 is exposed.

[0029]

According to the present invention, in the step of exposing the substrate surface in the region where the tunnel insulating film is formed, a polysilicon side wall which will later become a part of the floating gate is formed on the side surface of the opening for the floating gate and is masked. As a result, since the substrate surface is exposed by etching, the dimensions of the tunnel insulating film region can be determined without being affected by the formation conditions of the field oxide film. The process of forming the polysilicon portion of the floating gate existing on the tunnel insulating film as in claims 3 and 4 can be performed only by etching back and does not increase the lithography process, so that the number of steps can be suppressed. In the step of exposing the substrate in the region where the tunnel insulating film is to be formed, the wet etching has difficulty in controllability by switching to dry etching first and then wet etching. It is possible to reduce the damage given to the substrate by performing dry etching on the substrate to compensate for it, and then switching to wet etching when the substrate is exposed. This makes it possible to determine a tunnel region with good controllability while suppressing damage to the substrate. By performing ion implantation as described in claim 6, the insulating film between the conductors of the two layers of the floating gate can be made to be a film that easily conducts, and thus the two layers of the floating gate can be made conductive. . As a result, the floating gate width increases, drain current increases, coupling increases, and transistor performance improves.

[Brief description of drawings]

FIG. 1 is a sectional view showing a conventional EEPROM.

2A to 2D are views showing a method of manufacturing the EEPROM of FIG. 1 in order of steps, (A) to (D) shown in the left column are sectional views corresponding to FIG. 1, and shown in the right column. (A) ~
(D) is a sectional view taken along line XX 'in FIG.

FIG. 3 is a cross-sectional view showing an embodiment, (A) is a cross-sectional view in a state of being cut in a direction crossing a control gate,
(B) is a cross-sectional view taken along line YY 'of (A) in a direction orthogonal to that, that is, in the direction in which the control gate extends.

4A to 4D are process cross-sectional views showing the first half of the manufacturing method according to the embodiment of FIG. 3, in which the left columns (A) to (D) are cross-sectional views corresponding to FIG. 3A to 3D are shown in FIG.
It is sectional drawing corresponding to.

FIG. 5 is a process cross-sectional view showing the latter half of the manufacturing method of the embodiment in FIG. 3, (E) to (G) in the left column are cross-sectional views corresponding to FIG. (E) to (g) are shown in FIG.
It is sectional drawing corresponding to.

[Explanation of symbols]

 31 P-type silicon substrate 33 Tunnel region 34 Gate oxide film 38, 41 Conductor part 40 Tunnel oxide film 43 Floating gate 44 Insulating film 47 Control gate 48 Source / drain region

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/115

Claims (6)

[Claims] 1. A gate insulating film (34) having a tunnel insulating film (40) in a part of a channel region of a semiconductor substrate (31) and a gate insulating film (34) in another part of the channel region. And a floating gate (4) separated for each memory transistor on the tunnel insulating film (40).
3) is formed, and a control gate (47) common to a plurality of memory transistors is formed on the floating gate (43) via an insulating film (44). An electrically rewritable semiconductor memory device. At the floating gate (43),
0) and a conductor portion (41) in contact with the conductor portion (41) and another conductor portion 38 surrounding the conductor portion (41) laterally. 2. A method of manufacturing a semiconductor memory device including the following steps (A) to (L). (A) A device isolation insulating film (32) is formed on the surface of the first conductivity type semiconductor substrate (31), and a tunnel insulating film is to be formed on the island-shaped device region surface separated by the insulating film (32). Forming a diffusion layer (33) of the second conductivity type on the portion,
(B) a step of forming a first insulating film (34) to be a gate insulating film on the surface of the element region, (C) first insulating film (34)
A step of forming a second insulating film (35) different from the first insulating film (34) on the entire surface from above, (D) forming a second insulating film (35) on the second insulating film (35) Is a step of forming a third insulating film (36) having a different selectivity for dry etching. (E) A portion of the third insulating film (36) in the floating gate region is removed by lithography and dry etching. A step of forming an opening in the third insulating film (36), (F) depositing a first conductor film on the third insulating film (36), and performing etch back to perform the third insulating film (36) The side wall of the first conductor (3
8) In the step of forming (G), a dimension larger than the bottom dimension of the opening of the third insulating film (36) narrowed by the side wall (38) in the extending direction of the control gate formed after (G). Of the opening having a dimension smaller than the bottom dimension of the opening in the opening of the third insulating film (36) including the side wall (38) and narrowed in the direction orthogonal to the side wall (38). Resist pattern (3
9) is formed, and the resist pattern (39) and the first
Using the side wall (38) of the conductor as a mask, the opening of the resist pattern (39) and the second insulating film (35) and the first insulating film (34) inside the side wall (38) are removed to remove the resist. Exposing the surface of the semiconductor substrate to the inside of the opening of the pattern (39) and the side wall (38), (H) after removing the resist pattern (39), an insulating film (which becomes a tunnel insulating film) on the exposed surface of the semiconductor substrate ( 40), (I) The second conductor (4) is formed in the opening of the third insulating film (36) having the side wall (38) of the first conductor inside.
1) step of embedding, (J) removing the third insulating film (36) to form a floating gate (43) of the first conductor (38) and the second conductor (41),
(K) An insulating film (4
4) is formed, and a control gate (47) common to a plurality of memory transistors is formed on the insulating film (44).
And (L) a step of implanting a second conductivity type impurity into the semiconductor substrate (31) in the element region using the control gate (47) as a mask to form a diffusion layer 48 for source / drain. 3. The step (I) of burying the second conductor (41) is performed by depositing the second conductor (41) thick enough to eliminate the dents on the surface and then performing etch back. The method of manufacturing a semiconductor memory device according to claim 2, wherein the second conductor is left only in the opening of the third insulating film (36). 4. The step (I) of embedding the second conductor (41) comprises depositing the second conductor (41) to a thickness such that a recess remains on the surface thereof, and then performing a fourth recess in the recess. Of the second conductive material (41) by using the fourth conductive film (42) as a mask to etch back the second conductive material (41). 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the second conductor is left. 5. The resist pattern (39) in the step (G).
The etching method for removing the first insulating film (34) inside the opening of the first conductor and the side wall (38) of the first conductor is dry etching at first until the first insulating film (34) is slightly left. 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the method is performed and then wet etching is performed until the semiconductor substrate is exposed. 6. After embedding with the second conductor (41) in the step (I), impurities are ion-implanted from above the second conductor (41) to form the first conductor (38) and the first conductor (38). The method of manufacturing a semiconductor memory device according to claim 2, further comprising the step of electrically connecting the second conductor (41).