JPH04356969A - Nonvolatile semiconductor device - Google Patents

Abstract

PURPOSE:To improve writing/erasing characteristics by providing a conductive sidewall space to be electrically connected to a floating gate, at the sidewall of the gate. CONSTITUTION:A floating gate of polysilicon is arranged through an SiO2 gate oxide film 4 having a thickness of 300Angstrom and a conductive sidewall spacer 7 of polysilicon is arranged through an SiO2 tunnel oxide film 6 having a thickness of 80Angstrom on a drain 3, on an Si substrate 1 having N-type source and drain 2, 3. The gate 5 is formed of a gate body 9 arranged through a spacer insulating film 8 of the spacer 7, a gate piece 10 so arranged thereon as to be electrically connected to the spacer 7, and a gate sidewall 11 arranged above the source 2. Thus, an overlapped part of the source or/and drain and the spacer can be reduced in thickness as a tunnel region, thereby improving writing/erasing characteristics. Further, generation of a junction leakage can be prevented.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is based on FLOTOX (Flo
The present invention relates to a nonvolatile memory having a gate oxide (Gate Oxide) transistor.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 9, a memory has a floating gate 95 disposed on a Si substrate 91 having an N-type diffusion layer 92 with a thin gate oxide film 93 and a tunnel oxide film 94 interposed therebetween. There is. After simultaneously forming a thin gate oxide film 93 and a tunnel oxide film 94, polysilicon is deposited as a floating gate 95, ions are implanted in a self-aligned manner using this gate as a mask, and an N-type diffusion layer is formed by this ion implantation. The overlapping portion 96 of the floating gate and the floating gate becomes a tunnel region.

0003

However, since the gate oxide film and the tunnel oxide film are formed at the same time, the reliability of the transistor deteriorates, and since the film thickness is approximately 100 Å, it cannot be made very thin. Furthermore, since the end of the N-type diffusion layer is located under the thin gate oxide film, a high voltage cannot be applied to the N-type diffusion layer because so-called gate-controlled band-to-band junction leakage occurs.

0004

[Means for Solving the Problems and Their Effects] The present invention provides a FLOTOX type nonvolatile memory in which a floating gate and a control gate are sequentially stacked on a semiconductor substrate having a source and a drain via a gate oxide film. and/or a non-volatile semiconductor device including a conductive sidewall spacer made of the same material as the floating gate, disposed on the sidewall side of the floating gate above the drain and electrically connected to the floating gate. That is, the present invention provides a conductive sidewall space on the sidewall side of the floating gate, which is electrically connected to the floating gate, thereby making it possible to make the thickness of the gate oxide film different from the thickness of other films. , source or/
Also, the overlap portion between the drain and the conductive sidewall spacer can be made thinner, and this can be used as a tunnel region to improve write/erase characteristics. Further, since the gate oxide film where the end of the source and/or drain is located can be made thicker than before, it is possible to prevent junction leakage.

[0005]

[Example] This invention will be explained below. Note that this invention is not limited thereby. FIG. 7 shows a first embodiment of the invention. In FIG. 7, the memory is constructed by forming a polysilicon floating gate 5 on a Si substrate 1 having an N-type source 2 and a drain 3 through an SiO2 gate oxide film 4 with a thickness of 300 Å, and a polysilicon floating gate 5 with an 80 Å thickness on the drain 3. Conductive sidewall spacers 7 of polysilicon are disposed through a thick tunnel oxide film 6 of SiO2. The floating gate 5 includes a gate body 9 disposed through a spacer insulating film 8 of a spacer 7 , a gate piece 10 disposed on the gate body 9 so as to be electrically connectable to the spacer 7 , and a gate piece 10 above the source 2 . Gate side wall 1 installed in
Consists of 1. The manufacturing method will be explained below. first,
As shown in FIG. 1, after forming a 300 Å thick gate oxide film 4 on a Si substrate 1, a 2000 Å thick polysilicon layer 1
After sequentially stacking a SiO2 layer and a photoresist layer with a thickness of 000 Å, a photoresist pattern 15 is formed, and using this as a mask, the SiO2 layer and the polysilicon layer are etched to form the first polysilicon film 9 and the SiO2 layer as a floating gate. A pattern 14 is formed. Next, after removing the resist pattern 15, As ions 16 are implanted using the polysilicon film 9 and pattern 14 as masks to form an N-type source 2 and drain 3 (see FIG. 2). Subsequently, the gate oxide film 4 on the drain 3 is removed using the photoresist pattern 17 as a mask. Subsequently, after removing the pattern 17, the S layer containing the polysilicon film 9 is removed.
The entire surface of the i-substrate 1 is oxidized to form a tunnel oxide film 6 with a thickness of 80 Å.
A second polysilicon layer 18 with a thickness of 3000 Å is formed.
(see FIG. 4) and etch back the entire surface to form conductive sidewall spacers 7 of polysilicon on the drain 3 (see FIG. 5). At this time, the conductive sidewall spacer 7 is connected to the gate body 9 via the spacer insulating film 8, and a SiO2 film 14 is provided on the gate 9 to mask the gate body 9 during etchback. . Next, S
After removing the iO2 film 14, a third polysilicon film 19 with a thickness of 2500 Å is deposited (see FIG. 6), and this is etched back to form a gate that can electrically connect the conductive sidewall spacers 7 and the gate body 9. A piece 10 is formed (FIG. 7). Thereafter, control gates 22 and the like are formed with the control gate insulating film 21 interposed therebetween by a known method. In this way, a non-volatile memory can be formed.

[0006]

As described above, according to the present invention, a conductive side wall space is provided on the side wall side of the floating gate to be electrically connected to the floating gate, thereby controlling the thickness of the gate oxide film and other films. By making the thickness different, the overlap between the source and/or drain and the conductive sidewall spacer can be made thinner, which can be used as a tunnel region to improve write/erase characteristics. Further, since the gate oxide film where the end of the source and/or drain is located can be made thicker than before, it is possible to prevent junction leakage.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing the first step of the manufacturing process in an embodiment of the present invention.

FIG. 2 is a configuration explanatory diagram showing the second step of the manufacturing process in the above embodiment.

FIG. 3 is a configuration explanatory diagram showing the third step of the manufacturing process in the above embodiment.

FIG. 4 is a configuration explanatory diagram showing the fourth step of the manufacturing process in the above embodiment.

FIG. 5 is a configuration explanatory diagram showing the fifth step of the manufacturing process in the above embodiment.

FIG. 6 is a configuration explanatory diagram showing the sixth step of the manufacturing process in the above embodiment.

FIG. 7 is a configuration explanatory diagram showing the seventh step of the manufacturing process in the above embodiment.

FIG. 8 is a configuration explanatory diagram showing the eighth step of the manufacturing process in the above embodiment.

FIG. 9 is a configuration explanatory diagram showing a conventional example.

[Explanation of symbols]

1 Si substrate 2. Source 3 Drain 4 Gate oxide film 5 Floating gate 7 Conductive side wall spacer 8 Spacer insulation film 22 Control gate

Claims (3)

[Claims] 1. In a FLOTOX type nonvolatile memory in which a floating gate and a control gate are sequentially stacked on a semiconductor substrate having a source and a drain via a gate oxide film, the sidewall side of the floating gate on the source and/or the drain. A non-volatile semiconductor device comprising a conductive sidewall spacer made of the same material as the floating gate and electrically connected to the floating gate. 2. The floating gate is partially separated from the conductive sidewall spacer by a spacer insulating film having a thickness different from that of the gate oxide film, and the sidewall spacer has a tunnel oxide film directly below. A nonvolatile semiconductor device according to claim 1, comprising: 3. The non-volatile semiconductor device according to claim 1, wherein the source and/or the drain have a region end extending beyond just below the conductive sidewall spacer to just below the floating gate.