JP2907970B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an EPROM (Erasable Programmable Read Only Memory).
This is to improve the writing characteristics of y).

[Conventional technology]

EPROM is a semiconductor device used as a non-volatile memory, and is a FAMOS (Floating gate Avalanche injecti
On-Metal Oxide Semiconductor (EPROM) type EPROMs are particularly well known, but this type of EPROM has the disadvantage of a slow writing speed.

Therefore, there is a conventional EPROM with a high writing speed as shown in FIGS. 3 (a) and 3 (b).

3 (a) is a cross-sectional view showing the structure of a conventional EPROM, and FIG. 3 (b) is a cross-sectional view taken along the line BB of FIG. 3 (a). Element isolation regions 2,... 2 made of an oxide film are formed, and portions surrounded by the element isolation regions are element regions 3 and 4.

Thin oxide films 5 and 6 are formed in the element regions 3 and 4, and a floating gate 7 extending over both the element regions 3 and 4 beyond the element isolation region 2 is formed on the thin oxide films 5 and 6. Are laminated.

The floating gate 7 is made of, for example, a low-resistance metal formed by doping phosphorus after depositing polysilicon.

An N ^{+ -type} diffusion layer 8 for a source and an N ^{+ -type} diffusion layer 9 for a drain are formed in one of the element regions 3 so as to sandwich an area under the thin insulating film 5 of the floating gate 7. One of the N ^{+ -type} diffusion layers 8 is connected to a ground line 8a made of a metal such as aluminum, and the other N ^{+ -type} diffusion layer 9 is connected to a bit line 9a made of a metal such as aluminum.

That is, a MOS transistor is formed in the element region 3.

On the other hand, in the element region 4, an N ^{+ -type} diffusion layer 10 is formed below the floating gate 7 with the thin oxide film 6 interposed therebetween, and the N ^{+ -type} diffusion layer 10 is made of a metal such as aluminum. Connected to line 10a.

Further, the entire upper surface of the semiconductor substrate 1 is covered with the interlayer insulating film 11.

The FAMOS is hot due to a breakdown phenomenon that occurs when a high voltage is applied to the bit line 9a and the word line 10a, that is, the N ^{+ type} diffusion layer 9 serving as a drain and the N ^{+ type} diffusion layer 10 serving as a control gate. Data is written using the injection of electrons into the floating gate 7, but with such a configuration, the capacitance ratio is larger than that of a normal FAMOS in which a control gate is formed on the floating gate 7. Therefore, writing can be speeded up.

[Problems to be solved by the invention]

However, in the above-described conventional technology, writing is performed by injecting electric charges into the floating gate 7 by avalanche injection, so that a high voltage is required and the shortening of the writing time is not sufficient.

The present invention has been made in view of such unresolved problems of the conventional technology, and achieves a shorter writing time without complicating the manufacturing process.
It is intended to provide a ROM and a method of manufacturing the ROM.

[Means for solving the problem]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention includes a first and a second element region formed on a semiconductor substrate and an insulating film formed on the semiconductor substrate via an insulating film. A floating gate extending over both the first and second element regions, and a first gate formed below the floating gate in the first element region with the insulating film interposed therebetween and having the same shape as the semiconductor substrate. A high-concentration diffusion layer, a source / drain diffusion layer formed so as to sandwich an area of the first element region below the floating gate with the insulating film interposed therebetween, and the second element region A second high-concentration diffusion layer formed under the floating gate with the insulating film interposed therebetween and having the same shape as the semiconductor substrate, and formed so as to surround the second high-concentration diffusion layer Re was and and a said semiconductor substrate opposite type well.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an element isolation region on a semiconductor substrate;
Forming a second element region and a step of forming a well opposite to the semiconductor substrate in the second element region; and performing ion implantation simultaneously on the first and second element regions. Forming a high-concentration diffusion layer having the same shape as the semiconductor substrate in both the first element region and the well; and connecting the floating gate extending to both the first and second element regions to the semiconductor via an insulating film. Forming on the substrate, forming a source / drain diffusion layer on the semiconductor substrate sandwiching an area below the floating gate in the first element region with the insulating film interposed therebetween. Was.

[Action]

In the invention according to claim (1), when a voltage is applied to the drain diffusion layer and the second high-concentration diffusion layer, the first
High concentration diffusion layer becomes a high depletion layer region, so substrate hot electron injection (BBISHE: Ban
d to Band tunneling Induced Substrate Hot Electro
n) happens and the writing takes place.

Since BBISHE is more efficient than avalanche injection, writing to the semiconductor device of the present invention is performed at a higher speed than EPROM using avalanche injection.

Further, since both the first high-concentration diffusion layer and the second high-concentration diffusion layer have the same shape as the semiconductor substrate, the first
And the second high-concentration diffusion layer can be formed at the same time, and since a well inverse to the semiconductor substrate is formed so as to surround the second high-concentration diffusion layer, it functions as a control gate. It is also possible to prevent the substrate potential from fluctuating due to the voltage applied to the second high concentration diffusion layer. Furthermore, since the well is usually manufactured at any part in the manufacturing process of the semiconductor device, even if the well is formed in the second element region, only the mask pattern needs to be changed. There is no increase in the number of steps.

According to the invention of claim (2), ion implantation is performed on the first and second element regions to form a high-concentration diffusion layer having the same shape as the semiconductor substrate. Since the first and second high-concentration diffusion layers in the semiconductor device are formed in a single step, the number of steps is not increased.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a cross-sectional view showing a configuration of a semiconductor device according to the present invention, and FIG. 1B is a cross-sectional view taken along the line AA of FIG. 3 The same reference numerals are given to the same members and parts as those in FIGS. 3A and 3B, and the overlapping description will be omitted.

That is, the configuration of the semiconductor device according to the present embodiment is such that a high-concentration diffusion layer having the same shape as the semiconductor substrate 1 is provided below the floating gate 7 of the element region 3 as the first element region with the thin insulating film 5 therebetween. A P ^{+ type} diffusion layer 12 is formed, and a floating gate 7 of an element region 4 as a second element region is formed.
The P ^{+ -type} diffusion layer 13 which is a high-concentration diffusion layer having the same shape as the semiconductor substrate 1 instead of the N ^{+ -type} diffusion layer and surrounds the lower surface of the P ^{+ -type} diffusion layer 13 below the thin insulating film 6. Except that the n-well 1a was formed, it is the same as the conventional device shown in FIGS. 3 (a) and 3 (b).

2A to 2D are cross-sectional views showing the steps of manufacturing the semiconductor device of this embodiment.

First, an n-well 1a having a shape opposite to that of the semiconductor substrate 1 is formed on a P-type semiconductor substrate 1, and element isolation regions 2,..., 2 made of a LOCOS oxide film are formed.
Is formed, and a sacrificial oxide film 15 is formed in the element regions 3 and 4 (see FIG. 2A).

Next, a resist pattern 16 having openings in the center of the element region 3 and the element region 4 is formed by a normal photo process.
Is formed, boron ions B ⁺ are implanted to form an element region 3
Then, a P ^{+ -type} diffusion layer 12 is formed, and a P ^{+ -type} diffusion layer 13 is formed in the element region 4 (see FIG. 2B).

Here, the P ⁺ concentration of the P ^{+ -type} diffusion layers 12 and 13 is set to 10 ^{18 to} 5 × 10 ¹⁸ (cm ⁻³ ) at which the efficiency of BBISHE is maximized.

Then, after removing the resist pattern 16 and the sacrificial oxide film 15, thin oxide films 5 and 6 are formed in the element regions 3 and 4 (see FIG. 2C).
After arranging polysilicon over both of them, phosphorus is doped to form a floating gate 7 (FIG. 2 (d)).
reference).

Thereafter, an N ^{+ -type} diffusion layer 8 serving as a source diffusion layer and an N ^{+ -type} diffusion layer 9 serving as a drain diffusion layer are formed so as to sandwich the area under the thin oxide film 5 in the element region 3. The N ^{+ type} diffusion layer 8 is connected to the ground line 8a, and the N ^{+ type} diffusion layer 9 is connected to the bit line.
9a, the entire upper surface of the semiconductor substrate 1 is covered with an interlayer insulating film 11, and a P ^{+ type} diffusion layer 13 serving as a control gate is connected to a word line 10a (see FIGS. 1 (a) and 1 (b)).

Then, the injecting charges into the floating gate 7, the N ⁺ form diffusion layer 9 as drain, a positive voltage is applied to the P ⁺ diffusion layer 13 serving as a control gate, the P ⁺ diffusion layer
BBISHE should be caused by setting 12 as the high depletion layer region.
Is more efficient than normal channel hot electrons, so that charge injection into the floating gate 7, that is,
Since writing to the EPROM becomes faster and does not require a high voltage, the writing characteristics are improved.

Further, since the P ^{+ -type} diffusion layer 12 serving as a writing region can be formed at the same time as the P ^{+ -type} diffusion layer 13 is formed, the number of steps does not increase and the cost does not increase. Similarly, if the semiconductor device is the n-well 1a, the
Since it is formed at a different cross-sectional position not shown in the drawings, a new process for forming only the n-well 1a is not newly provided. Only the number of steps needs to be changed, and the number of steps is not particularly increased and the cost is not increased.

The diffusion layer serving as the control gate is a P ^{+ -type} diffusion layer 13 having the same shape as the semiconductor substrate 1. However, the control gate may be floating regardless of whether it is a P ^{+ -type} diffusion layer or an N ^{+ -type} diffusion layer. The characteristics of writing to the gate 7 hardly change.

Further, in the above embodiment, the case where a P-type semiconductor substrate is used is described, but the present invention is not limited to this, and an N-type semiconductor substrate may be used. However, in that case, an N ^{+ type} diffusion layer is formed as the high concentration diffusion layer.

〔The invention's effect〕

As described above, in the invention described in claim (1), the high-concentration diffusion layer having the same shape as the semiconductor substrate is formed below the floating gate in the first element region with the insulating film interposed therebetween. There is an effect that writing to the floating gate is performed at a high speed, a high voltage is not required, and the manufacturing cost can be suppressed since the number of steps is not increased in manufacturing.

Further, according to the invention described in claim (2), the semiconductor device described in claim (1) can be manufactured in the same number of steps as in the related art, so that there is an effect that cost is not increased. is there.

[Brief description of the drawings]

FIG. 1 (a) is a cross-sectional view showing the configuration of one embodiment of the present invention,
1 (b) is a cross-sectional view taken along line AA of FIG. 1 (a), FIGS. 2 (a) to 2 (d) are cross-sectional views showing an example of a manufacturing process of the semiconductor device of the present embodiment, and FIG. 3A is a cross-sectional view showing the structure of a conventional semiconductor device, and FIG. 3B is a sectional view taken along line BB of FIG.
It is a line sectional view. 1 ... semiconductor substrate, 1a ... n well, 2 ... element isolation region, 3 ... element region (first element region), 4 ... element region (second element region), 5, 6 ... Thin oxide film (insulating film), 7 ... Floating gate, 8 ... N ^{+ type} diffusion layer (diffusion layer for source), 9 ... N ^{+ type} diffusion layer (diffusion layer for drain), 12 ... P ⁺ -Type diffusion layer (first high-concentration diffusion layer), 13... P ^{+ -type} diffusion layer (second high-concentration diffusion layer)

Claims (2)

(57) [Claims] A first and second element region formed on a semiconductor substrate; and a floating gate formed on the semiconductor substrate via an insulating film and extending over both the first and second element regions. A first high-concentration diffusion layer formed below the floating gate in the first element region with the insulating film interposed therebetween and having the same shape as the semiconductor substrate;
A source / drain diffusion layer formed so as to sandwich an area below the floating gate in the first element region that separates the insulating film; and a lower layer of the floating gate in the second element region. A second substrate formed with the insulating film interposed therebetween and having the same shape as the semiconductor substrate.
A high-concentration diffusion layer, and a well formed to surround the second high-concentration diffusion layer and having an inverse shape to the semiconductor substrate;
A semiconductor device comprising: 2. A step of forming an element isolation region on a semiconductor substrate to form first and second element regions, and a step of forming a well opposite to the semiconductor substrate in the second element region. Forming a high-concentration diffusion layer having the same shape as the semiconductor substrate in both the first element region and the well by simultaneously ion-implanting the first and second element regions; Forming a floating gate over both of the two element regions on the semiconductor substrate with an insulating film interposed therebetween, and a source sandwiching a lower area of the floating gate in the first element region which is separated by the insulating film. Forming a drain diffusion layer on the semiconductor substrate; and a method for manufacturing a semiconductor device.