US5898006A - Method of manufacturing a semiconductor device having various types of MOSFETS - Google Patents

Method of manufacturing a semiconductor device having various types of MOSFETS Download PDF

Info

Publication number
US5898006A
US5898006A US08/524,850 US52485095A US5898006A US 5898006 A US5898006 A US 5898006A US 52485095 A US52485095 A US 52485095A US 5898006 A US5898006 A US 5898006A
Authority
US
United States
Prior art keywords
mosfet
gate
logic circuit
mos transistor
dose amount
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US08/524,850
Inventor
Takaharu Kudoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Assigned to NEC CORPORATION reassignment NEC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KUDOH, TAKAHARU
Application granted granted Critical
Publication of US5898006A publication Critical patent/US5898006A/en
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device having a non-volatile semiconductor memory built therein, and more particularly, to a method of manufacturing a semiconductor device composed of transistors of a single drain structure and transistors of a double drain structure such as a lightly doped drain structure or a graded junction structure.
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • the MOSFETs for the logic circuit preferably include source and drain regions formed so as to have double drain structure such as LDD structure or graded junction structure adapted to withstand hot electrons because the MOSFETs need to have resistance against hot electrons.
  • the MOSFETs for the memory cell have source and drain regions formed so as to have single drain structure because hot electrons need to be effectively generated for writing data in the non-volatile memory cell.
  • source and drain regions are formed so as to have single drain structure of low resistivity because the MOSFET can be prevented from being destroyed thermally by input electrostatic charge.
  • a p-type silicon substrate 111 is provided with a memory cell formed region 102a, a MOSFET formed region 102b for input protection, and a MOSFET formed region 102c for a logic circuit on the surface region.
  • a double gate electrode structure 113a composed of a floating gate electrode 115a, an insulating film 114, and a control gate electrode 115b, is formed on the substrate 111 via a gate insulating film 112.
  • gate electrodes 113b and 113c of single gate structure are formed on the substrate 111 via the gate insulating films 112.
  • phosphorus (P) ions are injected into the substrate 111 with acceleration energy of 100 KeV and a dose amount of 2 to 3 ⁇ 10 13 cm -2 in self-alignment with the double gate structure 113a and gate electrodes 113b and 113c using them as a mask to form n-type low dose amount diffusion layers 116.
  • a photoresist layer 119 is formed on the whole surface of the substrate 111 and then the photoresist layer 119 is removed from the memory cell formed region 102a using a first photoresist mask.
  • the MOSFET formed regions 102b and 102c remain covered by the photoresist layer 119.
  • arsenic (As) ions are injected into the substrate 111 with acceleration energy of 70 KeV and a dose amount of 5.0 ⁇ 10 15 cm -2 in self-alignment with the double gate structure 113a using it as a mask.
  • n-type high dose amount diffusion layers 118 are formed.
  • the n-type diffusion layers 118 functions as source and drain regions of a MOSFET for a memory cell having single drain structure.
  • the photoresist layer 119 is removed and a silicon oxide film is deposited on the whole substrate 111 by a low pressure CVD method.
  • the silicon oxide film is etched back by an anisotropic plasma etching method, so that side wall insulating films 120a, 120b and 120c are formed on the side walls of the double gate structure 113a and gate electrodes 113b and 113c.
  • a photoresist layer 121 is formed on the whole surface of the substrate 111. Then, the photoresist layer 121 is removed from the MOSFET formed region 102c for the logic circuit using a second photoresist mask, so that the memory cell formed region 102a and MOSFET formed region 102b for input protection remain covered with the photoresist layer 121. Subsequently, arsenic (As) ions are injected into the substrate 111 with acceleration energy of 70 KeV and dose amount of 3.0 ⁇ 10 15 cm -2 in self-alignment with the gate electrode 113c and side wall insulating film 120c using them as a mask.
  • As arsenic
  • n-type high dose amount diffusion layers 122 are formed while the low concentration n-type diffusion layers 116 remain.
  • the source and drain regions having double drain structure such as the graded junction structure or LDD structure are completed for the MOSFET for the logic circuit.
  • a photoresist layer 123 is formed on the whole surface of the substrate 111. Then, the photoresist layer 123 is removed from the MOSFET formed region 102b for input protection using a third photoresist mask, so that the memory cell formed region 102a and MOSFET formed region 102c for the logic circuit remain covered with the photoresist layer 123. Subsequently, phosphorus (P) ions are injected into the substrate 111 with acceleration energy of 70 KeV and dose amount of 1.0 ⁇ 10 15 cm -2 in self-alignment with the gate electrode 113b and side wall insulating film 120b using them as a mask.
  • P phosphorus
  • n-type diffusion layers 124 of high dose amount are formed while the low concentration n-type diffusion layers 116 remain.
  • a thermal treatment is performed after the ion injection.
  • phosphorus ions diffuse from the n-type high dose amount diffusion layer to a portion under the side wall insulating film 120b so that the source and drain regions 124 having single drain structure are completed.
  • the MOSFET having a single drain structure for the memory cell and input protection and the MOSFET having the double drain structure for the logic circuit are formed through a process of injecting impurity into all the MOSFET in common with a low dose amount, and a process of individually injecting impurity into each of the MOSFETs with a high dose amount. Therefore, three photoresist masking processes and four ion injecting processes are required. As a result, it is difficult to reduce manufacturing cost of the semiconductor device, and production yield also is reduced.
  • the present invention is made from the above standpoint and has, as an object, to provide a method of manufacutring a semiconductor device having various types of MOSFETs with simple processes.
  • Another object of the present invention is to provide a method of manufacturing a semiconductor device wherein the method can be simplified based on the drain structure.
  • a method of manufacturing a semiconductor device including on a single chip a non-volatile memory element, an input protecting element and a logic circuit element, comprising the steps of:
  • the non-volatile memory element, input protecting element and logic circuit element may be a first type of MOSFET required to have capability of generation of hot electrons, a second type of MOSFET required to have resistance against electrostatic break down, and a third type of MOSFET required to have resistance against hot electrons, respectively.
  • a side wall insulating film is preferably formed on a side wall of each of the gate structures of the non-volatile memory element, input protecting element and logic circuit element before the injection for the logic circuit element is performed. If there is the side wall insulating film, the impurity of the second conductivity type is injected in the parts of the source and drain regions of the logic circuit element in alignment with the side wall insulating film and gate structure for the logic circuit element. In this case, the injection may be performed so as to form the source and drain regions so as to have a lightly doped drain (LDD) structure or a graded junction structure.
  • LDD lightly doped drain
  • the impurity of the second conductive type is simultaneously injected in the substrate in self-alignment with the gate structures for the non-volatile memory element, input protecting element and logic circuit element with the first dose amount.
  • the injection of phosphorus (P) ions is performed in step (b), and the injection of arsenic ions (As) is performed in steps (c) and (d), masking a region for the logic circuit element to be formed, by photoresist using a first mask in step (c) and masking regions for the non-volatile memory element and input protecting element to be formed, by photoresist using a second mask in step (d).
  • a method of manufacturing a semiconductor device including on a single chip a first type of metal-oxide-semiconductor field effect transistor (MOSFET) required to have capability of generation of hot electrons, a second type of MOSFET required to have resistance against electrostatic break down, and a third type of MOSFET required to have resistance against hot electrons, comprising the steps of:
  • FIGS. 1A to 1E are schematic diagrams showing a conventional method of manufacturing a semiconductor device with a non-volatile memory built therein;
  • FIGS. 2A to 2D are schematic diagrams showing a method of manufacturing a semiconductor device with a built-in non-volatile memory according to the present invention.
  • a p-type silicon substrate 11 is provided with a MOSFET formed region 2a for a memory cell such as an EPROM, a MOSFET formed region 2b for input protection, and a MOSFET formed region 2c for a logic circuit on the surface region.
  • a double gate electrode structure 13a composed of a gate electrode 15a, an insulating film 14, and a control gate electrode 15b, is formed on the substrate 11 via a gate insulating film 12.
  • gate electrodes 13b and 13c of a single gate structure are formed on the substrate 11 via the gate insulating films 12.
  • phosphorus (P) ions are injected into the substrate 11 with acceleration energy of 100 KeV and dose amount of 2 to 3 ⁇ 10 13 cm -2 in self-alignment with the double gate structure 13a and single gate electrodes 13b and 13c using them as a mask to form n-type diffusion layers 116 of low dose amount.
  • a photoresist layer 19 is formed on the whole surface of the substrate 11 and then the photoresist layer 19 is removed from the MOSFET formed regions 2a and 2b for the memory cell and input protection using a first photoresist mask.
  • the MOSFET formed region 2c remains covered by the photoresist layer 19.
  • arsenic (As) ions are injected into the substrate 11 with acceleration energy of 70 KeV and dose amount of 5.0 ⁇ 10 15 cm -2 in self-alignment with the double gate structure 13a and single gate structure 13b using them as a mask.
  • n-type diffusion layers 18 of high dose amount are formed while low dose amount n-type diffusion layers 16 remain under the layers 18.
  • the n-type diffusion layers 18 function as source and drain regions of the MOSFETs having single drain structure.
  • the impurity doping level is high because hot electrons can be effectively generated.
  • the impurity doping level is high because electrostatic charge can be effectively discharged.
  • the actual impurity doping level is selected from the region where the region of impurity doping level desired for the MOSFET for a non-volatile memory cell and the region of impurity doping level desired for the MOSFET for input protection overlap.
  • the photoresist layer 19 is removed and a silicon oxide film is deposited on the whole substrate 111 by a low pressure CVD method.
  • the silicon oxide film is etched back by an anisotropic plasma etching method, so that side wall insulating films 20a, 20b and 20c are formed on the side walls of the double gate structure 13a and single gate electrodes 13b and 13c.
  • a photoresist layer 21 is formed on the whole surface of the substrate 11. Then, the photoresist layer 21 is removed from the MOSFET formed region 2c for the logic circuit using a second photoresist mask, so that the MOSFET formed regions 2a and 2b remain covered with the photoresist layer 21. Subsequently, arsenic (As) ions are injected into the substrate 11 with acceleration energy of 70 KeV and dose amount of 3.0 to 5.0 ⁇ 10 15 cm 2-2 in self-alignment with the gate electrode 13c and side wall insulating film 20c using them as a mask. As a result, n-type diffusion layers 22 of high dose amount are formed at part of the n-type low dose amount diffusion layers 16. As a result, the source and drain regions having the double drain structure, such as the LDD or graded junction structure, can be completed for the MOSFET for the logic circuit. Therefore, generation of hot electrons can be suppressed.
  • As arsenic
  • three types of MOSFETs having the single drain and double drain structure such as the LDD or graded junction structure, can be formed by two photoresist mask forming processes and three ion injecting processes. Therefore, one photoresist mask forming and one ion injecting process can be omitted compared to the conventional method of the semiconductor device. Although the whole processes are simplified, the capability to generate effectively hot electrons, resistance against electrostatic break down, and suppression of generation of hot electrons can be satisfied in the MOSFET for a memory cell such as an EPROM, the MOSFET for input protection, and the MOSFET for logic circuit, respectively.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

In a method of manufacturing a semiconductor device including a first MOSFET for a non-volatile memory element, a second MOSFET for an input protecting element and a third MOSFET for a logic circuit element, gate structures of the first to third MOSFETs are formed on a p-type substrate. Then, an n-type impurity is injected in the substrate in self-alignment with the gate structure for the third MOSFET with a first dose amount to form source and drain regions for the third MOSFET. An n-type impurity is simultaneously injected in the substrate in self-alignment with the gate structures for the first and second MOSFETs to form source and drain regions for the first and second MOSFETs. A side wall insulating film is formed on a side wall of each of the gate structures of the thirst to third MOSFETs. An n-type impurity is injected in parts of the source and drain regions of the third MOSFET in self-alignment with the side wall and gate structure with a second dose amount which is higher than the first dose amount.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a non-volatile semiconductor memory built therein, and more particularly, to a method of manufacturing a semiconductor device composed of transistors of a single drain structure and transistors of a double drain structure such as a lightly doped drain structure or a graded junction structure.
2. Description of Related Art
Conventionally, in a semiconductor device such as a single chip microcomputer, circuits for a random access memory (RAM) and a read only memory (ROM) are mounted on the same chip in addition to logic circuits. In this case, at least a part of the ROM is formed of a non-volatile memory such as an electrically programmable ROM (EPROM). In the semiconductor device with such a non-volatile memory built therein, at least three types of metal-oxide-semiconductor field effect transistors (MOSFETs), i.e., MOSFETs for a logic circuit, MOSFETs for memory cells (including a MOSFET with a double gate electrode structure), and MOSFETs for input protection are required. Of these MOSFETs, the MOSFETs for the logic circuit preferably include source and drain regions formed so as to have double drain structure such as LDD structure or graded junction structure adapted to withstand hot electrons because the MOSFETs need to have resistance against hot electrons. The MOSFETs for the memory cell have source and drain regions formed so as to have single drain structure because hot electrons need to be effectively generated for writing data in the non-volatile memory cell. Further, in the MOSFETs for input protection, source and drain regions are formed so as to have single drain structure of low resistivity because the MOSFET can be prevented from being destroyed thermally by input electrostatic charge.
Next, a method of manufacturing the above-mentioned conventional semiconductor device will be described below with reference to FIGS. 1A to 1E.
First, as shown in FIG. 1A, a p-type silicon substrate 111 is provided with a memory cell formed region 102a, a MOSFET formed region 102b for input protection, and a MOSFET formed region 102c for a logic circuit on the surface region. In the memory cell formed region 102a, a double gate electrode structure 113a composed of a floating gate electrode 115a, an insulating film 114, and a control gate electrode 115b, is formed on the substrate 111 via a gate insulating film 112. In the MOSFET formed regions 102b and 102c, gate electrodes 113b and 113c of single gate structure are formed on the substrate 111 via the gate insulating films 112. Note that insulating films and regions for isolating elements are not shown because they are well known to a person skilled in the art. Thereafter, phosphorus (P) ions are injected into the substrate 111 with acceleration energy of 100 KeV and a dose amount of 2 to 3×1013 cm-2 in self-alignment with the double gate structure 113a and gate electrodes 113b and 113c using them as a mask to form n-type low dose amount diffusion layers 116.
Next, as shown in FIG. 1B, a photoresist layer 119 is formed on the whole surface of the substrate 111 and then the photoresist layer 119 is removed from the memory cell formed region 102a using a first photoresist mask. As a result, the MOSFET formed regions 102b and 102c remain covered by the photoresist layer 119. Subsequently, arsenic (As) ions are injected into the substrate 111 with acceleration energy of 70 KeV and a dose amount of 5.0×1015 cm-2 in self-alignment with the double gate structure 113a using it as a mask. As a result, n-type high dose amount diffusion layers 118 are formed. The n-type diffusion layers 118 functions as source and drain regions of a MOSFET for a memory cell having single drain structure.
Next, as shown in FIG. 1C, the photoresist layer 119 is removed and a silicon oxide film is deposited on the whole substrate 111 by a low pressure CVD method. The silicon oxide film is etched back by an anisotropic plasma etching method, so that side wall insulating films 120a, 120b and 120c are formed on the side walls of the double gate structure 113a and gate electrodes 113b and 113c.
Next, as shown in FIG. 1D, a photoresist layer 121 is formed on the whole surface of the substrate 111. Then, the photoresist layer 121 is removed from the MOSFET formed region 102c for the logic circuit using a second photoresist mask, so that the memory cell formed region 102a and MOSFET formed region 102b for input protection remain covered with the photoresist layer 121. Subsequently, arsenic (As) ions are injected into the substrate 111 with acceleration energy of 70 KeV and dose amount of 3.0×1015 cm-2 in self-alignment with the gate electrode 113c and side wall insulating film 120c using them as a mask. As a result, n-type high dose amount diffusion layers 122 are formed while the low concentration n-type diffusion layers 116 remain. As a result, the source and drain regions having double drain structure, such as the graded junction structure or LDD structure are completed for the MOSFET for the logic circuit.
Finally, as shown in FIG. 1E, a photoresist layer 123 is formed on the whole surface of the substrate 111. Then, the photoresist layer 123 is removed from the MOSFET formed region 102b for input protection using a third photoresist mask, so that the memory cell formed region 102a and MOSFET formed region 102c for the logic circuit remain covered with the photoresist layer 123. Subsequently, phosphorus (P) ions are injected into the substrate 111 with acceleration energy of 70 KeV and dose amount of 1.0×1015 cm-2 in self-alignment with the gate electrode 113b and side wall insulating film 120b using them as a mask. As a result, n-type diffusion layers 124 of high dose amount are formed while the low concentration n-type diffusion layers 116 remain. A thermal treatment is performed after the ion injection. In this case, since the phosphorus ion has a greater diffusion coefficient than that of the arsenic ion, phosphorus ions diffuse from the n-type high dose amount diffusion layer to a portion under the side wall insulating film 120b so that the source and drain regions 124 having single drain structure are completed.
As described above, in the conventional method of manufacturing a semiconductor device with a non-volatile memory built therein, the MOSFET having a single drain structure for the memory cell and input protection and the MOSFET having the double drain structure for the logic circuit are formed through a process of injecting impurity into all the MOSFET in common with a low dose amount, and a process of individually injecting impurity into each of the MOSFETs with a high dose amount. Therefore, three photoresist masking processes and four ion injecting processes are required. As a result, it is difficult to reduce manufacturing cost of the semiconductor device, and production yield also is reduced.
SUMMARY OF THE INVENTION
The present invention is made from the above standpoint and has, as an object, to provide a method of manufacutring a semiconductor device having various types of MOSFETs with simple processes.
Another object of the present invention is to provide a method of manufacturing a semiconductor device wherein the method can be simplified based on the drain structure.
In order to achieve an aspect of the present invention, a method of manufacturing a semiconductor device is provided including on a single chip a non-volatile memory element, an input protecting element and a logic circuit element, comprising the steps of:
(a) forming gate structures of the non-volatile memory element, input protecting element and logic circuit element on a substrate of a first conductivity type;
(b) injecting an impurity of a second conductivity type in the substrate in self-alignment with the gate structure for the logic circuit element with a first dose amount to form source and drain regions for the logic circuit element;
(c) simultaneously injecting an impurity of the second conductivity type in the substrate in self-alignment with the gate structures for the non-volatile memory element and input protecting element to form source and drain regions for the non-volatile memory element and input protecting element; and
(d) injecting an impurity of the second conductivity type in parts of the source and drain regions of the logic circuit element apart from the gate structure with a second dose amount which is higher than the first dose amount.
The non-volatile memory element, input protecting element and logic circuit element may be a first type of MOSFET required to have capability of generation of hot electrons, a second type of MOSFET required to have resistance against electrostatic break down, and a third type of MOSFET required to have resistance against hot electrons, respectively.
In the above, a side wall insulating film is preferably formed on a side wall of each of the gate structures of the non-volatile memory element, input protecting element and logic circuit element before the injection for the logic circuit element is performed. If there is the side wall insulating film, the impurity of the second conductivity type is injected in the parts of the source and drain regions of the logic circuit element in alignment with the side wall insulating film and gate structure for the logic circuit element. In this case, the injection may be performed so as to form the source and drain regions so as to have a lightly doped drain (LDD) structure or a graded junction structure.
In order to form the source and drain regions of the non-volatile memory element and input protecting element, it is preferable that the impurity of the second conductive type is simultaneously injected in the substrate in self-alignment with the gate structures for the non-volatile memory element, input protecting element and logic circuit element with the first dose amount. The injection of phosphorus (P) ions is performed in step (b), and the injection of arsenic ions (As) is performed in steps (c) and (d), masking a region for the logic circuit element to be formed, by photoresist using a first mask in step (c) and masking regions for the non-volatile memory element and input protecting element to be formed, by photoresist using a second mask in step (d).
In order to achieve another aspect of the present invention, a method of manufacturing a semiconductor device including on a single chip a first type of metal-oxide-semiconductor field effect transistor (MOSFET) required to have capability of generation of hot electrons, a second type of MOSFET required to have resistance against electrostatic break down, and a third type of MOSFET required to have resistance against hot electrons, comprising the steps of:
(a) forming gate structures of the first to third types of MOSFETs on a substrate of a first conductivity type;
(b) forming the first and second types of MOSFETs using a first mask for masking the third type of MOSFET; and
(c) forming the third type of MOSFET using a second mask for masking the first and second types of MOSFETs.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A to 1E are schematic diagrams showing a conventional method of manufacturing a semiconductor device with a non-volatile memory built therein; and
FIGS. 2A to 2D are schematic diagrams showing a method of manufacturing a semiconductor device with a built-in non-volatile memory according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The method of manufacturing a semiconductor device with a non-volatile memory built therein, according to the present invention, will be described below with reference to the accompanying drawings.
First, referring to FIG. 2A, a p-type silicon substrate 11 is provided with a MOSFET formed region 2a for a memory cell such as an EPROM, a MOSFET formed region 2b for input protection, and a MOSFET formed region 2c for a logic circuit on the surface region. In the MOSFET formed region 2a for the memory cell, a double gate electrode structure 13a composed of a gate electrode 15a, an insulating film 14, and a control gate electrode 15b, is formed on the substrate 11 via a gate insulating film 12. In the MOSFET formed regions 2b and 2c, gate electrodes 13b and 13c of a single gate structure are formed on the substrate 11 via the gate insulating films 12. Note that films and regions for isolating elements are not shown because they are well known to a person skilled in the art. Thereafter, phosphorus (P) ions are injected into the substrate 11 with acceleration energy of 100 KeV and dose amount of 2 to 3×1013 cm-2 in self-alignment with the double gate structure 13a and single gate electrodes 13b and 13c using them as a mask to form n-type diffusion layers 116 of low dose amount.
Next, as shown in FIG. 2B, a photoresist layer 19 is formed on the whole surface of the substrate 11 and then the photoresist layer 19 is removed from the MOSFET formed regions 2a and 2b for the memory cell and input protection using a first photoresist mask. As a result, the MOSFET formed region 2c remains covered by the photoresist layer 19. Subsequently, arsenic (As) ions are injected into the substrate 11 with acceleration energy of 70 KeV and dose amount of 5.0×1015 cm-2 in self-alignment with the double gate structure 13a and single gate structure 13b using them as a mask. As a result, n-type diffusion layers 18 of high dose amount are formed while low dose amount n-type diffusion layers 16 remain under the layers 18. The n-type diffusion layers 18 function as source and drain regions of the MOSFETs having single drain structure. In the source and drain regions of the MOSFET formed region 2a, it is desirable that the impurity doping level is high because hot electrons can be effectively generated. Also, in the source and drain regions of the MOSFET formed region 2b, it is desirable that the impurity doping level is high because electrostatic charge can be effectively discharged. Thus, the actual impurity doping level is selected from the region where the region of impurity doping level desired for the MOSFET for a non-volatile memory cell and the region of impurity doping level desired for the MOSFET for input protection overlap.
Next, as shown in FIG. 2C, the photoresist layer 19 is removed and a silicon oxide film is deposited on the whole substrate 111 by a low pressure CVD method. The silicon oxide film is etched back by an anisotropic plasma etching method, so that side wall insulating films 20a, 20b and 20c are formed on the side walls of the double gate structure 13a and single gate electrodes 13b and 13c.
Next, as shown in FIG. 2D, a photoresist layer 21 is formed on the whole surface of the substrate 11. Then, the photoresist layer 21 is removed from the MOSFET formed region 2c for the logic circuit using a second photoresist mask, so that the MOSFET formed regions 2a and 2b remain covered with the photoresist layer 21. Subsequently, arsenic (As) ions are injected into the substrate 11 with acceleration energy of 70 KeV and dose amount of 3.0 to 5.0×1015 cm2-2 in self-alignment with the gate electrode 13c and side wall insulating film 20c using them as a mask. As a result, n-type diffusion layers 22 of high dose amount are formed at part of the n-type low dose amount diffusion layers 16. As a result, the source and drain regions having the double drain structure, such as the LDD or graded junction structure, can be completed for the MOSFET for the logic circuit. Therefore, generation of hot electrons can be suppressed.
As described above, according to the present invention, three types of MOSFETs having the single drain and double drain structure, such as the LDD or graded junction structure, can be formed by two photoresist mask forming processes and three ion injecting processes. Therefore, one photoresist mask forming and one ion injecting process can be omitted compared to the conventional method of the semiconductor device. Although the whole processes are simplified, the capability to generate effectively hot electrons, resistance against electrostatic break down, and suppression of generation of hot electrons can be satisfied in the MOSFET for a memory cell such as an EPROM, the MOSFET for input protection, and the MOSFET for logic circuit, respectively.

Claims (3)

What is claimed is:
1. A method of manufacturing a semiconductor device including on a single chip a non-volatile memory element, an input protecting element and a logic circuit element, comprising the steps of:
(a) forming a first gate of a first MOS transistor for said non-volatile memory element, a second gate of a second MOS transistor for said input protecting element and a third gate of a third MOS transistor for said logic circuit element on a substrate of a first conductivity type;
(b) simultaneously injecting a first impurity of a second conductivity type in said substrate in self-alignment with said first gate of said first MOS transistor for said non-volatile memory element, said second gate of said second MOS transistor for said input protecting element and said third gate of said third MOS transistor for said logic circuit element with a first dose amount;
(c) after said step (b) for a first mask for masking said third MOS transistor for said logic circuit element;
(d) after said step (c), injecting a second impurity of the second conductivity type in said substrate in self-alignment with said first and second gates of said first MOS transistor for said non-volatile memory and said second MOS transistor for said input protecting element with a second dose amount which is higher than said first dose amount so as to form source and drain regions of said first and second MOS transistors for said non-volatile memory element and input protecting element having single drain structure;
(e) removing said first mask, and forming first side wall insulating films on sidewalls of said third gate of said third MOS transistor for said logic circuit element;
(f) after said step (e) forming a second mask for masking said first and second MOS transistors for said non-volatile memory element and input protecting element; and
(g) injecting a third impurity of the second conductivity type in said source and drain regions of said third MOS transistor for said logic circuit in self-alignment with said third gate and said side wall insulating films with a bird dose amount which is higher than said first dose amount so as to form an LDD structure.
2. The method of manufacturing a semiconductor device according to claim 1, wherein said step (e) includes:
forming other side wall insulating film on side walls of said first and second gates of said first and second MOS transistors for said non-volatile memory element and input protecting element at the same time that said first side wall insulating films are formed on said third MOS transistor for said logic circuit element.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity injected in said step (b) is phosphors (P) and the impurity injected in said step (d) is arsenic (As).
US08/524,850 1994-09-14 1995-09-07 Method of manufacturing a semiconductor device having various types of MOSFETS Expired - Fee Related US5898006A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6244921A JP2600621B2 (en) 1994-09-14 1994-09-14 Method for manufacturing semiconductor device
JP6-244921 1994-09-14

Publications (1)

Publication Number Publication Date
US5898006A true US5898006A (en) 1999-04-27

Family

ID=17125961

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/524,850 Expired - Fee Related US5898006A (en) 1994-09-14 1995-09-07 Method of manufacturing a semiconductor device having various types of MOSFETS

Country Status (4)

Country Link
US (1) US5898006A (en)
JP (1) JP2600621B2 (en)
KR (1) KR100194008B1 (en)
CN (1) CN1052573C (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6124169A (en) * 1996-12-27 2000-09-26 Stmicroelectronics, S.R.L. Contact structure and associated process for production of semiconductor electronic devices and in particular nonvolatile EPROM and flash EPROM memories
US6144056A (en) * 1997-05-13 2000-11-07 Micron Technology, Inc. Methods of forming conductive lines, methods of forming insulative spacers over conductive line sidewalls, methods of forming memory circuitry, and memory circuitry
US6180494B1 (en) * 1999-03-11 2001-01-30 Micron Technology, Inc. Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
US6297102B1 (en) * 1999-10-01 2001-10-02 Taiwan Semiconductor Manufacturing Company Method of forming a surface implant region on a ROM cell using a PLDD implant
US6465831B1 (en) 1999-08-09 2002-10-15 Hyundai Electronics Industries Co., Ltd. MOSFET device and fabrication method thereof
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell
US20100090268A1 (en) * 2007-02-02 2010-04-15 Macronix International Co., Ltd. Semiconductor device and memory

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3144330B2 (en) * 1996-12-26 2001-03-12 日本電気株式会社 Semiconductor device
KR100344828B1 (en) * 1999-11-25 2002-07-20 주식회사 하이닉스반도체 Method for Manufacturing of semiconductor device
KR100388221B1 (en) * 2000-10-23 2003-06-19 주식회사 하이닉스반도체 Method of fabricating a semiconductor device
EP1742259A1 (en) * 2005-07-08 2007-01-10 STMicroelectronics S.r.l. Semiconductor power device with multiple drain structure and corresponding manufacturing process
JP5276282B2 (en) * 2007-06-08 2013-08-28 ローム株式会社 Manufacturing method of semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169470A (en) * 1986-01-22 1987-07-25 Hitachi Ltd Semiconductor integrated circuit device
US4745083A (en) * 1986-11-19 1988-05-17 Sprague Electric Company Method of making a fast IGFET
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
US5098855A (en) * 1984-05-23 1992-03-24 Hitachi, Ltd. Semiconductor device and method of producing the same
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766946B2 (en) * 1989-03-31 1995-07-19 株式会社東芝 Semiconductor device and manufacturing method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5098855A (en) * 1984-05-23 1992-03-24 Hitachi, Ltd. Semiconductor device and method of producing the same
JPS62169470A (en) * 1986-01-22 1987-07-25 Hitachi Ltd Semiconductor integrated circuit device
US4745083A (en) * 1986-11-19 1988-05-17 Sprague Electric Company Method of making a fast IGFET
US4775642A (en) * 1987-02-02 1988-10-04 Motorola, Inc. Modified source/drain implants in a double-poly non-volatile memory process
US4851361A (en) * 1988-02-04 1989-07-25 Atmel Corporation Fabrication process for EEPROMS with high voltage transistors
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6124169A (en) * 1996-12-27 2000-09-26 Stmicroelectronics, S.R.L. Contact structure and associated process for production of semiconductor electronic devices and in particular nonvolatile EPROM and flash EPROM memories
US6353241B1 (en) 1997-05-13 2002-03-05 Micron Technology, Inc. Memory circuitry with spaced conductive lines of different elevational thickness
US6144056A (en) * 1997-05-13 2000-11-07 Micron Technology, Inc. Methods of forming conductive lines, methods of forming insulative spacers over conductive line sidewalls, methods of forming memory circuitry, and memory circuitry
US6548339B2 (en) 1997-05-13 2003-04-15 Micron Technology, Inc. Methods of forming memory circuitry, and method of forming dynamic random access memory (DRAM) circuitry
US6258671B1 (en) * 1997-05-13 2001-07-10 Micron Technology, Inc. Methods of providing spacers over conductive line sidewalls, methods of forming sidewall spacers over etched line sidewalls, and methods of forming conductive lines
US20030203548A1 (en) * 1999-03-11 2003-10-30 Manning H. Montgomery Method of fabricating integrated circuitry, method of forming a local interconnect, and method of forming a conductive line.
US20040018710A1 (en) * 1999-03-11 2004-01-29 Manning H. Montgomery Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
US6391726B1 (en) 1999-03-11 2002-05-21 Micron Technology, Inc. Method of fabricating integrated circuitry
US7094636B2 (en) 1999-03-11 2006-08-22 Micron Technology, Inc. Method of forming a conductive line
US6225675B1 (en) 1999-03-11 2001-05-01 Micron Technology, Inc Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
US6610587B2 (en) 1999-03-11 2003-08-26 Micron Technology, Inc. Method of forming a local interconnect
US6638842B2 (en) 1999-03-11 2003-10-28 Micron Technology, Inc. Methods of fabricating integrated circuitry
US6180494B1 (en) * 1999-03-11 2001-01-30 Micron Technology, Inc. Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
US6982203B2 (en) 1999-03-11 2006-01-03 Micron Technology, Inc. Method of fabricating integrated circuitry
US20050098531A1 (en) * 1999-03-11 2005-05-12 Manning H. M. Method of forming conductive line
US20040115914A1 (en) * 1999-03-11 2004-06-17 Manning H. Montgomery Method of fabricating integrated circuitry, and method of forming a conductive line
US6803286B2 (en) 1999-03-11 2004-10-12 Micron Technology, Inc. Method of forming a local interconnect
US6797600B2 (en) 1999-03-11 2004-09-28 Micron Technology, Inc. Method of forming a local interconnect
US6649479B2 (en) 1999-08-09 2003-11-18 Hyundai Electronics Industries Co., Ltd. Method for fabricating MOSFET device
US6465831B1 (en) 1999-08-09 2002-10-15 Hyundai Electronics Industries Co., Ltd. MOSFET device and fabrication method thereof
US6297102B1 (en) * 1999-10-01 2001-10-02 Taiwan Semiconductor Manufacturing Company Method of forming a surface implant region on a ROM cell using a PLDD implant
US6773987B1 (en) * 2001-11-17 2004-08-10 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell
US7291546B1 (en) * 2001-11-17 2007-11-06 Altera Corporation Method and apparatus for reducing charge loss in a nonvolatile memory cell
US20100090268A1 (en) * 2007-02-02 2010-04-15 Macronix International Co., Ltd. Semiconductor device and memory
US8036027B2 (en) * 2007-02-02 2011-10-11 Macronix International Co., Ltd. Semiconductor device and memory

Also Published As

Publication number Publication date
CN1130806A (en) 1996-09-11
KR100194008B1 (en) 1999-06-15
KR960012474A (en) 1996-04-20
JPH0888288A (en) 1996-04-02
CN1052573C (en) 2000-05-17
JP2600621B2 (en) 1997-04-16

Similar Documents

Publication Publication Date Title
US6627928B2 (en) Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip
EP0164449B1 (en) Process for producing a semiconductor integrated circuit device including a misfet
US6518623B1 (en) Semiconductor device having a buried-channel MOS structure
US4566175A (en) Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations
US4845544A (en) Semiconductor integrated device having a field-effect transistor type memory cell array and peripheral circuitry structure
US5170232A (en) MOS field-effect transistor with sidewall spacers
KR900008207B1 (en) Semiconductor memory device
US5898006A (en) Method of manufacturing a semiconductor device having various types of MOSFETS
JP3227983B2 (en) Semiconductor device and manufacturing method thereof
KR0161474B1 (en) Method of manufacturing semiconductor memory device using cell plug ion injection
US5686338A (en) Process for fabricating high-resistance load resistors using dummy polysilicon in four-transistor SRAM devices
US5939757A (en) Semiconductor device having triple well structure
KR0147592B1 (en) Manufacturing method of mask-rom
JPH06350042A (en) Manufacture of transistor
EP1102319B1 (en) Process for manufacturing electronic devices comprising high-voltage MOS and EEPROM transistors
EP0414226B1 (en) MOS field-effect transistor with sidewall spacers
JPH10189771A (en) Semiconductor device and fabrication thereof
JP2933818B2 (en) Semiconductor device and manufacturing method thereof
JP3127951B2 (en) Semiconductor device and manufacturing method thereof
JPS62265765A (en) Semiconductor device and manufacture thereof
JP3117028B2 (en) Semiconductor storage device
JP3335876B2 (en) Semiconductor device manufacturing method and semiconductor device
JP2790167B2 (en) Semiconductor device and manufacturing method thereof
KR100224757B1 (en) Semiconductor device and method for manafacturing thereof
KR930008076B1 (en) Method of fabricating for sram

Legal Events

Date Code Title Description
AS Assignment

Owner name: NEC CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KUDOH, TAKAHARU;REEL/FRAME:007634/0030

Effective date: 19950823

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013798/0626

Effective date: 20021101

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20110427