JPS6155965A - Manufacture of nonvolatile semiconductor memory device - Google Patents
Manufacture of nonvolatile semiconductor memory deviceInfo
- Publication number
- JPS6155965A JPS6155965A JP59177436A JP17743684A JPS6155965A JP S6155965 A JPS6155965 A JP S6155965A JP 59177436 A JP59177436 A JP 59177436A JP 17743684 A JP17743684 A JP 17743684A JP S6155965 A JPS6155965 A JP S6155965A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- forming
- memory device
- semiconductor memory
- nonvolatile semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 8
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 2
- 239000011574 phosphorus Substances 0.000 claims 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000006104 solid solution Substances 0.000 abstract 2
- 239000010408 film Substances 0.000 description 44
- 239000010410 layer Substances 0.000 description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 150000004678 hydrides Chemical class 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- 229910019213 POCl3 Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は書き込み、消去特性の改善を図った不揮発性半
導体記憶装置の製造方法に関するものであるＯ
〔発明の技術的背景とその問題点〕
出願人は基板上の高濃度不純物層上べ形成した酸化膜と
３ｉ基板間の電気的なバリア・−イトが低下する現象を
利用して高性能のフローティングゲート型ＢＥＦＲＯＭ
を形成する方法を既に出願している（昭和５９年５月１
７日提出の特許類（６））。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a non-volatile semiconductor memory device with improved write and erase characteristics. [Technical Background of the Invention and Problems thereof] Application People have developed high-performance floating gate BEFROMs by taking advantage of the phenomenon in which the electrical barrier between the oxide film formed on the high concentration impurity layer on the substrate and the 3i substrate decreases.
An application has already been filed for a method of forming
Patents (6)) submitted on the 7th.
しかしながら良好な高濃度不純物層を形成する方法は知
られていなかった。However, a method for forming a good high concentration impurity layer has not been known.
本発明はバリアハイドを低下せしめる高濃度不純物層の
有効な形成方法を規定し、それを用いた高性能不揮発性
半導体記憶装置の製造方法を提供しようとするものであ
る。The present invention defines an effective method for forming a highly concentrated impurity layer that reduces barrier hydride, and provides a method for manufacturing a high-performance nonvolatile semiconductor memory device using the method.
本発明は上記目的を達成するため、フィールド酸化膜で
分離された第１導電屋シリコン基板の素子領域にゲート
酸化膜を形成する工程と、このゲート酸化膜の一部を除
去し、その基板露出部に不純物のピーク濃度が４００°
０以上の１ａ度における固溶限界を越えるようにイオン
注入した後１温度で熱アニールを行い高濃度不純物層を
形成する工程と、この高濃度不純物層上に熱酸化により
薄いシリコン酸化膜を形成する工程と、少なくともこの
薄いシリコン酸化膜上にフローティングゲート電極を形
成する工程とを具備したことを特徴とする。このように
して形成した薄いシリコン酸化膜とシリコン基板間の電
気的なＩくリア・・イトは１温度における熱アニールが
ない場合に比べ大きく低下しよシ低い書き込み／消去電
圧でブローティングゲート電極への電子の注入及びフロ
ーティングゲート電極からの電子の抽出を行うことがで
きるようになる。In order to achieve the above object, the present invention includes a step of forming a gate oxide film in an element region of a first conductive silicon substrate separated by a field oxide film, and removing a part of the gate oxide film to expose the substrate. The peak concentration of impurities at 400°
After ion implantation to exceed the solid solubility limit at 1A degree above 0 degrees, thermal annealing is performed at 1 temperature to form a highly concentrated impurity layer, and a thin silicon oxide film is formed on this highly concentrated impurity layer by thermal oxidation. The method is characterized by comprising a step of forming a floating gate electrode on at least this thin silicon oxide film. The electrical resistance between the thin silicon oxide film and the silicon substrate formed in this way is much lower than in the case without thermal annealing at one temperature. This makes it possible to inject electrons into the floating gate electrode and extract electrons from the floating gate electrode.
第１図（ａ）〜（鴫に本発明の＝実施例の製造工程図を
示す。Figures 1(a) to 1(a) show manufacturing process diagrams of embodiments of the present invention.
先ずｐｆＪ、シリコン基板１１上に・シツファ酸化［１
２を１００ＯＸ成長させ、次いでこの・くツファ酸化膜
１２上にシリコン窒化膜（８ｉ３Ｎ、、［：ナイトライ
ド）を３０００人堆積させた０次にこの８ｉ３Ｎ４膜゛
上に、素子領域を島状Ｋｆ＋離するためのフィールド酸
化膜形成予定位置が開口されたレジストパターンを形成
し、これをマスクに該３１３Ｎ４膜を選択的にエツチン
グして、フィールド酸化膜形成部分が開口されたＳｉ３
Ｎ４ｇパターン１３を形成した。次いで、レジストパタ
ーンを除去した後、前記Ｓ ｆ ３Ｎ４膜パターン１３
をマスクに、チャネルストッパ形成のため、Ｂを加速電
圧４Ｑ ＫｅＶ、ドーズ量５×１０１３ｃＩｎ２ノ条件
でイオン注入し、イオン注入理工４を形成した（第１図
（→図示）。First, Schiffer oxidation [1
Next, a silicon nitride film (8i3N, , [: nitride) was deposited for 3000 times on this Kf+ oxide film 12. Next, on this 8i3N4 film, an island-like Kf+ was formed in the element region. A resist pattern is formed with openings at the locations where the field oxide film is to be formed for separation, and the 313N4 film is selectively etched using this as a mask.
An N4g pattern 13 was formed. Then, after removing the resist pattern, the S f 3N4 film pattern 13 is removed.
Using this as a mask, B was ion-implanted under the conditions of an acceleration voltage of 4Q KeV and a dose of 5×10 13 cIn 2 to form a channel stopper, thereby forming an ion implantation process 4 (see FIG. 1).
ｉ １ｃ Ｈ２Ｏを用いた１０００℃のウェット酸化を
行い基板Ｕ露出面に酸化膜を成長させてフィールド酸化
１ｘ１５を形成した。その際、上記イオン注入層１４０
Ｂ原子は活性化されてフィールド酸化膜１５の下層に反
転防止層１６が形成された（第１図（ｂ）図示）。Wet oxidation at 1000° C. using i 1c H 2 O was performed to grow an oxide film on the exposed surface of the substrate U to form a field oxide 1×15. At that time, the ion implantation layer 140
The B atoms were activated to form an anti-inversion layer 16 under the field oxide film 15 (as shown in FIG. 1(b)).
次いで、ドライエツチングを行って、 Ｓｉ３Ｎ４膜″
ターン１３を除去し、次に弗化アンモニウム溶液により
リコン酸化膜上をエツチング除去した（第１図（Ｃ）図
示）。次いで、０２熱酸化を行って、基板露出面にゲー
ト酸化膜１７を５００Ｘ成長させた。本実施例では行わ
なかったが、ここで閾値コントロール用のイオン注入を
行っても良い。欠いで全面にレジストを塗布し、写真蝕
刻法により素子領域の書き込み／消去用３ｉ０２薄膜形
成予定部が開口されたレジストパターン１８を形成し、
次にこれをマスクに弗化アンモニウム溶液によりゲート
酸化膜１７をエツチング除去して、ゲート酸化膜ノ（タ
ーンを形成した。つぎにこれらレジスト／＜ターフ１８
、ゲート酸化膜パターン及びフィールド酸化膜１５を−
ｒ スフＡｓを加速電圧４Ｑ ＫｅＶ、ドーズｆｋ５×
１０１５ｃＩＩＬ２の条件でドレイン領域の一部とそれ
に連続するチャネル領域の一部１９′にイオン注入した
（第１図（ｄ）図示）０この時基板中のＡ８の濃度プロ
ファイルは図２のようＫな）、ピーク濃度は９００℃に
おける固溶限界を越えている。この後レジスト１８を除
去し、７％の酸素を含むＡｒ雰囲気中で９００’０．３
０分の熱アニールを行い、ドレイ／領域の一部とそれに
連続するチャネル領域の一部に高濃度不純物層１９を形
成した。この時形成される高濃度不純物拡欣層】９上の
約２ｏｏＸの酸化膜を剥離した後Ａ「で希釈１−た０２
中９００℃で熱酸化を行って、基板１】露出面ｗ厚す２
００Ｘ ｏｓｒｏｚ＊ｇｍｔ形成シタ。コノ５ｉ０２薄
膜加が７０−ティングゲート電極に対する電子の注入／
抽出を行う部分となる。次いで全面に多結晶シリコン膜
を４ｏｏｏＸ成長させた。次に１０００’Ｑ ｔｆ）
ＰＯＣｌ３雰囲気中で加分にわたシ熱処理を行って、多
結晶シリコン膜中にＰ拡散を行った後、レジストパター
ンを用いてこの多結晶シリコン、膜のエツチングを行い
、フローティングゲート電極２１を形成したつその際、
他に必要な周辺回路用ＭＯＳトランジスタのゲート電極
及び配線を同時にパターニングした（第１図（ｅ）図示
）。Next, dry etching is performed to form a Si3N4 film.
The turn 13 was removed, and then the silicon oxide film was etched away using an ammonium fluoride solution (as shown in FIG. 1(C)). Next, 02 thermal oxidation was performed to grow a gate oxide film 17 at a thickness of 500× on the exposed surface of the substrate. Although not performed in this embodiment, ion implantation for threshold control may be performed here. A resist is applied to the entire surface without any gaps, and a resist pattern 18 is formed in which a portion where a 3i02 thin film for writing/erasing in the element area is to be formed is opened by photolithography.
Next, using this as a mask, the gate oxide film 17 was removed by etching with an ammonium fluoride solution to form a gate oxide film turn.
, the gate oxide film pattern and the field oxide film 15 -
r Suff As acceleration voltage 4Q KeV, dose fk5×
Ions were implanted into a part of the drain region and a part 19' of the channel region continuous with it under the condition of 1015cIIL2 (as shown in Fig. 1(d)).At this time, the concentration profile of A8 in the substrate was as shown in Fig. 2. ), the peak concentration exceeds the solid solubility limit at 900°C. After that, the resist 18 was removed and the resist was heated at 90'0.3 in an Ar atmosphere containing 7% oxygen.
Thermal annealing was performed for 0 minutes to form a high concentration impurity layer 19 in a part of the drain/region and a part of the channel region continuous thereto. The high-concentration impurity diffusion layer formed at this time] After peeling off the oxide film of approximately 200X on 9, diluted with A
Thermal oxidation was carried out at 900°C in a medium temperature, and the substrate 1] exposed surface w thickness 2
00X osroz*gmt formation. KONO5i02 thin film addition 70-electron injection into gate electrode/
This is the part that performs extraction. Next, a 400X polycrystalline silicon film was grown on the entire surface. then 1000'Q tf)
After performing additional heat treatment in a POCl3 atmosphere to diffuse P into the polycrystalline silicon film, the polycrystalline silicon film was etched using a resist pattern to form a floating gate electrode 21. At that time,
Gate electrodes and wiring of other necessary peripheral circuit MOS transistors were patterned at the same time (as shown in FIG. 1(e)).
次いで、フローティングゲート電極２１とフィールド酸
化膜１５とをマスクにＡｓを加速電圧４０ ＫｅＶ、ド
ーズ量５ Ｘ １０”ｃｍ３０条件でイオン注入し、活
性化してノース、ドレイン領域η、２３を形成した（第
１図（ｆ）図示）。次に９００°０の０□雰囲気中で（
９）分、熱酸化を行い、フローティングゲート電極２１
の周囲Ｋ ８００Ｘのコントロールゲート電極用ゲート
酸化膜冴を形成した後、全面に多結晶シリコン膜を４０
００Ｘ成長させた。次いで９００°ＣのＰＯＣｌ３雰囲
気中で加分にわた）熱処理を行って、この多結晶シリコ
ン膜中にＰ拡散を行った後、全面にコントロールゲート
ｔｗ形成予定部を開口させたレジストパターンを形成し
、これをマスクに多結晶シリコン膜のエツチングを行っ
て、コントロールゲート電極５を形成した（第１図（ｇ
）図示）。Next, using the floating gate electrode 21 and the field oxide film 15 as a mask, As ions were implanted at an acceleration voltage of 40 KeV and a dose of 5 x 10" cm30, and activated to form the north and drain regions η, 23. 1(f) shown).Next, in a 0□ atmosphere at 900°0 (
9) minutes, thermal oxidation is performed to form the floating gate electrode 21.
After forming a gate oxide film for the control gate electrode with a peripheral K of 800X, a polycrystalline silicon film of 40X is deposited on the entire surface.
00X growth. Next, heat treatment was performed in a POCl3 atmosphere at 900° C. to diffuse P into this polycrystalline silicon film, and then a resist pattern was formed on the entire surface with an opening where the control gate TW was to be formed. Using this as a mask, the polycrystalline silicon film was etched to form a control gate electrode 5 (see Fig. 1 (g)).
).
以後は通常の工程に従って層間絶Ｒ膜訪を形成し、コン
タクトホールｎの開孔を行った後、金属配線材料を堆積
し、これをパターニングしてコンタクトホールｎを介し
てソース、ドレイン領域ｎ。Thereafter, an interlayer insulation film is formed according to the usual process, and a contact hole n is formed. Then, a metal wiring material is deposited and patterned to form a source and drain region n through the contact hole n.
乙に接続される配線路を形成し、次にバッフベージ舊ン
膜四を形成してＢＥＦＲＯＭを完成させた（第１図（ｈ
）図示）。BEFROM was completed by forming the wiring path connected to BEFROM, and then forming the buff page outer membrane 4 (see Figure 1 (h).
).
尚、本実施例で用いたＡｒはＮ２等の不活性気体に置き
換えても良い。またチャネル領域の不純物拡散層１９は
Ａｓをイオン注入することにより形成したが、これはＰ
をイオン注入するよう忙しても良く、また、ＡｓとＰ若
しくはこれとＢをイオン注入して形成するようＫしても
良い。高濃度不純物層１９の形成時に熱アニールを行わ
すに薄い酸化膜を形成した場合パリアノ・イトは３．ｏ
ｅＶまでしか下らない（低濃度基板上に酸化膜を形成し
た時のパリγ）・イトは３．２ ｅＶ ）のに対し１本
実施例のように熱アニールを行った後酸化膜を形成すれ
ばバリアハイドは２．７ｅＶ ｔで下る。又、高濃度不
純物層１９上では酸化膜の成長速度が低濃度の場合に比
べ速くなる。Note that Ar used in this example may be replaced with an inert gas such as N2. Furthermore, the impurity diffusion layer 19 in the channel region was formed by ion-implanting As;
Alternatively, it may be formed by ion-implanting As and P, or by ion-implanting As and B. If a thin oxide film is formed during thermal annealing when forming the high concentration impurity layer 19, the pallianoite will be 3. o
On the other hand, if the oxide film is formed after thermal annealing as in this example, it can be reduced to only 3.2 eV. Barrier hydride drops at 2.7 eV t. Further, the growth rate of the oxide film on the high concentration impurity layer 19 is faster than that on the low concentration impurity layer.
従って薄い酸化膜をその上に形成するには、酸化剤をＡ
ｒ等の不活性気体で希釈して酸化速度を遅くした方が良
い。さらく薄い酸化膜を形成する時の酸化剤として酸素
の替シに水蒸気を用いてもよく、その場合バリアハイド
の低下はよシ顕著になる。Therefore, in order to form a thin oxide film on it, the oxidizing agent should be
It is better to dilute with an inert gas such as r to slow down the oxidation rate. Steam may be used as an oxidizing agent to replace oxygen when forming a smooth and thin oxide film, and in that case, the reduction in barrier hydride becomes more significant.
以上詳述したように本発明によれば、従来より低いバリ
ア・・イトを持つ薄い酸化膜を有効に形成することがで
きる。従って従来よ）低い書き込み／消去電圧で７０−
ティングゲート電極への電子の注入及びフローティング
ゲート’ｇｉからの電子の抽出を行うことができるよう
になり、この低電圧動作化により、高電圧に対する複雑
な高耐圧構造は不要となって、その分、セルの高集積化
を図ることができるよう罠なる他、低電圧動作を可能し
たととによるＥＦｉＰＲＯＭセル破壊の抑制、確実で速
い書き込み／消去性能など素子の高信頼性、高性能化が
計れるなどの特徴を有する不揮発性半導体記憶装置の製
造方法を提供することが出来る。As detailed above, according to the present invention, it is possible to effectively form a thin oxide film having a lower barrier property than the conventional method. Therefore, at low write/erase voltage (conventional)
It is now possible to inject electrons into the floating gate electrode and extract electrons from the floating gate 'gi.This low-voltage operation eliminates the need for a complex high-voltage structure for high voltages. In addition to making it possible to achieve high cell integration, it also enables low-voltage operation, which suppresses EFiPROM cell destruction, and improves device reliability and performance through reliable and fast write/erase performance. It is possible to provide a method for manufacturing a nonvolatile semiconductor memory device having the following characteristics.
第１図（ａ）〜（ｈ）は本発明の一実施例を説明するた
めの製造工徨図、第２図は高濃度不純物層形成用のＡｓ
をイオン注入した直後のＡ８濃度の深さ方向のプロファ
イルを示す図である。
１１・・・ｐ型シリコン基板、１２・・・バッファ酸化
膜、１３・・・５ｉ３Ｎ４膜パターン、１４・・・イオ
ン注入層、１５・・・フィールド酸化膜、 １６・・
・反転防止層、１７・・・ゲート酸化膜、 １８・
・・レジストパターン、１９′・・・高濃度不純物層形
成領域、ル・・・高濃度不純物層、 （９）・・・Ｓｉ
Ｏ２薄膜、２１・・・７０−ティングゲート電極。
２２、Ｚ３・・・ソース、ドレイン領域、ム・・・コン
トロールゲート電極用ゲート酸化膜、δ・・・コントロ
ールゲー）ｍＷ、
託・・・層間絶縁膜、 ｎ・・・コンタクトホール、
路・・・配ｌ、 ２９・・・パッジページ覆
ン膜。
第１図
１’１
第１ｍｌ
り１
第２図
Ｑ、５ ＋、Ｏｄｅｐｔｈ（ｐ
ｍ）Figures 1 (a) to (h) are manufacturing process diagrams for explaining one embodiment of the present invention, and Figure 2 is a diagram of As for forming a high concentration impurity layer.
FIG. 3 is a diagram showing a profile of the A8 concentration in the depth direction immediately after ion implantation. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Buffer oxide film, 13... 5i3N4 film pattern, 14... Ion implantation layer, 15... Field oxide film, 16...
- Inversion prevention layer, 17... gate oxide film, 18.
...Resist pattern, 19'...High concentration impurity layer formation region, Ru...High concentration impurity layer, (9)...Si
O2 thin film, 21...70-ting gate electrode. 22, Z3...source, drain region, m...gate oxide film for control gate electrode, δ...control gate) mW, consignment...interlayer insulating film, n...contact hole,
Road...Arrangement l, 29...Pudge page covering membrane. Fig. 1 1'1 1 ml 1 Fig. 2 Q, 5 +, Odepth (p
m)
Claims (6)
膜を形成するとともに該絶縁膜で分離された島状の素子
領域を形成する工程と、前記素子領域にゲート酸化膜を
形成する工程と、このゲート酸化膜の一部を除去し、そ
の基板露出部に不純物のピーク濃度が４００℃以上の１
温度における固溶限界を越えるようにイオン注入した後
１温度で熱アニールを行い高濃度不純物層を形成する工
程と、この高濃度不純物層上に熱酸化により薄いシリコ
ン酸化膜を形成する工程と、少なくともこの薄いシリコ
ン酸化膜上にフローティングゲート電極を形成する工程
とを具備してなる不揮発性半導体記憶装置の製造方法。(1) A step of forming an insulating film for element isolation on the surface of a first conductivity type silicon substrate and forming an island-shaped element region separated by the insulating film, and a step of forming a gate oxide film in the element region. Then, a part of this gate oxide film is removed, and the exposed part of the substrate is exposed to a 1.
A step of forming a highly concentrated impurity layer by performing thermal annealing at one temperature after ion implantation at a temperature exceeding the solid solubility limit, and a step of forming a thin silicon oxide film by thermal oxidation on this highly concentrated impurity layer. A method of manufacturing a nonvolatile semiconductor memory device, comprising at least the step of forming a floating gate electrode on the thin silicon oxide film.
ン若しくは砒素とボロンいずれかの不純物をイオン注入
することにより形成することを特徴とする特許請求の範
囲第１項記載の不揮発性半導体記憶装置の製造方法。(2) The nonvolatile semiconductor memory device according to claim 1, wherein the high concentration impurity layer is formed by ion-implanting impurities of arsenic, phosphorus, arsenic and phosphorus, or arsenic and boron. manufacturing method.
の不活性気体で希釈した酸素中で行うことを特徴とする
特許請求の範囲第１項記載の不揮発性半導体記憶装置の
製造方法。(3) The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the thermal annealing at one temperature is performed in oxygen diluted with an inert gas such as Ar or N_2.
性気体で希釈した酸素中で形成することを特徴とする特
許請求の範囲第１項記載の不揮発性半導体記憶装置の製
造方法。(4) The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the thin silicon oxide film is formed in oxygen diluted with an inert gas such as Ar or N_2.
性気体で希釈した水蒸気中で形成することを特徴とする
特許請求の範囲第１項記載の不揮発性半導体記憶装置の
製造方法。(5) The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the thin silicon oxide film is formed in water vapor diluted with an inert gas such as Ar or N_2.
とを特徴とする特許請求の範囲第１項記載の不揮発性半
導体記憶装置の製造方法。(6) The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein channel ion implantation is performed after forming the gate oxide film.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59177436A JPS6155965A (en) | 1984-08-28 | 1984-08-28 | Manufacture of nonvolatile semiconductor memory device |
| KR1019850003150A KR900000204B1 (en) | 1984-08-28 | 1985-05-09 | Manufacture of novolatile semiconductor memory device |
| DE8585106028T DE3576245D1 (en) | 1984-05-17 | 1985-05-15 | METHOD FOR PRODUCING A NON-VOLATILE SEMICONDUCTOR EEPROM ELEMENT. |
| EP85106028A EP0164605B1 (en) | 1984-05-17 | 1985-05-15 | Method of manufacturing nonvolatile semiconductor eeprom device |
| US06/735,211 US4642881A (en) | 1984-05-17 | 1985-05-17 | Method of manufacturing nonvolatile semiconductor memory device by forming additional impurity doped region under the floating gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59177436A JPS6155965A (en) | 1984-08-28 | 1984-08-28 | Manufacture of nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6155965A true JPS6155965A (en) | 1986-03-20 |
Family
ID=16030909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59177436A Pending JPS6155965A (en) | 1984-05-17 | 1984-08-28 | Manufacture of nonvolatile semiconductor memory device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS6155965A (en) |
| KR (1) | KR900000204B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04211177A (en) * | 1990-03-08 | 1992-08-03 | Matsushita Electron Corp | Nonvolatile semiconductor storage device and its manufacture |
| JPH04287977A (en) * | 1991-01-24 | 1992-10-13 | Matsushita Electron Corp | Manufacture of nonvolatile semiconductor memory |
| US5208173A (en) * | 1990-03-20 | 1993-05-04 | Kabushiki Kaisha Toshiba | Method of manufacturing non-volatile semiconductor memory device |
-
1984
- 1984-08-28 JP JP59177436A patent/JPS6155965A/en active Pending
-
1985
- 1985-05-09 KR KR1019850003150A patent/KR900000204B1/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04211177A (en) * | 1990-03-08 | 1992-08-03 | Matsushita Electron Corp | Nonvolatile semiconductor storage device and its manufacture |
| US5208173A (en) * | 1990-03-20 | 1993-05-04 | Kabushiki Kaisha Toshiba | Method of manufacturing non-volatile semiconductor memory device |
| JPH04287977A (en) * | 1991-01-24 | 1992-10-13 | Matsushita Electron Corp | Manufacture of nonvolatile semiconductor memory |
Also Published As
| Publication number | Publication date |
|---|---|
| KR860002146A (en) | 1986-03-26 |
| KR900000204B1 (en) | 1990-01-23 |
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