JPH01108776A - Manufacture of semiconductor storage device - Google Patents
Manufacture of semiconductor storage deviceInfo
- Publication number
- JPH01108776A JPH01108776A JP26679787A JP26679787A JPH01108776A JP H01108776 A JPH01108776 A JP H01108776A JP 26679787 A JP26679787 A JP 26679787A JP 26679787 A JP26679787 A JP 26679787A JP H01108776 A JPH01108776 A JP H01108776A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- polycrystalline silicon
- tunneling
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 230000005641 tunneling Effects 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000001590 oxidative effect Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 13
- 239000002344 surface layer Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 238000002347 injection Methods 0.000 abstract description 6
- 239000007924 injection Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 238000001259 photo etching Methods 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 230000002542 deteriorative effect Effects 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 239000010410 layer Substances 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- -1 phosphorus ions Chemical class 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、フローティングゲート型の電界効果トランジ
スタからなる半導体記憶装置の記憶特性の高性能化をは
かるとともに、その記憶特性を安定して得ることができ
る製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Industrial Field of Application The present invention aims to improve the performance of the memory characteristics of a semiconductor memory device consisting of a floating gate field effect transistor, and can stably obtain the memory characteristics. This relates to a manufacturing method.
従来の技術
従来、電気的曹き込み消去が可能なROM(EEPRO
M;Electrically Erasable a
ndProgramable ROM)の1つとして、
トンネリング注入によシ書き込み消去を行うフローティ
ングゲート構造の半導体記憶装置がよく知られている。Conventional technology Conventionally, electrically eraseable ROM (EEPRO)
M;Electrically Erasable a
As one of the ndProgrammable ROM),
2. Description of the Related Art Semiconductor memory devices having a floating gate structure in which writing and erasing are performed by tunneling injection are well known.
このフローティングゲート型の半導体記憶装置は、拡散
層上に形成した薄い絶縁膜を介して電荷のトンネリング
を行い、絶縁膜上にさらに形成したフローティングゲー
ト電極に電荷を蓄積させ、トランジスタのしきい値電圧
を変化させて情報を記憶させることを原理としている。This floating gate type semiconductor memory device tunnels charges through a thin insulating film formed on a diffusion layer, accumulates charges in a floating gate electrode further formed on the insulating film, and raises the threshold voltage of the transistor. The principle is to memorize information by changing the
このようなフローティングゲート型の半導体記憶装置を
製作するための従来の製造方法の一例を第3図に示す。An example of a conventional manufacturing method for manufacturing such a floating gate type semiconductor memory device is shown in FIG.
第3図aで示すようにP型シリコン基板1の表面にゲー
ト絶縁膜となる厚い酸化膜1oを形成する。次いでイオ
ン注入法でN型拡散層3および4を形成したのち、酸化
シリコン膜1゜の一部を選択的゛に除去して開孔を形成
し、この中ヘトンネリング媒体となシうる薄い酸化シリ
コン膜11を形成する(第3図b)。次いで、第3図C
で示すようにフローティングゲート電極7.酸化シリコ
ン膜8およびコントロールゲート電極9を形成すること
によって(第3図C)、フローティング型の半導体記憶
装置が形成される。なお、トンネリング媒体となシうる
薄い酸化膜11は、通常のプログラム電圧(16〜20
v)で十分なトンネリング電流をうる目的から、その膜
厚を100八程度の極めて薄い厚さに設定する必要があ
る。一方、ゲート絶縁膜となる酸化シリコン膜1oは、
半導体基板からのトンネリング注入が起ることのない厚
さ(600八程度)に形成する必要がある。従って、従
来はまず、ゲート絶縁膜となる酸化シリコン膜10を形
成した後、トンネリング領域となる所定の部分に形成さ
れている酸化シリコン膜1oをエツチングして開孔を形
成し、この後開孔部分にトンネリング媒体となりうる薄
い酸化シリコン膜11を形成する方法が採られていた。As shown in FIG. 3a, a thick oxide film 1o which will become a gate insulating film is formed on the surface of a P-type silicon substrate 1. Next, after forming N-type diffusion layers 3 and 4 by ion implantation, a part of the silicon oxide film 1° is selectively removed to form an opening, and a thin oxide film that can serve as a tunneling medium is inserted into the opening. A silicon film 11 is formed (FIG. 3b). Next, Figure 3C
As shown in the floating gate electrode 7. By forming the silicon oxide film 8 and the control gate electrode 9 (FIG. 3C), a floating type semiconductor memory device is formed. Note that the thin oxide film 11, which can serve as a tunneling medium, has a normal programming voltage (16 to 20
For the purpose of obtaining a sufficient tunneling current in (v), it is necessary to set the film thickness to an extremely thin thickness of about 100%. On the other hand, the silicon oxide film 1o that becomes the gate insulating film is
It is necessary to form the layer to a thickness (approximately 60.0 mm) so that tunneling injection from the semiconductor substrate does not occur. Therefore, conventionally, after first forming a silicon oxide film 10 that will become a gate insulating film, the silicon oxide film 1o formed in a predetermined portion that will become a tunneling region is etched to form an opening. A method has been adopted in which a thin silicon oxide film 11 that can serve as a tunneling medium is formed in the portion.
発明が解決しようとする問題点
ところで、近年要求が高まシつつあるプログラム電圧の
低電圧化を実現するためには、トンネリング媒体となる
薄い酸化シリコン膜11の膜厚を100Å以下の極めて
薄い厚みに設定する必要があるが、従来の製造方法では
100Å以下の薄い酸化シリコン膜を制御性よく、安定
して形成することは非常に困難であシ、実用上の大きな
問題点となっている。さらに、酸化シリコン膜11の膜
厚を1oo八以下の極めて薄い厚さにすると、フローテ
ィングゲート電極7に蓄えられた電荷の放出速度が速く
なシ、記憶保持特性の悪化を招く不都合が生じる。Problems to be Solved by the Invention Incidentally, in order to realize a lower programming voltage, which has been increasing in demand in recent years, it is necessary to reduce the thickness of the thin silicon oxide film 11, which serves as the tunneling medium, to an extremely thin thickness of 100 Å or less. However, with conventional manufacturing methods, it is extremely difficult to stably form a thin silicon oxide film of 100 Å or less with good controllability, which poses a major practical problem. Furthermore, if the thickness of the silicon oxide film 11 is made extremely thin, such as 1.08 or less, the discharge speed of the charges stored in the floating gate electrode 7 will be fast, resulting in a disadvantage that the memory retention characteristics will be deteriorated.
本発明の目的は、フローティングゲート型半導体記憶装
置の記憶保持特性を悪化させることなくトンネリング注
入効率の増加をはかることができ、さらに、トンネリン
グ媒体となる絶縁膜を制御性よく安定して形成すること
ができる製造方法を提供することにある。An object of the present invention is to increase the tunneling injection efficiency without deteriorating the memory retention characteristics of a floating gate semiconductor memory device, and to form an insulating film that serves as a tunneling medium stably with good controllability. The objective is to provide a manufacturing method that allows for
問題点を解決するための手段
上記の目的を達成することができる本発明の製造方法は
一導電型半導体基板の表面層に反対導電型の第1および
第2の領域を離間させて形成する工程と、前記第1と第
2の領域にはさまれたチャネル領域上にゲート絶縁膜を
形成する工程と、前記第1もしくは第2領域の表面上の
所定の部分に前記半導体基板と反対導電型の不純物が添
加された多結晶シリコン膜を形成する工程と、同多結晶
シリコン膜の表面層を酸化してトンネリング媒体となる
絶縁膜を形成する工程と、前記ゲート絶縁膜およびトン
ネリング媒体となる絶縁膜の上にフローティング電極、
絶縁膜およびコントロール電極を積層形成する工程を備
えたことを特徴とするものである。Means for Solving the Problems The manufacturing method of the present invention which can achieve the above object includes a step of forming first and second regions of opposite conductivity types in a spaced manner on the surface layer of a semiconductor substrate of one conductivity type. forming a gate insulating film on a channel region sandwiched between the first and second regions; a step of forming a polycrystalline silicon film doped with impurities; a step of oxidizing the surface layer of the polycrystalline silicon film to form an insulating film that will become a tunneling medium; floating electrode on top of the membrane,
This method is characterized by comprising a step of laminating an insulating film and a control electrode.
作 用
本発明の製造方法では、多結晶シリコン膜上を酸化して
トンネリング媒体となる絶縁膜が形成され、しかも、こ
の絶縁膜は、通常のプログラム電圧(15〜20v)で
十分なトンネリング電流を得るのに必要とされる膜厚を
従来の膜厚(約100人)の6〜8倍(6oO〜aoo
人)厚くすることが可能となる。従って、トンネリング
媒体となる絶縁膜の膜厚の制御性が非常に高くなる。さ
らにトンネリング注入効率を増大させるためにトンネリ
ング媒体となる絶縁膜を薄くしたとしても、その膜厚は
従来の方法で実現が可能な膜厚(約100人)よシかな
シ厚くなるため、記憶保持特性の悪化は生じない。Function: In the manufacturing method of the present invention, an insulating film that becomes a tunneling medium is formed by oxidizing a polycrystalline silicon film, and this insulating film can generate a sufficient tunneling current at a normal programming voltage (15 to 20 V). The film thickness required to obtain
(person) can be made thicker. Therefore, the controllability of the thickness of the insulating film serving as the tunneling medium becomes extremely high. Furthermore, even if the insulating film that serves as the tunneling medium is made thinner in order to increase the tunneling injection efficiency, the film thickness will be much thicker than that which can be achieved using conventional methods (approximately 100 layers), so memory retention No deterioration of properties occurs.
また、チャネル上のゲート絶縁膜の厚さは通常600人
程度合用いるため、形成条件を適当に選べばゲート絶縁
膜とトンネリング媒体となる絶縁膜を同時に形成するこ
とも可能となる。Further, since the thickness of the gate insulating film on the channel is normally used by about 600 people, if the formation conditions are appropriately selected, it is possible to form the gate insulating film and the insulating film to serve as the tunneling medium at the same time.
なお、多結晶シリコン膜上を酸化して形成されたトンネ
リング媒体となる絶縁膜のトンネリング注入メカニズム
については詳らかでないが、絶縁膜の膜質および多結晶
シリコンの表面状態が大きく関係しているものと考えら
れる。Although the tunneling injection mechanism of the insulating film, which is formed by oxidizing the polycrystalline silicon film and becomes the tunneling medium, is not clear, it is thought that the quality of the insulating film and the surface condition of the polycrystalline silicon are largely related. It will be done.
実施例 本発明の具体的な実施例を図面を用いて説明する。Example Specific embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の製造方法の一実施例を示した工程順断
面図である。FIG. 1 is a step-by-step sectional view showing an embodiment of the manufacturing method of the present invention.
まず、第1図aに示すように、P型シリコン基板1の上
に、シランの熱分解反応に基づく減圧気相成長法によシ
多結晶シリコン膜を約1ooo人の厚さに形成し、さら
に、トンネリング領域となる所定の部分2のみを残すよ
うにエツチングする。First, as shown in FIG. 1a, a polycrystalline silicon film is formed on a P-type silicon substrate 1 to a thickness of about 100 mm by a low pressure vapor phase growth method based on a thermal decomposition reaction of silane. Further, etching is performed so as to leave only a predetermined portion 2 that will become a tunneling region.
次に、第1図すに示すように、イオン注入法により、選
択的にリンイオンを注入し、多結晶シリコン膜2の中に
リンをドープすると同時に、N型の拡散層3,4を形成
する。本実施例では、リンイオンがポリシリコン膜2の
中だけでなく、ポリシリコン膜2の直下のシリコン基板
中にも一部注入されるようにするため、イオン注入条件
を加速電圧100KeV、ドーズ量1×1o15c##
ニ設定してイオン注入を実施した。Next, as shown in FIG. 1, phosphorus ions are selectively implanted by an ion implantation method to dope phosphorus into the polycrystalline silicon film 2, and at the same time form N-type diffusion layers 3 and 4. . In this example, in order to implant phosphorus ions not only into the polysilicon film 2 but also into the silicon substrate directly under the polysilicon film 2, the ion implantation conditions were set to an acceleration voltage of 100 KeV and a dose of 1. ×1o15c##
Ion implantation was performed using the following settings.
次いで、第1図Cに示すように、通常の熱酸化法により
、シリコン基板1および多結晶シリコン膜の表面を酸化
し、チャネル領域上のゲート絶縁膜5と、多結晶シリコ
ン膜上のトンネリング絶縁膜6を形成する。本実施例で
は、1oOo℃の水蒸気雰囲気中で酸化させることによ
シ、厚さが500人のゲート絶縁膜6と厚さが700人
のトンネリング媒体となる絶縁膜6を同時に形成させた
。Next, as shown in FIG. 1C, the surfaces of the silicon substrate 1 and the polycrystalline silicon film are oxidized by a normal thermal oxidation method to form the gate insulating film 5 on the channel region and the tunneling insulating film on the polycrystalline silicon film. A film 6 is formed. In this example, a gate insulating film 6 with a thickness of 500 mm and an insulating film 6 serving as a tunneling medium with a thickness of 700 mm were simultaneously formed by oxidation in a steam atmosphere at 100° C.
次いで、ゲート絶縁膜6およびトンネリング媒体となる
絶縁膜6の上に、導電性の多結晶シリコン膜を気相成長
法によシ約5ooo人の厚さに形成したのち、周知のフ
ォトエツチング処理を施して多結晶シリコン膜よりなる
フローティングゲート電極7を形成し、さらにこの上に
通常の熱酸化法によシ、フローティングゲート電極上の
膜厚が約1oOo人となるように酸化シリコン膜を形成
し、こののち、導電性の多結晶シリコン膜を気相成長法
によシ約40oO人の厚さに形成し、これに周知のフォ
トエツチング処理を施して多結晶シリコン膜からなるコ
ントロールゲート電極9を形成することによって第1図
dに示すフローティングゲート型の半導体記憶装置が完
成する。Next, a conductive polycrystalline silicon film is formed on the gate insulating film 6 and the insulating film 6 serving as the tunneling medium to a thickness of about 500 mm by vapor phase growth, and then a well-known photoetching process is performed. A floating gate electrode 7 made of a polycrystalline silicon film is formed by applying a polycrystalline silicon film, and a silicon oxide film is further formed on the floating gate electrode by a normal thermal oxidation method so that the film thickness on the floating gate electrode is about 100 m. After this, a conductive polycrystalline silicon film is formed to a thickness of about 40 µm by vapor phase growth, and a well-known photoetching process is applied to this to form a control gate electrode 9 made of a polycrystalline silicon film. By forming this, a floating gate type semiconductor memory device shown in FIG. 1d is completed.
本実施例では、トンネリング媒体となる絶縁膜 46と
ゲート絶縁膜5を同時に形成する場合を示したが、第2
図に示すように、ゲート絶縁g5を形成した後、トンネ
リング領域となる所定の部分に開孔を形成し、この開孔
部分に多結晶シリコン膜2を埋め込み、この後、多結晶
シリコン膜上を酸化してトンネリング媒体となる絶縁膜
6を形成してもよいことは言うまでもない。In this embodiment, a case was shown in which the insulating film 46 serving as a tunneling medium and the gate insulating film 5 were formed at the same time.
As shown in the figure, after forming the gate insulator g5, an opening is formed in a predetermined portion that will become the tunneling region, a polycrystalline silicon film 2 is buried in this opening, and then a layer is formed on the polycrystalline silicon film. It goes without saying that the insulating film 6 may be oxidized to serve as a tunneling medium.
発明の詳細
な説明したところから明らかなように、本発明の製造方
法によれば、トンネリング媒体となる絶縁膜を従来に比
べて厚くすることが可能となシ、トンネリング媒体とな
る絶縁膜の膜厚の制御性が容易となる。さらに、プログ
ラム電圧の低電圧化を実現するためにトンネリング媒体
となる絶縁膜を薄くしたとしても、この膜厚が従来よシ
もかなシ厚くてよいため、記憶保持特性を確保したまま
で低電圧化を実現でき、フローティングゲート型の半導
体記憶装置の高性能化に大きく寄与する効果も奏される
。As is clear from the detailed description of the invention, according to the manufacturing method of the present invention, it is possible to make the insulating film that serves as the tunneling medium thicker than in the past. Thickness can be easily controlled. Furthermore, even if the insulating film that serves as the tunneling medium is made thinner in order to achieve a lower program voltage, this film can be thicker than before, so the voltage can be reduced while maintaining memory retention characteristics. It is also possible to achieve the effect of greatly contributing to improving the performance of floating gate type semiconductor memory devices.
第1図は本発明の半導体記憶装置の製造方法の一実施例
を示す工程順断面図、第2図は、本発明の製造方法の他
の実施例で形成される半導体記憶装置の構造を示す断面
図、第3図は従来の製造方法を説明するための工程順断
面図である。
1・・・・・・P型シリコン基板、2・・・・・・多結
晶膜、3゜4・・・・・・N型拡散層、5,8・・・・
・・酸化シリコン膜、6・・・・・・トンネリング媒体
となる絶縁膜、7・・・・・・フローティング電極、9
・・・・・・コントロール電極。
第1図
/−P型シリコン基板
9−・コントロール電極
第2図FIG. 1 is a step-by-step sectional view showing one embodiment of the method for manufacturing a semiconductor memory device of the present invention, and FIG. 2 shows the structure of a semiconductor memory device formed by another embodiment of the method for manufacturing a semiconductor memory device of the present invention. The cross-sectional views and FIG. 3 are step-by-step cross-sectional views for explaining the conventional manufacturing method. 1... P-type silicon substrate, 2... Polycrystalline film, 3° 4... N-type diffusion layer, 5, 8...
...Silicon oxide film, 6...Insulating film serving as a tunneling medium, 7...Floating electrode, 9
・・・・・・Control electrode. Figure 1/-P-type silicon substrate 9-/control electrode Figure 2
Claims (3)
び第2の領域を離間させて形成する工程と、前記第1と
第2の領域にはさまれたチャネル領域上にゲート絶縁膜
を形成する工程と、前記第1もしくは第2の領域の表面
上の所定の部分に前記半導体基板と反対導電型の不純物
が添加された多結晶シリコン膜を形成する工程と、前記
多結晶シリコン膜上にトンネリング媒体となる絶縁膜を
形成する工程と、前記ゲート絶縁膜およびトンネリング
媒体となる絶縁膜の上にフローティング電極、絶縁膜お
よびコントロール電極を積み重ねて形成する工程を備え
たことを特徴とする半導体記憶装置の製造方法。(1) A step of forming first and second regions of opposite conductivity types in a surface layer of a semiconductor of one conductivity type, and forming a gate insulator on a channel region sandwiched between the first and second regions. a step of forming a polycrystalline silicon film doped with an impurity of a conductivity type opposite to that of the semiconductor substrate at a predetermined portion on the surface of the first or second region; The present invention is characterized by comprising a step of forming an insulating film to serve as a tunneling medium on the film, and a step of stacking and forming a floating electrode, an insulating film, and a control electrode on the gate insulating film and the insulating film to serve as a tunneling medium. A method for manufacturing a semiconductor memory device.
膜を酸化して形成されることを特徴とする特許請求の範
囲第1項に記載の半導体記憶装置の製造方法。(2) The method for manufacturing a semiconductor memory device according to claim 1, wherein the insulating film serving as the tunneling medium is formed by oxidizing a polycrystalline silicon film.
膜が同時に形成されることを特徴とする特許請求の範囲
第1項に記載の半導体記憶装置の製造方法。(3) The method for manufacturing a semiconductor memory device according to claim 1, wherein a gate insulating film and an insulating film serving as a tunneling medium are formed at the same time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26679787A JPH01108776A (en) | 1987-10-21 | 1987-10-21 | Manufacture of semiconductor storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26679787A JPH01108776A (en) | 1987-10-21 | 1987-10-21 | Manufacture of semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
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JPH01108776A true JPH01108776A (en) | 1989-04-26 |
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ID=17435819
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP26679787A Pending JPH01108776A (en) | 1987-10-21 | 1987-10-21 | Manufacture of semiconductor storage device |
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JP (1) | JPH01108776A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013168576A (en) * | 2012-02-16 | 2013-08-29 | Rohm Co Ltd | Semiconductor device and semiconductor device manufacturing method |
-
1987
- 1987-10-21 JP JP26679787A patent/JPH01108776A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013168576A (en) * | 2012-02-16 | 2013-08-29 | Rohm Co Ltd | Semiconductor device and semiconductor device manufacturing method |
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