JPH02277269A - Manufacture of nonvolatile memory - Google Patents

Manufacture of nonvolatile memory

Info

Publication number
JPH02277269A
JPH02277269A JP9738789A JP9738789A JPH02277269A JP H02277269 A JPH02277269 A JP H02277269A JP 9738789 A JP9738789 A JP 9738789A JP 9738789 A JP9738789 A JP 9738789A JP H02277269 A JPH02277269 A JP H02277269A
Authority
JP
Japan
Prior art keywords
film
oxide film
silicon oxide
silicon nitride
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9738789A
Other languages
Japanese (ja)
Inventor
Kazuo Sato
和夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP9738789A priority Critical patent/JPH02277269A/en
Publication of JPH02277269A publication Critical patent/JPH02277269A/en
Pending legal-status Critical Current

Links

Landscapes

  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To reduce deterioration of memory characteristics by forming a tunneling insulating film, and then providing a step of implanting hydrogen ions. CONSTITUTION:A silicon oxide film 2, a silicon nitride film 3, and a field thermal oxide film 4 are formed on a substrate 1, the films 3, 4 are sequentially etched, a silicon oxide film 5 is then formed, ion implanted with photoresist 6 as a mask, and N-type diffused layers 8, 9 are formed. Then, the photoresist 6 is removed, the part of the film 5 on the layer 9 is opened, and a thin silicon nitride film 10 to become a tunneling medium is formed. Thereafter, a floating gate 11, a silicon oxide film 12, a control gate electrode 13, N-type diffused layers 14, 15 reformed, a silicon oxide film 16 are vapor grown on a whole surface, and hydrogen ions 17 are then implanted to the whole surface. Thus, the hydrogen content of the film 10 is increased to prevent the deterioration of memory holding characteristic.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、フローティングゲート構造を有する、電界効
果トランジスタからなる記憶保持特性の優れた不揮発性
メモリ装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a nonvolatile memory device having excellent memory retention characteristics and comprising a field effect transistor having a floating gate structure.

(従来の技術) 従来、電気的に書込み消去するE E P ROM(E
lectrically Erasable and 
Programable ROM)の一つに、トンネリ
ング注入によって書込み、消去が可能なフローティング
ゲート(以下、Fゲートと記す)構造の不揮発性メモリ
装置が知られている。その装置は、半導体基板側から薄
い酸化シリコン膜を介して電荷をトンネリングさせ、絶
縁膜上のFゲート電極に電荷を蓄積させ、トランジスタ
のしきい値電圧を変化させることによって。
(Prior Art) Conventionally, electrically written and erased EEPROM (E
Electrically Erasable and
2. Description of the Related Art A nonvolatile memory device having a floating gate (hereinafter referred to as F gate) structure that can be written and erased by tunneling injection is known as one type of programmable ROM (ROM). This device tunnels charges from the semiconductor substrate side through a thin silicon oxide film, accumulates charges in the F gate electrode on the insulating film, and changes the threshold voltage of the transistor.

情報を記憶させることを原理としている。The principle is to memorize information.

第3図は、そのような従来のFゲート構造の不揮発性メ
モリの代表的な例を示す断面図である。
FIG. 3 is a cross-sectional view showing a typical example of such a conventional F-gate structure nonvolatile memory.

31はP型シリコン基板で、その中にN型拡散層からな
るドレイン領域32.ソース領域33およびそれを跨い
で形成された酸化シリコン膜34を有し、この膜のドレ
イン領域32の上部に接する一部分は開孔されて、トン
ネリング媒体となる薄い酸化シリコン膜35が全面に形
成されており、この酸化シリコン膜35の上面にFゲー
ト電極36.酸化シリコン膜37およびコン1−ロール
ゲート電極38が順次積層された構造を有している。
Reference numeral 31 denotes a P-type silicon substrate, in which a drain region 32 made of an N-type diffusion layer is formed. It has a source region 33 and a silicon oxide film 34 formed over it, and a part of this film that contacts the upper part of the drain region 32 is opened to form a thin silicon oxide film 35 that becomes a tunneling medium over the entire surface. An F gate electrode 36. is provided on the upper surface of this silicon oxide film 35. It has a structure in which a silicon oxide film 37 and a control gate electrode 38 are sequentially laminated.

近年、上述のように構成される不揮発性メモリ装置にお
いて、プログラミング電圧の低電圧化、あるいは書換え
に伴うメモリ特性の劣化を低減させるために、上記トン
ネリング膜となる薄い酸化シリコン膜(トンネリング絶
縁膜)35に代えて、薄い窒化シリコン膜、または酸化
シリコン膜−窒化シリコン膜の二層膜、または酸化シリ
コン膜−窒化シリコン暎−酸化シリコン膜の三層膜、あ
るいはオキシナイトライド膜等の窒化シリコン膜系のト
ンネリング絶縁股を用いることが提案されている。
In recent years, in nonvolatile memory devices configured as described above, thin silicon oxide films (tunneling insulating films), which serve as the tunneling films, have been developed in order to lower the programming voltage or to reduce deterioration of memory characteristics due to rewriting. In place of 35, a thin silicon nitride film, a two-layer film of silicon oxide film-silicon nitride film, a three-layer film of silicon oxide film-silicon nitride film-silicon oxide film, or a silicon nitride film such as an oxynitride film It has been proposed to use a tunneling insulation crotch system.

しかしながら、窒化シリコン膜系のトンネリング絶縁膜
を使用する不揮発性メモリ装置においては、通常、Fゲ
ート電極36およびコントロールゲート電極38にポリ
シリコン膜等の高融点金属を使用するため、トンネリン
グ絶縁膜の形成後に900℃ないしtooo℃程度の高
熱の処理を必ず必要とする。従って、窒化シリコン膜系
のトンネリング絶縁囚の膜質は著しく劣化し、記憶保持
特性が悪化することになる。
However, in a nonvolatile memory device that uses a silicon nitride film-based tunneling insulating film, a high melting point metal such as a polysilicon film is usually used for the F gate electrode 36 and the control gate electrode 38, so the formation of the tunneling insulating film Afterwards, high heat treatment of about 900°C to too much°C is always required. Therefore, the film quality of the silicon nitride film-based tunneling insulator deteriorates significantly, resulting in deterioration of memory retention characteristics.

(発明が解決しようとする課題) 本発明は上述の従来の問題点に鑑み、Fゲート構造の不
揮発性メモリ装置における記憶保持特性を悪化させるこ
となく、プログラム電圧の低電圧化、書換えに伴うメモ
リ特性劣化の低減を可能とする不揮発性メモリ装置の提
供を目的とする。
(Problems to be Solved by the Invention) In view of the above-mentioned conventional problems, the present invention aims to reduce the programming voltage and reduce the memory capacity associated with rewriting without deteriorating the memory retention characteristics of a nonvolatile memory device with an F-gate structure. An object of the present invention is to provide a nonvolatile memory device that can reduce characteristic deterioration.

(a題を解決するための手段) 上述の記憶保持特性の悪化は、窒化シリコン膜成長後の
膜質に強く依存し、特に窒化シリコン膜に含まれる水素
、特に5i−It結合の含有量に関係があり、5i−H
結合が多い窒化シリコン膜は、成長温度以上の高熱処理
により5i−H結合の数が少なくなって5不安定なトラ
ップが付加増大して、窒化シリコン膜に電気伝導度を増
大させ、記憶保持特性が低下することが本発明者の究明
によってわかった。すなわち、窒化シリコン膜形成後の
高熱処理による記憶保持特性の悪化は、主として窒化シ
リコン膜形成時の水素含有量に大きく依存する。
(Means for solving problem a) The deterioration of the memory retention characteristics described above strongly depends on the film quality after the silicon nitride film is grown, and is particularly related to the content of hydrogen contained in the silicon nitride film, especially the content of 5i-It bonds. There is 5i-H
In silicon nitride films with many bonds, the number of 5i-H bonds decreases due to high heat treatment above the growth temperature, and 5 unstable traps are added and increased, increasing the electrical conductivity of the silicon nitride film and improving memory retention properties. As a result of investigation by the present inventors, it was found that the That is, deterioration in memory retention characteristics due to high heat treatment after forming a silicon nitride film largely depends on the hydrogen content at the time of forming the silicon nitride film.

よって、本発明は上記の目的を、−導電型半導体基板内
に少なくとも窒化シリコン股を含むトンネリング絶縁膜
を形成して、その上面にFゲート電極を形成する工程と
、その電極上に絶縁膜を介してコントロールゲート電極
を形成する工程とを含む不揮発性メモリ装置の製造方法
において、上記トンネリング絶縁膜を形成した後に水素
イオンを注入する工程を設けることによって達成する。
Therefore, the present invention achieves the above-mentioned object by: - forming a tunneling insulating film including at least a silicon nitride layer in a conductive type semiconductor substrate, forming an F gate electrode on the upper surface thereof, and forming an insulating film on the electrode; This is achieved by providing a step of implanting hydrogen ions after forming the tunneling insulating film in a method of manufacturing a nonvolatile memory device including a step of forming a control gate electrode through the tunneling insulating film.

(作 用) 本発明によれば、水素イオンの注入により、窒化シリコ
ン膜の水素含有量を増大させ、電気伝導度を小さくさせ
、記憶保持特性が悪化しない優れた記憶保持特性を得る
ことができる。
(Function) According to the present invention, by implanting hydrogen ions, the hydrogen content of the silicon nitride film is increased, the electrical conductivity is reduced, and excellent memory retention characteristics can be obtained without deterioration of memory retention characteristics. .

また、Fゲート構造の不揮発性メモリ装置は、トンネリ
ング絶縁膜の形成後、通常、ポリシリコン膜のような高
融点金属からなるFゲート電極を形成し、さらにソース
、ドレインあるいは表面保護膜の形成等を行うが、その
場合のソース、ドレインの押込み2表面保護膜の緻密化
等のために、トンネリング絶縁膜の窒化シリコン膜の成
長温度以上の高温の処理を行うので、水素イオン注入は
高温処理後に行う必要があったが、本発明は水素イオン
注入後の活性化を窒化シリコン膜成長温度以下の温度で
処理するので、さらに効果を得ることができる。
In addition, in a nonvolatile memory device with an F-gate structure, after forming a tunneling insulating film, an F-gate electrode made of a high-melting point metal such as a polysilicon film is usually formed, and then a source, drain, or surface protection film is formed. However, in order to indent the source and drain 2 and make the surface protective film denser, high-temperature treatment is performed at a temperature higher than the growth temperature of the silicon nitride film of the tunneling insulating film, so hydrogen ion implantation is performed after the high-temperature treatment. However, since the present invention performs activation after hydrogen ion implantation at a temperature lower than the silicon nitride film growth temperature, further effects can be obtained.

(実施例) 以下、本発明を@1図に示す本発明の一実施例の工程断
面図によって説明する。
(Example) Hereinafter, the present invention will be explained with reference to a process sectional view of an example of the present invention shown in Figure @1.

はじめに、P型シリコン栽板1の全面に酸化シリコン膜
2を500人の厚さに形成し、さらに窒化シリコン股3
を1000人形成して、素子分歴のため所定部分をフォ
トエツチングする〔図(a)〕。
First, a silicon oxide film 2 was formed on the entire surface of a P-type silicon planting board 1 to a thickness of 500 mm, and then a silicon nitride film 3 was formed.
A total of 1,000 samples are formed, and predetermined portions are photo-etched for element history [Figure (a)].

次いで、通常の熱酸化によってフィールド熱酸化膜4を
1μm程度形成し〔図(b)〕、次に、図(c)のよう
に、窒化シリコン膜3.フィールド熱酸化膜4を順次エ
ツチングしてがら、通常の方法で酸化シリコン膵5を5
00人形成し、その後、フォトレジスト6をマスクにリ
ンイオン7を注入し、N型拡散層8,9を100 k 
eV、I X 101gcm −” (7)条件で形成
する。
Next, a field thermal oxide film 4 with a thickness of about 1 μm is formed by normal thermal oxidation [Figure (b)], and then, as shown in Figure (c), a silicon nitride film 3. While sequentially etching the field thermal oxide film 4, the silicon oxide pancreas 5 is etched using the usual method.
After that, using photoresist 6 as a mask, phosphorus ions 7 are implanted to form N-type diffusion layers 8 and 9 at 100 k.
eV, I x 101 gcm −” (7).

次に、図(d)のように、フォトレジスト6を除去し、
N型拡散層9上の酸化シリコン膜5の一部を開孔して、
これにジクロロシラン(SiH□CO,)とアンモニア
(NH3)の化学反応に基づく減圧気相成長法によって
、トンネリング媒体となる薄い窒化シリコン膜10を、
NH3/ 5iH2CO2” 5.750℃の条件で1
20人形成させる。
Next, as shown in figure (d), the photoresist 6 is removed,
A part of the silicon oxide film 5 on the N-type diffusion layer 9 is opened,
A thin silicon nitride film 10, which will serve as a tunneling medium, is deposited on this layer by a low pressure vapor phase growth method based on a chemical reaction between dichlorosilane (SiH□CO,) and ammonia (NH3).
NH3/ 5iH2CO2” 5.1 at 750℃
Have 20 people form.

次に、図(e)のように、窒化シリコン膜10上に、リ
ンを約2 ×10211.、、−3ドープしたポリシリ
コン膜を気相成長法によって約5000人形成させ、そ
の後。
Next, as shown in Figure (e), approximately 2×10211. About 5,000 -3 doped polysilicon films were formed by vapor phase growth, and then.

フォトエツチングによりポリシリコン膜によるFゲート
電極11を形成し1次に、熱酸化法によって酸化シリコ
ン膜12を上記Fゲート電極11上で約400人となる
ように形成する。その後、リンを約2 X t o 2
0■−7ドープしたポリシリコン膜を約4000人気相
成長させ、さらに、ポリシリコンからなるコントロール
ゲート電極13をフォトエツチングによって形成し、こ
の膜とフィールド熱酸化膜4をマスクにして砒素イオン
を約50 k eVで4X101sC1l+−2打込み
、ソース、ドレイン領域のN型拡散層14、15を形成
する。
An F gate electrode 11 made of a polysilicon film is formed by photoetching, and then a silicon oxide film 12 is formed on the F gate electrode 11 to a thickness of approximately 400 by thermal oxidation. Then add about 2 X t o 2 phosphorus
A polysilicon film doped with 0-7 is grown in about 4,000 phases, and a control gate electrode 13 made of polysilicon is formed by photoetching. Using this film and the field thermal oxide film 4 as a mask, arsenic ions are etched into the film. 4×101sC11+-2 implantation is performed at 50 keV to form N-type diffusion layers 14 and 15 in the source and drain regions.

次に、図(f)のように、酸化シリコン膜16の全面に
気相成長させた後、ソース、ドレインの活性化と酸化シ
リコン膜16の緻密化のために、tooo℃のN2雰囲
気中で熱処理する。その後、水素イオン17を全面に注
入する。
Next, as shown in Figure (f), after vapor phase growth is performed on the entire surface of the silicon oxide film 16, in order to activate the source and drain and to make the silicon oxide film 16 dense, Heat treatment. Thereafter, hydrogen ions 17 are implanted into the entire surface.

この実施例では水素イオン種としてH%イオンを用い、
加速エネルギー10keV、注入量5X10”■−2と
した。さらに、注入イオンの活性化のため。
In this example, H% ions were used as the hydrogen ion species,
The acceleration energy was 10 keV and the implantation amount was 5 x 10'' -2.Furthermore, the implanted ions were activated.

700℃の窒化シリコン膜の成長温度以下の温度で。At a temperature below the silicon nitride film growth temperature of 700°C.

N2雰囲気中で20分熱処理する。Heat treatment is performed in a N2 atmosphere for 20 minutes.

最後に1図(g)のように、ソース、ドレイン領域を構
成するN重拡散Nj14,15に電極を設けるため、酸
化シリコン膜16にフォトエツチングでコンタクト孔を
開孔し、アルミ電極18を形成することによって、Fゲ
ート型の不揮発性メモリ装置が形成される。
Finally, as shown in Figure 1(g), in order to provide electrodes for the N-heavy diffusions Nj 14 and 15 that constitute the source and drain regions, contact holes are formed in the silicon oxide film 16 by photoetching, and aluminum electrodes 18 are formed. By doing so, an F-gate type nonvolatile memory device is formed.

第2図は、上述のように形成したFゲート型の不揮発性
メモリ装置の記憶保持特性を示す図で、縦軸はしきい値
電圧、横軸は記憶保持時間を表わしており、実線aが本
発明による記憶保持特性である。これを破線すで示す従
来方法による特性と比べ、明らかに本発明の場合の特性
が優れていることがわかる。
FIG. 2 is a diagram showing the memory retention characteristics of the F-gate type nonvolatile memory device formed as described above, in which the vertical axis represents the threshold voltage, the horizontal axis represents the memory retention time, and the solid line a represents 1 is a memory retention characteristic according to the present invention. It can be seen that the characteristics of the present invention are clearly superior to those of the conventional method, which is indicated by the broken line.

以上、本発明をトンネリング絶縁膜に単層の窒化シリコ
ン膜を用いて詳細に説明したが、これは窒化シリコン膜
−酸化シリコン膜の二層膜、あるいは酸化シリコン膜−
窒化シリコン膜−酸化シリコン膜の三層膜、またはオキ
シナイトライド膜の窒化シリコン膜系の絶縁膜を使用し
ても同様な結果が得られることはいうまでもない。
The present invention has been described in detail above using a single layer silicon nitride film as the tunneling insulating film, but this invention is not limited to a double layer film of a silicon nitride film and a silicon oxide film, or a silicon oxide film and a silicon oxide film.
It goes without saying that similar results can be obtained by using a three-layer film of a silicon nitride film and a silicon oxide film, or a silicon nitride film-based insulating film of an oxynitride film.

(発明の効果) 以上の説明から明らかなように1本発明は、記憶保持特
性を悪化させることなく、プログラミング電圧の低電圧
化、書換えに伴うメモリ特性劣化の低減化が実現され、
Fゲート型の不揮発性メモリ装置の高性能化に大きく寄
与する。
(Effects of the Invention) As is clear from the above description, the present invention realizes lower programming voltage and reduction of deterioration of memory characteristics due to rewriting without deteriorating memory retention characteristics.
This greatly contributes to improving the performance of F-gate type nonvolatile memory devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を説明する工程断面図、第2
図はその特性を示す図、第3図は従来例の構造断面図で
ある。 1・・・P型シリコン基板、 2.5.12.16・・
・酸化シリコン膜、3.10・・・窒化シリコン膜、 
4・・・フィールド熱酸化膜、 6・・・フォトレジス
ト、  7・・・リンイオン、  819.14.15
・・・N型拡散層、 11・・・フローティングゲート
電極(Fゲート電極)、 】3・・・コントロールゲー
ト電極、 17・・・水素イオン、18・・・アルミ電
極。 特許出願人 松下電子工業株式会社 第 図 5ffi多己イを二′/1JJyRり(第 図 第 図 14N型拡散層 第 図 保持片開 (hr)
Fig. 1 is a process sectional view explaining one embodiment of the present invention;
The figure shows its characteristics, and FIG. 3 is a cross-sectional view of the structure of a conventional example. 1...P-type silicon substrate, 2.5.12.16...
・Silicon oxide film, 3.10... silicon nitride film,
4... Field thermal oxide film, 6... Photoresist, 7... Phosphorus ion, 819.14.15
... N type diffusion layer, 11... Floating gate electrode (F gate electrode), ]3... Control gate electrode, 17... Hydrogen ion, 18... Aluminum electrode. Patent applicant: Matsushita Electronics Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 一導電型半導体基板内に少なくとも窒化シリコン膜を含
むトンネリング絶縁膜を形成して、その上面にフローテ
ィングゲート電極を形成する工程と、その電極上に絶縁
膜を介してコントロールゲート電極を形成する工程とを
含む不揮発性メモリ装置の製造方法において、上記トン
ネリング絶縁膜を形成した後に水素イオンを注入させる
工程を有することを特徴とする不揮発性メモリ装置の製
造方法。
A step of forming a tunneling insulating film containing at least a silicon nitride film in a semiconductor substrate of one conductivity type, forming a floating gate electrode on the upper surface of the tunneling insulating film, and a step of forming a control gate electrode on the electrode via an insulating film. A method of manufacturing a non-volatile memory device comprising the step of implanting hydrogen ions after forming the tunneling insulating film.
JP9738789A 1989-04-19 1989-04-19 Manufacture of nonvolatile memory Pending JPH02277269A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9738789A JPH02277269A (en) 1989-04-19 1989-04-19 Manufacture of nonvolatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9738789A JPH02277269A (en) 1989-04-19 1989-04-19 Manufacture of nonvolatile memory

Publications (1)

Publication Number Publication Date
JPH02277269A true JPH02277269A (en) 1990-11-13

Family

ID=14191105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9738789A Pending JPH02277269A (en) 1989-04-19 1989-04-19 Manufacture of nonvolatile memory

Country Status (1)

Country Link
JP (1) JPH02277269A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252270B1 (en) 1997-04-28 2001-06-26 Agere Systems Guardian Corp. Increased cycle specification for floating-gate and method of manufacture thereof
US6309938B1 (en) 1997-04-28 2001-10-30 Agere Systems Guardian Corp. Deuterated bipolar transistor and method of manufacture thereof
US6365511B1 (en) 1999-06-03 2002-04-02 Agere Systems Guardian Corp. Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability
US7256449B2 (en) 2003-05-20 2007-08-14 Samsung Electronics, Co., Ltd. EEPROM device for increasing a coupling ratio and fabrication method thereof
CN100401521C (en) * 2003-05-20 2008-07-09 三星电子株式会社 EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6252270B1 (en) 1997-04-28 2001-06-26 Agere Systems Guardian Corp. Increased cycle specification for floating-gate and method of manufacture thereof
US6309938B1 (en) 1997-04-28 2001-10-30 Agere Systems Guardian Corp. Deuterated bipolar transistor and method of manufacture thereof
US6365511B1 (en) 1999-06-03 2002-04-02 Agere Systems Guardian Corp. Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability
US7256449B2 (en) 2003-05-20 2007-08-14 Samsung Electronics, Co., Ltd. EEPROM device for increasing a coupling ratio and fabrication method thereof
CN100401521C (en) * 2003-05-20 2008-07-09 三星电子株式会社 EEPROM cell structures having non-uniform channel-dielectric thickness and methods of making the same

Similar Documents

Publication Publication Date Title
TW561513B (en) Semiconductor device and method of manufacturing the same
US5449941A (en) Semiconductor memory device
WO1992007382A1 (en) Structure of semiconductor device and manufacturing method thereof
KR100482711B1 (en) Semiconductor memory device and manufacturing method thereof
JPH07123146B2 (en) Method of manufacturing nonvolatile semiconductor memory device
JPH021988A (en) Electrically programmable memory cell
JP2003282748A (en) Nonvolatile semiconductor memory device
KR930001888B1 (en) Non-volatile semiconductor memory device
JPH02277269A (en) Manufacture of nonvolatile memory
JPH0964205A (en) Si nitride film forming method
US6011289A (en) Metal oxide stack for flash memory application
JPH05129630A (en) Production of nonvolatile semiconductor storage device
JPH061839B2 (en) Method of manufacturing nonvolatile memory device
TWI239598B (en) Semiconductor memory device and manufacturing method thereof
US20020145162A1 (en) Non-volatile semiconductor storage device and method for producing the same
JPH0831539B2 (en) Non-volatile memory manufacturing method
JPH02114568A (en) Manufacture of nonvolatile storage device
JP2604863B2 (en) Method for manufacturing semiconductor nonvolatile memory device
JPH0422031B2 (en)
JPH05129632A (en) Charge trap film
JPH0665232B2 (en) Method of manufacturing semiconductor memory device
JPH0227773A (en) Manufacture of nonvolatile semiconductor memory
JPH0521805A (en) Manufacture of semiconductor device
JPS58212180A (en) Nonvolatile memory device and manufacture thereof
JPH0478189B2 (en)