JPH061839B2 - Method of manufacturing nonvolatile memory device - Google Patents
Method of manufacturing nonvolatile memory deviceInfo
- Publication number
- JPH061839B2 JPH061839B2 JP58110121A JP11012183A JPH061839B2 JP H061839 B2 JPH061839 B2 JP H061839B2 JP 58110121 A JP58110121 A JP 58110121A JP 11012183 A JP11012183 A JP 11012183A JP H061839 B2 JPH061839 B2 JP H061839B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride film
- film
- memory device
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 29
- 235000012239 silicon dioxide Nutrition 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 239000001257 hydrogen Substances 0.000 claims description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 239000003870 refractory metal Substances 0.000 claims description 7
- -1 hydrogen ions Chemical class 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000010354 integration Effects 0.000 description 8
- 230000006866 deterioration Effects 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000007373 indentation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、MNOS（金属−窒化膜−酸化膜−半導体）型の
電界トランジスタからなる不揮発性記憶装置の製造方法
に関するものである。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a nonvolatile memory device including an electric field transistor of MNOS (metal-nitride film-oxide film-semiconductor) type.
（従来例の構成とその問題点） 一般に、MNOS型の不揮発性記憶装置は、ゲート絶縁膜と
して薄い二酸化シリコン膜と窒化シリコン膜との二層を
用いて、これらをシリコン基板上に順次積層し、さらに
窒化シリコン膜上にアルミニウムからなるゲート電極を
形成したもので、これら二層の絶縁膜の界面または窒化
シリコン膜のバルク中に分布するトラップに、シリコン
基板側から薄い二酸化シリコン膜を通してのトンネル注
入により電荷を捕獲し、その蓄積によりトランジスタの
閾値電圧を変化させて情報を記憶するものである。(Structure of Conventional Example and Problems Thereof) In general, a MNOS type non-volatile memory device uses two layers of a thin silicon dioxide film and a silicon nitride film as a gate insulating film, and these are sequentially laminated on a silicon substrate. , A gate electrode made of aluminum is further formed on the silicon nitride film, and the traps distributed at the interface between these two insulating films or in the bulk of the silicon nitride film are tunneled through the thin silicon dioxide film from the silicon substrate side. The charge is captured by injection, and the threshold voltage of the transistor is changed by storing the charge to store information.
ここで、近年では半導体装置の寸法微細化、高集積化お
よび高速化が推進されているが、ゲート電極をアルミニ
ウムで形成していると、現在要求されている高度な寸法
微細化および高集積化を達成することが困難になってい
る。そのため、MOS型半導体装置などでは、ゲート電極
をポリシリコンまたは高融点金属で形成するとともにセ
ルファライン技術を用いて高集積化を実現している。Here, in recent years, dimensional miniaturization, high integration, and high speed of semiconductor devices have been promoted. However, if the gate electrode is made of aluminum, the high dimensional miniaturization and high integration required at present are required. Is difficult to achieve. Therefore, in a MOS type semiconductor device or the like, the gate electrode is made of polysilicon or a refractory metal and high integration is realized by using the self-alignment technique.
そこで従来、MNOS型の不揮発性記憶装置においても、高
集積化を実現するためにゲート電極をポリシリコンまた
は高融点金属で形成し、且つセルファライン技術を用い
て構成したものが提案されていて、この場合、シリコン
基板上に薄い二酸化シリコン膜を形成し、その上に窒化
シリコン膜を成長させた後、ポリシリコンまたは高融点
金属からなるゲート電極を形成し、さらに、ソースおよ
びドレインの形成、保護膜の形成などの工程を経て構成
されている。Therefore, conventionally, even in the MNOS type non-volatile memory device, it has been proposed that the gate electrode is formed of polysilicon or a refractory metal in order to realize high integration, and is configured by using the self-aligning technique. In this case, a thin silicon dioxide film is formed on a silicon substrate, a silicon nitride film is grown on it, and then a gate electrode made of polysilicon or a refractory metal is formed. It is configured through steps such as film formation.
しかしながら、このような従来のMNOS型の不揮発性記憶
装置では、上記の製造工程においてソースおよびドレイ
ンの押し込み、保護膜の緻密化などのために1000℃程度
の高温処理を必要とするので、記憶保持特性が悪化する
ことが知られている。このため、元来他の不揮発性記憶
装置に比べて記憶保持特性がやや劣るMNOS型の不揮発性
記憶装置では、上記の高集積化に伴う記憶保持特性の悪
化が実用上の最大の問題となっていた。However, in such a conventional MNOS type non-volatile memory device, since high temperature treatment of about 1000 ° C. is required for the source and drain indentation and the protective film densification in the above manufacturing process, the memory retention It is known that the characteristics deteriorate. Therefore, in the MNOS type non-volatile memory device, which originally has a slightly poorer memory retention characteristic than other non-volatile memory devices, the deterioration of the memory retention characteristic due to the above-mentioned high integration is the biggest practical problem. Was there.
（発明の目的） 本発明は、上記従来例の欠点に鑑みてなされたもので、
ゲート電極にポリシリコンまたは高融点金属を用いて高
集積化を可能にし、且つ記憶保持特性を向上させること
ができる不揮発性記憶装置の製造方法を提供するもので
ある。(Object of the Invention) The present invention has been made in view of the drawbacks of the above-mentioned conventional examples,
Provided is a method for manufacturing a non-volatile memory device which can be highly integrated by using polysilicon or a refractory metal for a gate electrode and can improve memory retention characteristics.
（発明の構成） 上記目的を達成するために、本発明は、半導体基板上に
ゲート絶縁膜として薄い二酸化シリコン膜と窒化シリコ
ン膜とを積層して形成し、その上にゲート電極を形成
し、さらに半導体基板内にソースおよびドレインを形成
した後に、水素イオン注入を行うことにより窒化シリコ
ン膜の水素の含有量を増加させるようにしたものであ
る。(Structure of the Invention) In order to achieve the above-mentioned object, the present invention forms a thin silicon dioxide film and a silicon nitride film as a gate insulating film by laminating on a semiconductor substrate, and forms a gate electrode thereon, Further, after the source and drain are formed in the semiconductor substrate, hydrogen ion implantation is performed to increase the hydrogen content of the silicon nitride film.
（実施例の説明） 実施例を説明する前に記憶保持特性の悪化について述べ
ると、この記憶保持特性の悪化は、ソースおよびドレイ
ンの押し込みなどのための熱処理に起因するものである
が、窒化シリコン膜の形成条件にも関係があり、熱処理
の温度が窒化シリコン膜の成長温度よりも高い場合に記
憶保持特性の悪化が生じ、熱処理の温度が窒化シリコン
膜の成長温度よりも低い場合には記憶保持特性の悪化が
ほとんど生じない。これは、窒化シリコン膜の成長温度
よりも高い温度で熱処理したとき、窒化シリコン膜の中
に含まれる水素、とくにSi-H結合の数が少なくなり、不
安定なトラップが附加増大されるためである。(Explanation of Embodiments) Before describing the embodiments, the deterioration of the memory retention characteristics will be described. Although the deterioration of the memory retention characteristics is caused by the heat treatment for pushing the source and drain, It also depends on the film formation conditions. When the temperature of the heat treatment is higher than the growth temperature of the silicon nitride film, the memory retention characteristic deteriorates, and when the temperature of the heat treatment is lower than the growth temperature of the silicon nitride film, the memory Almost no deterioration of the holding property occurs. This is because when heat treatment is performed at a temperature higher than the growth temperature of the silicon nitride film, the number of hydrogen, particularly Si-H bonds, contained in the silicon nitride film decreases, and unstable traps increase additionally. is there.
従って、本発明は、窒化シリコン膜の成長温度よりも高
い温度を必要とする熱処理を行った後に、水素イオンを
注入して窒化シリコン膜の水素の含有量を増加させ、さ
らに注入した水素イオンの活性化のために、窒化シリコ
ン膜の成長温度よりも低い温度で熱処理を行うことによ
り、MNOS型の不揮発性記憶装置の高集積化に伴う記憶保
持特性の悪化を防止するようにしたものであり、以下、
図面により本発明の実施例を具体的に説明する。Therefore, according to the present invention, after performing a heat treatment that requires a temperature higher than the growth temperature of the silicon nitride film, hydrogen ions are implanted to increase the hydrogen content of the silicon nitride film, and For activation, heat treatment is performed at a temperature lower than the growth temperature of the silicon nitride film to prevent the deterioration of the memory retention characteristic due to the high integration of the MNOS type nonvolatile memory device. ,Less than,
Embodiments of the present invention will be specifically described with reference to the drawings.
第１図(A)ないし(F)は、本発明の一実施例の工程を示す
図である。まず、第１(A)に示すように、Ｐ型のシリコ
ン基板１の一主面に二酸化シリコン膜２を500Å形成
し、その上に窒化シリコン膜３を1200Å程度形成した後
に、フォトエッチング技術を用いてシリコン基板１上の
素子分離領域となる部分の二酸化シリコン膜２および窒
化シリコン膜３を除去する。次に、第１図(B)に示すよ
うに、熱酸化法によりシリコン基板１の表面が露出した
部分に素子分離用のフィールド酸化膜４を１μｍ程度形
成させる。その後、第１図(C)に示すように、窒化シリ
コン膜３とその下の二酸化シリコン膜２とを順次エッチ
ングにより除去し、新たに２０Å程度の薄い二酸化シリ
コン膜５を、800℃、酸素雰囲気中で酸化して形成す
る。次いで、第１図(D)に示すように、二酸化シリコン
膜５上に、ジクロルシラン(SiH2Cl2)とアンモニア(NH3)
の化学反応に基づく減圧気相成長法により窒化シリコン
膜６を形成する。本実施例では、成長温度800℃、ガス
流量比NH3/SiH2Cl2＝100の条件下で、窒化シリコン膜６
を500Å形成した。そして窒化シリコン膜６上にポリシ
リコン膜を形成した後、ゲート電極７となる部分だけを
残してフォトエッチングにより除去して、窒化シリコン
膜６上にポリシリコンからなるゲート電極７を形成す
る。その後、このゲート電極７とフィールド酸化膜４を
マスクとし、リンを加速エネルギー100kevで、注入量４
×1015cm-2だけ注入して、ソース８およびドレイン９を
打ち込むとともに、ポリシリコンからなるゲート電極７
にもリンを注入する。次に、第１(E)に示すように、表
面保護膜として二酸化シリコン膜10を気相成長法により
被着した後、ソースおよびドレイン9の押し込みと、二
酸化シリコン膜10の緻密化と、ゲート電極７のアニール
のために、1000℃で２０分、Ｎ２雰囲気中で熱処理を行
う。その後、水素イオン11を注入する。本実施例では、
水素イオン11としてＨ２ ＋イオンを用いて、注入条件は
加速エネルギー10KeV、注入量５×1015cm-2とした。さ
らに、注入イオンの活性化のために、窒化シリコン膜６
の成長温度よりも低い温度で熱処理を行う。本実施例で
は、700℃で２０分、Ｎ２雰囲気中で熱処理を行った。
最後に、第１図(F)に示すように、ソース8およびドレイ
ン9にそれぞれ電極を設けるために、シリコン基板１上
に積層された二酸化シリコン膜５、窒化シリコン膜６お
よび二酸化シリコン膜10を貫通し、シリコン基板１内の
ソース８およびドレイン９にそれぞれ到達するコンタク
ト孔をエッチングにより開孔し、アルミニウム膜を主面
に被着した後、フォトエッチングによりソース８および
ドレイン９と接続したアルミニウム電極12をそれぞれ形
成する。こうして、MNOS型のＮチャンネル型不揮発性記
憶装置が完成する。FIGS. 1 (A) to 1 (F) are views showing steps of one embodiment of the present invention. First, as shown in FIG. 1 (A), a silicon dioxide film 2 is formed on a main surface of a P-type silicon substrate 1 by 500 Å, and a silicon nitride film 3 is formed thereon by about 1200 Å, and then a photoetching technique is applied. Then, the silicon dioxide film 2 and the silicon nitride film 3 in the portion to be the element isolation region on the silicon substrate 1 are removed. Next, as shown in FIG. 1B, a field oxide film 4 for element isolation is formed to a thickness of about 1 μm on the exposed portion of the surface of the silicon substrate 1 by a thermal oxidation method. Thereafter, as shown in FIG. 1 (C), the silicon nitride film 3 and the silicon dioxide film 2 thereunder are sequentially removed by etching, and a new thin silicon dioxide film 5 of about 20 Å is newly formed at 800 ° C. in an oxygen atmosphere. It oxidizes in and forms. Then, as shown in FIG. 1 (D), dichlorosilane (SiH 2 Cl 2 ) and ammonia (NH 3 ) are formed on the silicon dioxide film 5.
The silicon nitride film 6 is formed by the low pressure vapor phase growth method based on the chemical reaction of. In this example, the silicon nitride film 6 was formed under the conditions of a growth temperature of 800 ° C. and a gas flow rate ratio of NH 3 / SiH 2 Cl 2 = 100.
Formed 500Å. Then, after forming a polysilicon film on the silicon nitride film 6, the gate electrode 7 made of polysilicon is formed on the silicon nitride film 6 by photoetching, leaving only the portion to be the gate electrode 7. After that, using the gate electrode 7 and the field oxide film 4 as a mask, phosphorus is implanted with an acceleration energy of 100 kev and an implantation amount of 4
Implanting only × 10 15 cm -2 to implant the source 8 and the drain 9 and the gate electrode 7 made of polysilicon.
Also inject phosphorus. Next, as shown in the first (E), after depositing a silicon dioxide film 10 as a surface protection film by vapor phase epitaxy, the source and drain 9 are pushed in, the silicon dioxide film 10 is densified, and the gate is formed. To anneal the electrode 7, heat treatment is performed at 1000 ° C. for 20 minutes in an N 2 atmosphere. Then, hydrogen ions 11 are implanted. In this embodiment,
H 2 + ions were used as hydrogen ions 11, and the implantation conditions were an acceleration energy of 10 KeV and an implantation dose of 5 × 10 15 cm -2 . Further, the silicon nitride film 6 is used to activate the implanted ions.
Heat treatment is performed at a temperature lower than the growth temperature of. In this example, heat treatment was performed at 700 ° C. for 20 minutes in an N 2 atmosphere.
Finally, as shown in FIG. 1 (F), the silicon dioxide film 5, the silicon nitride film 6 and the silicon dioxide film 10 laminated on the silicon substrate 1 are provided to form electrodes on the source 8 and the drain 9, respectively. Contact holes penetrating through and reaching the source 8 and the drain 9 in the silicon substrate 1 are opened by etching, an aluminum film is deposited on the main surface, and then an aluminum electrode connected to the source 8 and the drain 9 by photoetching. 12 are formed respectively. Thus, the MNOS type N-channel nonvolatile memory device is completed.
上記のように作製されたMNOS型の不揮発性記憶装置の記
憶保持特性を第２図に示す。第２図において、横軸は書
き込み消去直後の閾値電圧、縦軸はその時に蓄積された
電荷減衰率（∂Vth/∂logt;Vthは閾値電圧、ｔは時間）
を示していて、直線の傾きが小さいほど記憶特性が優れ
ていることを示している。また、直線13は本実施例によ
り作製さた不揮発性記憶装置の記憶保持特性を示してい
て、水素イオン注入を行わない従来の不揮発性記憶装置
の記憶保持特性を示す直線14に比べて傾きが小さく、優
れた記憶保持特性を有していることがわかる。The memory retention characteristics of the MNOS type nonvolatile memory device manufactured as described above are shown in FIG. In FIG. 2, the horizontal axis represents the threshold voltage immediately after programming and erasing, and the vertical axis represents the charge decay rate accumulated at that time (∂Vth / ∂logt; Vth is the threshold voltage, t is time).
And the smaller the slope of the straight line, the better the memory characteristic. Further, the straight line 13 shows the memory retention characteristics of the nonvolatile memory device manufactured according to this example, and has a slope smaller than that of the straight line 14 showing the memory retention characteristics of the conventional nonvolatile memory device in which hydrogen ion implantation is not performed. It can be seen that it is small and has excellent memory retention characteristics.
なお、本実施例では、Ｐ型のシリコン基板１を用いてＮ
チャンネル型の不揮発性記憶装置を作製する場合につい
て説明したが、Ｎ型のシリコン基板を用いてＰチャンネ
ル型のものを作製できることはもちろんであり、さら
に、ゲート電極７としては、ポリシリコンだけでなく高
融点金属でも同様に作製できることな自明である。ま
た、本実施例では、水素イオン11としてＨ２ ＋イオンを
用いたが、Ｈ＋イオンおよびＨ３ ＋イオンなどを用いて
も同様な効果が得られる。In this embodiment, the P-type silicon substrate 1 is used for N
Although the case of manufacturing a channel type nonvolatile memory device has been described, it goes without saying that a P channel type can be manufactured using an N type silicon substrate, and further, as the gate electrode 7, not only polysilicon but also It is self-evident that a refractory metal can be similarly produced. Further, in this embodiment, H 2 + ions are used as the hydrogen ions 11, but the same effect can be obtained by using H + ions and H 3 + ions.
（発明の効果） 以上説明したように、本発明は、不揮発性記憶装置を作
製する際に、窒化シリコン膜を形成した後にそれの成長
温度よりも高い温度の熱処理を施す場合、その熱処理後
に水素イオン注入を行うことにより、前記保持特性の悪
化のない非常に優れた不揮発性記憶装置を作製すること
ができるので、ゲート電極にポリシリコンまたは高融点
金属を用いて高集積化を図る際の記憶保持特性の悪化を
解消し、不揮発性記憶装置の高集積化および高性能化を
可能にするものである。(Effects of the Invention) As described above, according to the present invention, when a silicon nitride film is formed and then heat treatment is performed at a temperature higher than its growth temperature when a nonvolatile memory device is manufactured, hydrogen is generated after the heat treatment. By performing ion implantation, it is possible to manufacture a very excellent nonvolatile memory device in which the retention characteristic is not deteriorated. Therefore, it is possible to use a polysilicon or a refractory metal for the gate electrode to achieve high integration. It is possible to solve the deterioration of the retention characteristic and to realize high integration and high performance of the nonvolatile memory device.
第１図は、本発明の一実施例の工程図、第２図は、本発
明の一実施例により作製された不揮発性記憶装置の記憶
保持特性を示す図である。 １……シリコン基板、2，5，10……二酸化シリコン膜、
3，6……窒化シリコン膜、４……フィールド酸化膜、７
……ゲート電極、８……ソース、９……ドレイン、11…
…水素イオン、12……アルミニウム電極。FIG. 1 is a process diagram of one embodiment of the present invention, and FIG. 2 is a diagram showing a memory retention characteristic of a nonvolatile memory device manufactured according to one embodiment of the present invention. 1 ... Silicon substrate, 2, 5, 10 ... Silicon dioxide film,
3, 6 ... Silicon nitride film, 4 ... Field oxide film, 7
... gate electrode, 8 ... source, 9 ... drain, 11 ...
… Hydrogen ion, 12… Aluminum electrode.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−93289（ＪＰ，Ａ) 特開 昭59−69973（ＪＰ，Ａ) 特開 昭55−30846（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-58-93289 (JP, A) JP-A-59-69973 (JP, A) JP-A-55-30846 (JP, A)
Claims (1)
膜を選択的に形成する工程と、前記二酸化シリコン膜上
に窒化シリコン膜を形成する工程と、前記窒化シリコン
膜上にゲート電極となるポリシリコン膜または高融点金
属膜を形成する工程と、前記工程で形成したゲート電極
をマスクとして不純物を自己整合的に注入したのち、前
記窒化シリコン膜の成長温度よりも高い温度の熱処理を
施してソース領域およびドレイン領域を形成する工程
と、前記熱処理後に水素イオンを注入し、さらに前記窒
化シリコン膜の成長温度よりも低い温度の熱処理を施し
て前記窒化シリコン膜の水素含有量を増加させる工程を
有することを特徴とする不揮発性記憶装置の製造方法。1. A step of selectively forming a thin silicon dioxide film on one main surface of a semiconductor substrate, a step of forming a silicon nitride film on the silicon dioxide film, and a gate electrode on the silicon nitride film. After a step of forming a polysilicon film or a refractory metal film and implanting impurities in a self-aligned manner using the gate electrode formed in the step as a mask, heat treatment at a temperature higher than the growth temperature of the silicon nitride film is performed. A step of forming a source region and a drain region, and a step of implanting hydrogen ions after the heat treatment and further performing a heat treatment at a temperature lower than the growth temperature of the silicon nitride film to increase the hydrogen content of the silicon nitride film. A method for manufacturing a non-volatile memory device having:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58110121A JPH061839B2 (en) | 1983-06-21 | 1983-06-21 | Method of manufacturing nonvolatile memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58110121A JPH061839B2 (en) | 1983-06-21 | 1983-06-21 | Method of manufacturing nonvolatile memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS603159A JPS603159A (en) | 1985-01-09 |
| JPH061839B2 true JPH061839B2 (en) | 1994-01-05 |
Family
ID=14527560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58110121A Expired - Lifetime JPH061839B2 (en) | 1983-06-21 | 1983-06-21 | Method of manufacturing nonvolatile memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH061839B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0665232B2 (en) * | 1984-07-30 | 1994-08-22 | 松下電子工業株式会社 | Method of manufacturing semiconductor memory device |
| JPH0693452B2 (en) * | 1986-01-29 | 1994-11-16 | 株式会社日立製作所 | Single-wafer thin film forming method and thin film forming apparatus |
| JPH0739676B2 (en) * | 1989-03-15 | 1995-05-01 | 東洋運搬機株式会社 | Vehicle with balance device |
| JPH0423363A (en) * | 1990-05-14 | 1992-01-27 | Matsushita Electron Corp | Manufacture of semiconductor memory |
| KR100549320B1 (en) * | 2002-02-21 | 2006-02-02 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor storage device and its manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5893289A (en) * | 1981-11-30 | 1983-06-02 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS5969973A (en) * | 1982-10-15 | 1984-04-20 | Nec Corp | Semiconductor device |
-
1983
- 1983-06-21 JP JP58110121A patent/JPH061839B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS603159A (en) | 1985-01-09 |
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