JPH01264268A - Manufacture of nonvolatile memory device - Google Patents
Manufacture of nonvolatile memory deviceInfo
- Publication number
- JPH01264268A JPH01264268A JP63092598A JP9259888A JPH01264268A JP H01264268 A JPH01264268 A JP H01264268A JP 63092598 A JP63092598 A JP 63092598A JP 9259888 A JP9259888 A JP 9259888A JP H01264268 A JPH01264268 A JP H01264268A
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride film
- film
- gate electrode
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 35
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 12
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 11
- 239000011737 fluorine Substances 0.000 claims abstract description 11
- -1 fluorine ions Chemical class 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000005641 tunneling Effects 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 abstract description 16
- 239000010410 layer Substances 0.000 abstract description 11
- 230000001681 protective effect Effects 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 2
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000002844 melting Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 229910000473 manganese(VI) oxide Inorganic materials 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910008284 Si—F Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、ＭＮＯＳ （金属−窒化シリコン膜−二酸化
シリコン膜−半導体）型の電界トランジスタからなる不
揮発性記憶装置、特に記憶保持特性の優れた高性能の不
揮発性記憶装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a non-volatile memory device comprising an MNOS (metal-silicon nitride film-silicon dioxide film-semiconductor) field transistor, particularly a high-performance non-volatile memory device with excellent memory retention characteristics. The present invention relates to a method of manufacturing a nonvolatile memory device.
従来の技術
従来、ＭＮＯ３型不揮発性記憶装置では、半導体表面上
に第１層のゲート電極として、電荷がトンネル現象で通
過し得る＠薄め二酸化シリコン膜を、さらに第２層のゲ
ート電極として窒化シリコン膜を設け、この上にゲート
電極として、アルミニウム！＠を形成した構造が採られ
ている。Conventional technology Conventionally, in an MNO3 type nonvolatile memory device, a thin silicon dioxide film is used as a first layer gate electrode on a semiconductor surface through which charges can pass through by tunneling, and a silicon nitride film is further used as a second layer gate electrode. A film is provided, and a gate electrode is formed on this film using aluminum! The structure that forms @ is adopted.
なお、ＭＯ３型集積回路技術の進歩に伴い、寸法の微細
化、高集積化および高速化が進んでいる。In addition, with the progress of MO3 type integrated circuit technology, miniaturization of dimensions, higher integration, and higher speed are progressing.
この取り組みの中ではゲート！極材料として、多結晶シ
リコンなどの高融点金属を用いたセルファライン技術が
広く採用されている。Gate! Selfaline technology, which uses high-melting point metals such as polycrystalline silicon as the electrode material, is widely used.
ＭＮＯ３型不揮発性記憶装置においても、高集積化を実
現するために、ゲート電極材料として多結晶シリコンな
どの高融点金属を用い、セルフアライメント拡散技術を
駆使することがある。ところで、この方法ではゲート電
極形成後に、ソース領域および、ドレイン領域を形成す
る拡散処理が施され、しかも、この拡散処理温度が窒化
シリコン膜形成温度以上の高温（９００〜１０００℃）
であるために、ＭＮＯ３型記憶素子の記憶保持特性が悪
化する。Even in MNO3 type nonvolatile memory devices, in order to achieve high integration, a high melting point metal such as polycrystalline silicon is used as the gate electrode material, and self-alignment diffusion technology is sometimes used. By the way, in this method, after the gate electrode is formed, a diffusion process is performed to form a source region and a drain region, and the temperature of this diffusion process is a high temperature (900 to 1000°C) higher than the silicon nitride film formation temperature.
Therefore, the memory retention characteristics of the MNO3 type memory element deteriorate.
発明が解決しようとする課題
ＭＮＯ３型不揮発性記憶装置は、窒化シリコン膜と極薄
の二酸化シリコン膜の界面、または窒化シリコン膜のバ
ルク中に分布するトラップへ半導体側から［！薄の二酸
化シリコン膜を介して行われる電荷のトンネリング注入
とその蓄積によってトランジスタのしきい値電圧（Ｖ
ｔｈ）を変化させ、情報を記憶させるものであり、その
記憶保持特性の確保がＭＮＯ３型不揮発性記憶装置の最
大の課題である。したがって、ゲート電極材料として多
結晶シリコンなどの高融点金属を用いた場合の記憶保持
特性の悪化は、実用上の最大の問題となっていた。Problems to be Solved by the Invention In an MNO3 type nonvolatile memory device, [! The threshold voltage of the transistor (V
th) to store information, and ensuring the memory retention characteristics is the biggest challenge for MNO3 type nonvolatile storage devices. Therefore, deterioration in memory retention characteristics when a high melting point metal such as polycrystalline silicon is used as a gate electrode material has become the biggest practical problem.
本発明は上記問題を解決するもので、ゲート電極材料と
して高融点金属を用いるものの、良好な記憶保持特性を
維持することができ、したがって高集積化においても飛
躍的な向上をはかることのできる半導体記憶装置の製造
方法を提供することを目的とするものである。The present invention solves the above problems, and although a high-melting point metal is used as the gate electrode material, it is possible to maintain good memory retention characteristics, and therefore, it is possible to create a semiconductor that can be dramatically improved in terms of high integration. An object of the present invention is to provide a method for manufacturing a storage device.
課題を解決するための手段
上記問題を解決するために本発明は、一導電型の半導体
基板面に、電子または正孔のトンネリング媒体となる極
薄の二酸化シリコン膜を形成する工程と、前記極薄の二
酸化シリコン膜上に窒化シリコン膜を形成する工程と、
前記窒化シリコン膜上にゲート電極を形成する工程を少
なくとも有し、さらに、上記窒化シリコン膜を形成した
後に、フッ素イオンを注入する工程と、フッ素イオン注
入後に熱処理を施す工程を含むことを特徴とするもので
ある。Means for Solving the Problems In order to solve the above problems, the present invention includes a step of forming an ultra-thin silicon dioxide film, which serves as a tunneling medium for electrons or holes, on the surface of a semiconductor substrate of one conductivity type; forming a silicon nitride film on a thin silicon dioxide film;
The present invention is characterized by comprising at least a step of forming a gate electrode on the silicon nitride film, and further comprising a step of implanting fluorine ions after forming the silicon nitride film, and a step of performing heat treatment after implanting the fluorine ions. It is something to do.
作用
本発明者の研究によれば、ＭＮＯＳメモリのゲート電極
である窒化シリコン膜形成後の高温熱処理による記憶保
持特性の悪化は、窒化シリコン膜中に含まれる水素、特
にＳｉ −Ｈ結合の含有量に関係があり、Ｓｉ −Ｈ結
合の多い窒化シリコン膜では９００℃以上の温度で熱処
理を行うことにより５ｉ−Ｈ結合が減少し、Ｓｉ原子の
未結合手（ｄａｎｇｌｉｎｇ ｂｏｎｄ ）が増大する
ことから不安定なトラップが附加増大し、記憶保持特性
が悪化することが明らかとなった。すなわち、窒化シリ
コン膜形成後の熱処理による記憶保持特性の悪化は、窒
化シリコン膜中の不安定なＳｉ原子の未結合手の含有量
に大きく依存している。According to the research conducted by the present inventors, the deterioration of memory retention characteristics due to high temperature heat treatment after forming the silicon nitride film, which is the gate electrode of the MNOS memory, is due to the hydrogen contained in the silicon nitride film, especially the content of Si-H bonds. In a silicon nitride film with many Si-H bonds, heat treatment at a temperature of 900°C or higher reduces the number of 5i-H bonds and increases the number of dangling bonds between Si atoms. It became clear that the number of stable traps increased and the memory retention properties deteriorated. That is, deterioration in memory retention characteristics due to heat treatment after forming a silicon nitride film largely depends on the content of unstable dangling bonds of Si atoms in the silicon nitride film.
ところで、Ｓｉ原子の未結合手をＨ（水素）で終端した
５ｉ−Ｈ結合にくらべてＦ（フッ素）で終端しなＳｉ
−Ｆ結合は分解しにくいことがよく知られている。これ
は、Ｓｉ −Ｈ結合エネルギ（７１，４Ｋｃａｌ／ｎｏ
ｔ ）よりもＳｉ −Ｆ結合エネルギ（１１６にｃａｌ
／ｎｏｌ ）が大きいためである。By the way, compared to the 5i-H bond in which the dangling bond of the Si atom is terminated with H (hydrogen), the Si atom which does not terminate with F (fluorine)
It is well known that the -F bond is difficult to decompose. This is the Si-H bond energy (71,4Kcal/no
t ) than the Si-F bond energy (116 cal
/nol) is large.
本発明は、上記の事実に基づき、トンネリング媒体とな
る１Ｆｆｌ薄の二酸化シリコン膜上に窒化シリコン膜、
ゲート電極を形成した後、水素よりも安定なフッ素イオ
ンを注入し、さらにフッ素イオンの活性化を目的としな
熱処理（アニール）を行うことによりＳｉ原子の未結合
手を減少させて、不安定なトラップの増大を防ぎ優れた
記憶保持特性を得たものである。Based on the above facts, the present invention provides a silicon nitride film on a 1 Ffl thin silicon dioxide film serving as a tunneling medium.
After forming the gate electrode, fluorine ions, which are more stable than hydrogen, are implanted, and heat treatment (annealing) is performed to activate the fluorine ions, thereby reducing the dangling bonds of Si atoms and making them unstable. This prevents the increase of traps and provides excellent memory retention properties.
実施例 以下、本発明の一実施例を図面を用いて説明する。Example An embodiment of the present invention will be described below with reference to the drawings.
第１図［ａ）〜（ｄ）は本発明の製造方法の一実施例を
工程順に示す半導体記憶装置の断面楕遣図である０本発
明の製造方法では、先ず、第１図（ａ）で示すように、
Ｐ型シリコン基板１上に、保護酸化ＷＡ２を、さらに窒
化シリコン膜３を形成した後、トランジスタ活性領域形
成のためにリソグラフィ技術およびエツチング技術を用
いて所定の部分を除去する０次いで、窒化シリコン膜３
をマスクとして用いた選択酸化（Ｌ、０ＣＯ３）処理を
緒して素子分離用のフィールド酸化Ｍ４を形成する０本
実施例では、保護酸化膜２を５００Ａ、窒化シリコンＭ
３を１２００人程度ヒレ、フィールド酸化膜厚を８００
０人程度上巳な。FIGS. 1(a) to 1(d) are cross-sectional elliptical views of a semiconductor memory device showing an embodiment of the manufacturing method of the present invention in the order of steps. In the manufacturing method of the present invention, first, FIG. 1(a) As shown in
After forming a protective oxide WA2 and a silicon nitride film 3 on a P-type silicon substrate 1, predetermined portions are removed using lithography and etching techniques to form a transistor active region.Next, the silicon nitride film is removed. 3
In this example, the protective oxide film 2 is made of silicon nitride M4 of 500A and silicon nitride M4.
3 to about 1200 fins, field oxide film thickness to 800
About 0 people.
次いで、窒化シリコン膜３および保護酸化膜２をエツチ
ングにより除去した後、第１図（ｂ）で示すようにＭＮ
Ｏ３型不揮発性メモリトランジスタのゲート電極である
極薄の二酸化シリコン膜５、窒化シリコン膜６さらに、
ゲート電極層７を成長する。この極薄の二酸化シリコン
膜は電子または正孔のトンネリング媒体となりうるちの
である。Next, after removing the silicon nitride film 3 and the protective oxide film 2 by etching, the MN is etched as shown in FIG. 1(b).
Ultra-thin silicon dioxide film 5 and silicon nitride film 6, which are gate electrodes of the O3 type nonvolatile memory transistor;
A gate electrode layer 7 is grown. This ultra-thin silicon dioxide film can serve as a tunneling medium for electrons or holes.
その後リソグラフィ技術およびエツチング技術を用いて
、ゲートとなる部分以外のゲート電極層７、さらに窒化
シリコン１ｌＵ６、二酸化シリコン膜５を除去する０本
実施例では、トンネリング媒体となる極薄の二酸化シリ
コン膜５の厚みを２０人程度、窒化シリコン膜６の厚み
を５００ Ａ程度とし、ゲート電極層７を４０００八程
度の厚さの多結晶シリコン層とした。なお、窒化シリコ
ン膜６の形成は、ジクロルシラン（ＳｉＨ２Ｃ１２）ガ
スとアンモニア（ＮＨ３）ガスの化学反応を利用した減
圧気相成長法により、成長温度８００℃、ガス流量比Ｎ
Ｈ３／Ｓ ｉ Ｈ２Ｃ１２＝１０の条件下で行った。Thereafter, using lithography technology and etching technology, the gate electrode layer 7 other than the portion that will become the gate, as well as the silicon nitride layer 11U6 and the silicon dioxide film 5 are removed. The thickness of the silicon nitride film 6 was about 500 A, and the gate electrode layer 7 was a polycrystalline silicon layer about 4,000 A thick. The silicon nitride film 6 was formed by a low-pressure vapor phase growth method using a chemical reaction between dichlorosilane (SiH2C12) gas and ammonia (NH3) gas at a growth temperature of 800°C and a gas flow rate ratio of N.
The test was carried out under the condition of H3/S i H2C12=10.
次いで、第１図（Ｃ）に示すように、ゲート電極層７と
フィールド酸化膜４をマスクとするセルファライン技術
を用いたｎ型不純物のイオン注入、気相成長技術を用い
た眉間電極１０の形成およびアニールと注入した不純物
イオンの押し込みのための窒化シリコン膜の成長温度以
上の高温熱処理を施してソース領域８とドレイン領域９
を形成した後、フッ素イオン（Ｆ”、Ｆ”＋など）の注
入を施し、さらに窒素雰囲気中において熱処理（アニー
ル）を施す。Next, as shown in FIG. 1C, n-type impurity ions are implanted using self-line technology using the gate electrode layer 7 and field oxide film 4 as masks, and glabellar electrodes 10 are formed using vapor phase growth technology. The source region 8 and the drain region 9 are formed by performing high-temperature heat treatment at a temperature higher than the growth temperature of the silicon nitride film for forming, annealing, and pushing in the implanted impurity ions.
After forming, fluorine ions (F", F"+, etc.) are implanted, and further heat treatment (annealing) is performed in a nitrogen atmosphere.
以上のような製造方法で得られた半導体記憶装置の記憶
保持特性の一例を第２図に示す、横軸は書き込み−、消
去直後のしきい値電圧、縦軸はそのときに蓄積された電
荷の減衰率（ａ Ｖｔｈ／ ａ ｆｏｇｔ ；Ｖｔｈ：
Ｌきい値電圧、ｔ：時間）を示している。An example of the memory retention characteristics of a semiconductor memory device obtained by the above manufacturing method is shown in Figure 2, where the horizontal axis represents the threshold voltage immediately after writing and erasing, and the vertical axis represents the charge accumulated at that time. Attenuation rate (a Vth/ a fogt ; Vth:
L threshold voltage, t: time).
第２図の直線の傾きが小さいほど、記憶保持特性が優れ
ていることを示している。Ａ直線は本実施例の製造方法
により作製された不揮発性記憶装置の記憶保持特性を示
し、Ｂ直線のフッ素イオン注入を施さない場合に比べて
傾きが小さく、優れた記憶保持特性を有していることが
わかる。The smaller the slope of the straight line in FIG. 2, the better the memory retention characteristics are. The A straight line indicates the memory retention characteristics of the nonvolatile memory device manufactured by the manufacturing method of this example, and the slope is smaller than that of the nonvolatile memory device manufactured by the manufacturing method of this example, and the slope is smaller than that of the nonvolatile memory device manufactured by the manufacturing method of this example, and it has excellent memory retention characteristics. I know that there is.
本実施例では、ソース領域８とドレイン領域９を形成す
るｎ型不純物イオンとしてヒ素（Ａｓ”）イオンを用い
、眉間電極１０としてリンガラス膜（ＰＳＧＩＩｇ）を
用い、膜厚を９５００人とした。また、アニールと注入
した不純物イオン、ソース、トレインの押し込みに、窒
素雰囲気中で１０００℃程度の熱処理を施した。In this example, arsenic (As'') ions were used as n-type impurity ions forming the source region 8 and drain region 9, and a phosphorous glass film (PSGIIg) was used as the glabella electrode 10, with a film thickness of 9,500. Further, heat treatment at about 1000° C. in a nitrogen atmosphere was performed for annealing and pushing in the implanted impurity ions, sources, and trains.
さらにフッ素イオン注入条件を、フッ素イオン（Ｆ”）
、加速電圧１５０ＫｅＶ、注入量８．ＯｘｌｏＪ】−２
に設定し、このイオン注入後のアニール条件を、窒素雰
囲気中でｓｏｏ”ｃ程度の加熱処理とした。Furthermore, the fluorine ion implantation conditions were changed to fluorine ion (F”).
, acceleration voltage 150 KeV, implantation amount 8. OxloJ】-2
The annealing conditions after this ion implantation were a heat treatment of about soo''c in a nitrogen atmosphere.
次いで第１図（ｄ）に示すように、リソグラフの技術、
エツチング技術、および気相成長技術を用いて、コンタ
クト孔１１、金属（アルミニウム）配置１１２、および
保護膜１３の形成を行うことにより、ＮチャネルＭＮＯ
３型不揮発性記憶装置の作製が完了する。Next, as shown in FIG. 1(d), lithographic technology,
By forming contact holes 11, metal (aluminum) arrangement 112, and protective film 13 using etching technology and vapor phase growth technology, N-channel MNO
The fabrication of the type 3 nonvolatile memory device is completed.
本実施例では、Ｐ型シリコン基板を用いＮチャネル型不
揮発性記憶装置を作製する場合について説明したが、Ｐ
チャネル型不揮発性記憶装置の製作にも本発明を使用で
きることはもちろんである。In this example, a case was explained in which an N-channel type nonvolatile memory device was manufactured using a P-type silicon substrate.
Of course, the present invention can also be used to fabricate a channel type non-volatile memory device.
またゲート電極として多結晶シリコン膜以外の高融点金
属膜を用いてもよい、さらに、ゲート電極である窒化シ
リコン膜を酸化したゲート構造のＭＯＮＯ３型不揮発性
記憶装置についても同様の効果がある。Further, a high-melting point metal film other than a polycrystalline silicon film may be used as the gate electrode. Furthermore, a MONO3 type nonvolatile memory device having a gate structure in which the silicon nitride film serving as the gate electrode is oxidized has the same effect.
発明の効果
以上のように、本発明によれば、記憶保持特性の非常に
優れた高性能の不揮発性記憶装置を作製することができ
る。また、多結晶シリコンなどの高融点金属膜をゲート
電極として用いる構造の下で良好な記憶保持特性を維持
できるため、高集積化にも大きく寄与するものである。Effects of the Invention As described above, according to the present invention, a high-performance nonvolatile memory device with extremely excellent memory retention characteristics can be manufactured. Furthermore, since good memory retention characteristics can be maintained in a structure using a high-melting point metal film such as polycrystalline silicon as the gate electrode, it greatly contributes to higher integration.
第１図は本発明の一実施例を説明するための工程順断面
図、第２図は本発明の詳細な説明するための特性図であ
る。
１・・・Ｐ型シリコン基板、２・・・保護酸化膜、３・
・・窒化シリコン膜、４・・・フィールド酸化膜、５・
・・二酸化シリコン膜、６・・・窒化シリコン膜、７・
・・ゲート電極層、８・・・ソース（拡散ＩＷ）、９・
・・ドレイン（拡散Ｎ）、１０・・・層間電極、１１・
・・コンタクト孔、１２・・・金属配線、１３・・・保
護膜。
代理人 森 本 義 弘
第１図）Ｆｆ）２
ｇ ５６ り ’？ ｔ
／／第 ｌ 図 ￥のｆ
１：” Ｆ” Ｆ” Ｆ’ Ｆ” ｒ’
ｐ” Ｆ″４ ′
ｇ５６７’／ｆ
第２図FIG. 1 is a step-by-step sectional view for explaining an embodiment of the present invention, and FIG. 2 is a characteristic diagram for explaining the present invention in detail. 1...P-type silicon substrate, 2...protective oxide film, 3.
...Silicon nitride film, 4...Field oxide film, 5.
...Silicon dioxide film, 6...Silicon nitride film, 7.
...Gate electrode layer, 8...Source (diffused IW), 9.
...Drain (diffused N), 10...Interlayer electrode, 11.
...Contact hole, 12...Metal wiring, 13...Protective film. Agent Yoshihiro MorimotoFigure 1) Ff) 2 g 56 ri'? t
//Figure l f1 of ¥:” F” F” F' F” r'
p"F"4'g567'/f Fig. 2
Claims (1)
ネリング媒体となる極薄の二酸化シリコン膜を形成する
工程と、前記二酸化シリコン膜上に窒化シリコン膜を形
成する工程と、前記窒化シリコン膜上にゲート電極を形
成する工程と、前記窒化シリコン膜を形成した後に、フ
ッ素イオン注入を施す工程と、フッ素イオンを活性化す
る熱処理工程を含む不揮発性記憶装置の製造方法。 ２、フッ素イオン注入を施す工程は、窒化シリコン膜の
成長温度以上の熱処理工程が終了した後に行われること
を特徴とする請求項１記載の不揮発性記憶装置の製造方
法。[Claims] 1. A step of forming an extremely thin silicon dioxide film to serve as a tunneling medium for electrons or holes on the surface of a semiconductor substrate of one conductivity type, and forming a silicon nitride film on the silicon dioxide film. a step of forming a gate electrode on the silicon nitride film; a step of implanting fluorine ions after forming the silicon nitride film; and a heat treatment step of activating the fluorine ions. Method. 2. The method of manufacturing a nonvolatile memory device according to claim 1, wherein the step of implanting fluorine ions is performed after a heat treatment step at a temperature equal to or higher than the growth temperature of the silicon nitride film is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63092598A JPH01264268A (en) | 1988-04-14 | 1988-04-14 | Manufacture of nonvolatile memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63092598A JPH01264268A (en) | 1988-04-14 | 1988-04-14 | Manufacture of nonvolatile memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01264268A true JPH01264268A (en) | 1989-10-20 |
Family
ID=14058887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63092598A Pending JPH01264268A (en) | 1988-04-14 | 1988-04-14 | Manufacture of nonvolatile memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01264268A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521748A (en) * | 1991-07-17 | 1993-01-29 | Sharp Corp | Manufacture of insulation film for semiconductor device |
| US6445030B1 (en) | 2001-01-30 | 2002-09-03 | Advanced Micro Devices, Inc. | Flash memory erase speed by fluorine implant or fluorination |
| US6806532B2 (en) * | 2000-12-21 | 2004-10-19 | Renesas Technology Corp. | Nonvolatile semiconductor device |
-
1988
- 1988-04-14 JP JP63092598A patent/JPH01264268A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521748A (en) * | 1991-07-17 | 1993-01-29 | Sharp Corp | Manufacture of insulation film for semiconductor device |
| US6806532B2 (en) * | 2000-12-21 | 2004-10-19 | Renesas Technology Corp. | Nonvolatile semiconductor device |
| US6445030B1 (en) | 2001-01-30 | 2002-09-03 | Advanced Micro Devices, Inc. | Flash memory erase speed by fluorine implant or fluorination |
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