KR100307343B1 - A novel process to form reliable ultra-thin gate dielectric for advanced integrated circuit - Google Patents

Abstract

Disclosed herein is a process for fabricating a gate dielectric layer for use in silicon gate field effect transistors. The gate dielectric layer is a composite of a first layer grown with SiO ₂ , a second layer deposited with silicon nitride, and a third layer deposited with SiO ₂ . Nitride silicon present in the composite gate dielectric interferes with the diffusion of boron from the boron doped poly gate to the channel, thus reproducing the gate threshold. A threshold voltage is generated. These layers are formed in-situ in a low pressure chemical vapor deposition (LPCVD) reactor. These deposited layers are annealed to remove the remaining hydrogen, thereby reducing the trap density in the gate dielectric layer.

Description

A NOVEL PROCESS TO FORM RELIABLE ULTRA-THIN GATE DIELECTRIC FOR ADVANCED INTEGRATED CIRCUIT}

TECHNICAL FIELD The present invention relates to a method of manufacturing a field effect device, and more particularly, to a method of producing a gate dielectric for a silicon gate transistor.

Since the commercialization of silicon gate field effect transistors in the early 1970s, SiO ₂ layers were grown on silicon substrates in the channel region and polysilicon was deposited on the grown oxide layers. As a result, gate dielectrics for field effect devices have been manufactured. Workers in the art have used a number of alternative methods for forming gate dielectrics, but dielectric layers grown with SiO ₂ generally have a consistently superior dielectric due to the nature of the interface between the grown oxide and the silicon substrate. Proved to be. The low density of surface state at this interface is an attractive feature that has been difficult to satisfy with other dielectric materials. After the oxide layer has been grown, a low density surface state is deposited because a polysilicon gate electrode is deposited immediately which effectively seals the interface of the silicon oxide substrate from the effects of potential contamination in subsequent processing steps. Is limited to some.

Although many composite dielectric layers, in particular SiO ₂ / Si ₃ N ₄ , have been used, the preparation techniques used to form these composites typically degrade the quality of the interface, and oxide-nitrides Gate voltage hysteresis is caused by charge trapping at the oxide-nitride interface. Non-volatile memory devices have been developed using this charge storage mechanism, but in standard dynamic random access memory (DRAM) or static random access memory (SRAM) and logic devices, Gate dielectrics have been generally turned off due to the charge trapping properties of nitride thin films.

Certain techniques have been developed for producing composite SiO ₂ / Si ₃ N ₄ / SiO ₂ gate dielectrics for silicon gate field effect devices. This composite oxide-nitride dielectric acts as an electrically homogeneous grown oxide layer, but has the added advantage of higher dielectric constant for a given thickness, and is also boron-doped. doped) effectively blocks boron diffusion from the polysilicon gate through the gate dielectric. An important feature of this technique is that the quality of the interface between the SiO ₂ / Si ₃ N ₄ layers and the SiO ₂ layer and the silicon substrate is such that all layers of the composite are treated in-situ and the remaining hydrogen is removed. This is maintained by post annealing the low pressure chemical vapor deposition (LPCVD) deposition layer. Residual hydrogen generates dangling Si—H bonds in the composite layer forming the trapping site. These Si-H bonds become processing characteristics of LPCVD using silane or disilane and ammonia precursors.

1 is a schematic diagram of a gate region of a typical field effect transistor showing a composite gate dielectric layer fabricated in accordance with the fabrication method of the present invention;

2 is a schematic diagram after performing additional processing steps for the field effect transistor of FIG.

3-6 are schematic diagrams of process sequences for forming the composite gate dielectric layer of FIG. 1,

7 shows the drive current and gate leakage current for the voltage of a transistor processed according to the present invention in comparison to the case of a transistor having a standard gate dielectric layer,

8 shows a comparison of transconductance with respect to voltage;

9 shows a comparison of transistor lifetimes.

Explanation of symbols for the main parts of the drawings

11: substrate 12: field oxide

13: SiO ₂ growth layer 14: Si ₃ N ₄ deposition layer

15 SiO ₂ deposited layer 16 polysilicon gate layer

17 polysilicon gate 18 source

19: drain

Referring to FIG. 1, a silicon substrate 11 is shown with field oxide 12 formed in a conventional manner. In the next process sequence, a composite gate dielectric layer is formed. This composite dielectric layer includes a SiO ₂ growth layer 13, a Si ₃ N ₄ deposition layer 14, and a SiO ₂ deposition layer 15. In forming a composite gate dielectric stack, as will be described later, a total of three dielectric layers are deposited in one sequential operation. The completed stack is processed in a rapid thermal anneal process. A polysilicongate layer 16 is deposited on the gate dielectric stack.

After forming the gate dielectric and polysilicon gate contact layers, the device is completed in a conventional manner. 2, the gate dielectric layer is shown etched in the source and drain regions by polysilicon gate 17 as a mask. Sources and drains 18 and 19 are formed by conventional ion implantation methods. Alternatively, the dielectric layer may remain appropriate and the implant of the source and drain is injected through the dielectric layer by a polysilicon gate as an injection mask. For an n-channel device on a p-tub, the dopant is arsenic or phosphorus, which also exposes the gate electrode exposed to improve gate conductivity. electrode). Thereafter, an interlevel dielectric (not shown) is deposited, and the source and drain contact windows are opened by conventional lithography. Next, the source and drain contact metallization layers are deposited and patterned to form contacts for the source and drain, which contacts are shown generally at 21 and 22 in FIG. 2.

An important feature of the method of the present invention is that it forms a silicon gate structure. This will be explained in more detail with reference to FIGS. 3 to 6.

Referring to FIG. 3, a silicon substrate, shown at 31, is shown with a grown oxide layer 32. This process step and all subsequent process steps are performed sequentially in the same low pressure chemical vapor deposition (LPCVD) furnace, while the substrate is at reduced pressure, ie without breaking the vacuum of the furnace. To form a gate dielectric of the composite layer. For illustrative purposes, the layers created in this manner are defined as being formed "in-situ".

The LPCVD process itself is conventional and may be performed in any suitable LPCVD reactor. The point of the LPCVD process is to use a heating process and a low pressure process to initiate the chemical reaction of precursors to form a thin film or layer on the substrate. The silicon substrate is mounted in the furnace to form the original oxide layer, and the atmosphere is pumped to a pressure of less than 1 Torr, for example 50-950 mTorr. The atmosphere for oxide growth can be any suitable oxidizing gas, for example O ₂ , NO, N ₂ O. This oxidizing gas is introduced into the furnace with N ₂ , Ar or He, which is typically an inert carrier gas. The temperature of the furnace is typically 500-850 ° C., and the growth rate depends on the particular condition chosen. The growth process is conventional, and those skilled in the art will be well aware of the appropriate state.

The Si ₃ N ₄ layer shown at 33 in FIG. 4 is subsequently deposited sequentially in situ. If necessary, the pressure and temperature are adjusted. Typically Si ₃ N ₄ is deposited at a higher pressure than grown oxide layer 32, such as 10-500 mTorr, and at a higher temperature, such as 600-900 ° C. The atmosphere for silicon nitride deposition includes N ₂ , or NH ₃ mixed with silanes such as SiH ₄ , SiH ₂ Cl _2, and the like. Preferred mixtures are ammonia and dichlorosilane.

Referring to FIG. 5, this oxide layer 34 is deposited on a nitride layer 33. Various choices can be made to deposit SiO ₂ . Generally, tetraethoxysilane (TEOS) is used. Preferred choices are N ₂ O and SiH ₂ Cl ₂ , which are particularly compatible with the in-situ process sequence disclosed herein.

After the layers described above have been created, the dielectric stack is annealed to remove hydrogen remaining in the LPCVD layer. LPCVD processes using silane and ammonia as precursor gases contain a significant amount of hydrogen, and the hydrogen remaining in the gate dielectric traps carriers, changing the gate threshold (VT). It is important for this process to remove the hydrogen remaining at the stage of this process sequence. Annealing is carried out in the same LPCVD furnace in an inert gas atmosphere, where the inert gas is preferably the carrier gas that has been used in one or more previous steps. This annealing is carried out at a temperature of 800-1000 ° C. for 5 seconds to 5 minutes. This annealing also reduces the porosity of the layer and the potential for contamination during processing.

After completing this gate dielectric stack, the polysilicon gate layer 35 is deposited using well known techniques as shown in FIG. For example, LPCVD and chemical vapor deposition (CVD) can be used with SiH ₄ and H ₂ as precursor gases. The polysilicon layer may be evaporated or sputtered.

The overall thickness of the gate dielectric is very thin and is typically 10 to 50 angstroms at the current state of the art. For these reasons, these devices are susceptible to the penetration of dopants through the gate dielectric into the n-channel, thereby changing the gate threshold voltage and degrading the quality of the Si / SiO ₂ interface. The silicon nitride layer acts as a barrier to boron diffusion, thereby improving the manufacturing yield of the process. In the composite layer of the present invention, the preferred thickness of the SiO ₂ growth layer is 3-20 angstroms, the Si ₃ N ₄ deposition layer is 4-50 angstroms, and the SiO ₂ deposition layer is 3-20 angstroms. The overall thickness of the dielectric stack is between 10-90 angstroms, preferably 10-50 angstroms. The exact thickness depends on the device technical requirements.

The method for producing the composite dielectric layer of the present invention is described according to the following sequence of steps.

The silicon substrate is placed in a conventional LPCVD furnace, the furnace is heated to 800 ° C. and lowered to a pressure of 900 mTorr. The oxidizing gas is oxygen in a nitrogen carrier gas having an oxygen flow late of 1.9 slm. Growth proceeds for 60 minutes to produce an oxide layer with a thickness of 10 angstroms.

Immediately thereafter, the pressure in the furnace is adjusted to 65 mTorr and the temperature of the furnace is adjusted to 750 ° C. A silicon nitride layer is deposited on the SiO ₂ growth layer by flowing ammonia and dichlorosilane into the furnace at 22.5 sccm and 7.5 sccm, respectively. This deposition proceeds for 10 minutes to produce a silicon nitride layer having a thickness of 20 angstroms.

Following nitride deposition, the furnace temperature and pressure are maintained at the previous stages, and a SiO ₂ layer is deposited on the silicon nitride layer by flowing N ₂ O and SiH ₂ Cl ₂ into the furnace at 15 sccm and 7.5 sccm, respectively. This deposition proceeds for 10 minutes to deposit a SiO ₂ layer having a thickness of 10 Angstroms.

The composite dielectric stack is annealed at 900 ° C. for 30 seconds in N ₂ . The temperature increases at a rate of 50 ° C./min. The total annealing time including this increase period is 7 minutes. In general, the temperature is increased at a rate of at least 25 ℃ / min is preferably maintained for 5 seconds to 5 minutes in the range of 800-1100 ℃, the shorter the annealing time the higher the annealing temperature. The atmosphere used for annealing can be an inert gas or an oxidizing gas with a sparse concentration. In the latter case, the silicon substrate will be very slightly oxidized, which will increase the thickness of the grown oxide layer. For the general conditions described above, the additional thickness is typically a few angstroms, but the additional thickness may break down in the overall process design.

Electrical performance is described by comparing the electrical data of a MOS device with a composite gate dielectric according to the present invention and a MOS device with a standard SiO ₂ gate dielectric. For convenience, a device having an oxide-nitride-oxide composite gate dielectric of 30 Angstroms and a device having a 40 Angstrom SiO ₂ (O) gate dielectric is compared. However, as shown, since the gate dielectric is thicker in some tests, a gate dielectric of 40 angstroms is generally expected to show better performance, but due to the improved quality of the composite gate dielectric, the performance data shows at least the same result. have.

FIG. 7 illustrates the gate driving current I _D and the gate leakage current I _G according to the voltage. Curve 71 represents I _D data and curve 72 represents I _G data. In this case the transistor has a channel dimension of 0.24 μm × 15 μm. V _DS is 1.8 volts. The dashed curve represents the performance data of a 40 Angstrom SiO ₂ (O) gate dielectric and the solid line represents the 30 Angstrom composite (ONO) gate dielectric shown in accordance with the present invention. Saturation current (I _D ) at 1.8 volts is 0.402 mA / μm for ONO devices and 0.381 mA / μm for O devices. The measured threshold voltage (V _T ) is 0.47 volts for ONO devices and 0.48 volts for O devices. The current I _off in the off state is 2.4 pA / μm in the ONO device and 3.4 pA / μm in the O device. Peak transconductance is 374 mS / mm for ONO devices, 345 mS / mm for O devices, and S is equal to 78 for both devices.

8 is a diagram of transconductance (g _m (S)) vs. V _GS (V) comparing an ONO device (solid curve) and an O device (dashed curve). Curve 81 is for the NMOS device and curve 82 is for the PMOS device.

9 shows device lifetime data in relation to NMOS DC lifetime versus substrate current I _sus (A). The device is stressed at 4 volts. In addition, the data of the ONO device is shown by the solid line curve, and the data of the O device is shown by the dotted line curve. Curve 91 represents data measured to be 10% lower in g _m and curve 92 represents data measured to be lower in I _D-sat . Device operating life at 1.8 volts is 8.2 x 10 ⁴ years.

As described above, the present invention has a high dielectric constant for the thickness, effectively blocks boron diffusion from the boron doped polysilicon gate through the gate dielectric, treats all layers of the composite in situ and anneales the LPCVD layer. By removing the remaining hydrogen, the quality of the interface between the SiO ₂ / Si ₃ N ₄ layers and the SiO ₂ layer and the silicon substrate is preserved.

Those skilled in the art will recognize various additional modifications of the invention. All variations that basically rely on the basic principles of the present technology and corresponding principles from the specific description herein are considered to be within the scope of the present invention.

Claims (12)

a. Forming a field oxide on a portion of the silicon substrate leaving the selected device region uncovered; b. Forming a dielectric layer on the silicon substrate in the selected device region; c. Depositing a polysilicon gate layer on the dielectric layer in the selected device region; d. Etching the polysilicon layer to produce a silicon gate over a portion of the gate of the dielectric layer in the device region, leaving a portion of the dielectric layer covering the source and drain regions in the substrate exposed; e. Implanting impurity into the source and drain regions using the silicon gate as a mask; f. Forming electrical contacts in the source and drain regions, The dielectric layer is a composite layer of silicon dioxide, silicon nitride and silicon dioxide, 10-50 angstroms thick, Iii. Growing a silicon dioxide layer on the silicon substrate; Ii. Depositing a silicon nitride layer on the silicon dioxide growth layer; Iii. Depositing a silicon dioxide layer on the silicon nitride deposition layer to form the composite layer; Iii. Immediately after the step iii, annealing the composite layer by heating the composite layer to a temperature of at least 800 ° C. for at least 5 seconds in an inert atmosphere, The step of 실행 is carried out in a low pressure furnace, which continuously maintains a low pressure state, Method of manufacturing a silicon gate field effect transistor. The method of claim 1, And the source and drain are implanted through the exposed region of the dielectric layer. The method of claim 1, Etching the exposed regions of the dielectric layer to expose the source and drain regions, wherein the impurities are implanted into the exposed source and drain regions. The method of claim 1, And the silicon dioxide growth layer has a thickness of 5-20 angstroms. The method of claim 4, wherein And the silicon nitride layer has a thickness of 5-50 angstroms. The method of claim 5, And the silicon dioxide deposited layer has a thickness of 5-20 angstroms. The method of claim 6, And a total thickness of said dielectric layer is 10-50 Angstroms. The method of claim 1, Wherein steps ii and iii are performed by low pressure chemical vapor deposition. a. Forming a field oxide on a portion of the silicon substrate leaving the selected device region uncovered; b. Forming a dielectric layer on the silicon substrate in the selected device region; c. Depositing a polysilicon gate layer on the dielectric layer in the selected device region; d. Etching the polysilicon layer to produce a silicon gate over the gate portion of the dielectric layer in the device region, leaving a portion of the dielectric layer covering the source and drain regions in the substrate exposed; e. Implanting impurity into the source and drain regions using the silicon gate as a mask; f. Forming electrical contacts in the source and drain regions, The dielectric layer is a composite layer of silicon dioxide growth layer, silicon nitride deposition layer and silicon dioxide deposition layer, having a thickness of 10-50 angstroms, Iii. Positioning the silicon substrate in a low pressure chemical vapor deposition reactor; Ii. Adjusting the temperature in the reactor to 500-900 ° C., Iii. Adjusting the pressure in the reactor to 700-950 mTorr, Iii. Injecting an oxidizing gas into the reactor to grow a first silicon dioxide growth layer on the silicon substrate; Iii. Adjusting the temperature in the reactor to 600-900 ° C., Iii. Adjusting the pressure in the reactor to 10-100 mTorr; Iii. Injecting precursor gases for silicon nitride into the reactor to deposit a silicon nitride layer on the first silicon dioxide growth layer; Iii. By injecting precursor gases for silicon dioxide into the reactor to deposit a second silicon dioxide deposition layer on the silicon nitride deposition layer, Forming a composite layer essentially comprising a silicon dioxide growth layer, a silicon nitride deposition layer, and a silicon dioxide deposition layer; Iii. Immediately after the step iii, annealing the composite layer by heating the composite layer at a temperature of at least 800 ° C. in an inert atmosphere to manufacture the silicon gate field effect transistor. The method of claim 9, Precursor gases for depositing the silicon nitride layer are ammonia and dichlorosilane. The method of claim 10, Precursor gases for the silicon dioxide deposition layer are silane dichloride and N ₂ O. The method of claim 11, And the oxidizing gas used to grow the silicon dioxide growth layer is selected from the group consisting of O ₂ , NO, and N ₂ O.