JPH0642547B2 - Nonvolatile semiconductor memory and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory and a method for manufacturing the same, and more particularly, to rewritable information having a control gate and a floating gate. The present invention relates to a dedicated memory cell and a method for forming the same.

(Prior Art) Nonvolatile semiconductor memory such as EPROM (Erassable Pro)
When writing information to a grammable read only memory) memory cell, the control gate is set to a positive high potential to form a channel on the substrate surface, and a positive voltage is applied to the drain. At this time, the electrons traveling in the channel receive high energy due to the high electric field generated in the vicinity of the drain, and the electrons are injected into the floating gate over the energy barrier due to the insulating film below the floating gate. The state in which the injection is performed is the write state.

By the way, in order to miniaturize the structure of the memory cell, when the channel length is shortened to form a channel length in the submicron region, not only during the write operation of applying a high voltage as described above, A high electric field is generated in the vicinity of the drain even during the read operation executed at a relatively low voltage. Due to the generation of a high electric field during such a read operation, erroneous writing of electrons into the floating gate may occur and the stored data may be destroyed, and there is a problem that reliability is deteriorated during long-time operation. .

Therefore, in order to avoid such a malfunction during the read operation, a memory cell having a structure as shown in FIG. 7 is considered. That is, in the figure, 71 is a P-type silicon substrate, and 72 and 73 are N ^{+ serving as a} source and a drain.
A diffusion layer, 74 is a gate insulating film, 75 is a floating gate, and 76 is a control gate, and an N ⁻ diffusion layer 77 is formed in contact with the channel side of the N ⁺ diffusion layer 73 to be the drain. Since the electric field in the drain region can be relaxed by the presence of the N ⁻ diffusion layer 77, it is possible to prevent the above-described malfunction during the read operation.

However, the cell structure using the low-concentration region (N ⁻ diffusion layer 77) having a low impurity concentration as described above has a serious drawback that the writing characteristics are poor. That is, since the drain electric field is lowered by the N ⁻ diffusion layer 77, sufficient energy cannot be given to the electrons traveling in the channel region,
This is because the efficiency of injecting electrons into the floating gate 75 decreases.

In order to solve the above-mentioned problems, the applicant of the present application has already proposed in Japanese Patent Application No. 308610/1986.
According to this proposal, by forming an N ⁺ region in the surface region of the N ⁻ diffusion layer 77, the current is increased to the above N level during a write operation.
^The floating gate 75 now flows to the ⁺ area.
It is possible to increase the efficiency of injecting electrons into.

However, during the write operation, since a channel path is likely to occur in a deep portion of the channel region, it is difficult to generate a sufficiently high electric field in the drain portion, and it is inevitable that the efficiency of injecting electrons into the floating gate is sufficiently high. I can't say.

(Problems to be Solved by the Invention) According to the present invention, as described above, the conventional non-volatile memory cell having the floating gate has a problem that its write characteristic is deteriorated when attempting to prevent malfunction during a read operation. SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile semiconductor memory which can prevent a malfunction during a read operation and has good write characteristics, and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving Problems) A nonvolatile semiconductor memory of the present invention has a drain (or at least one of a source) in a nonvolatile memory cell having a floating gate, which is closer to a channel region side than the above region. A low-concentration low-concentration region, a high-concentration region higher in concentration than the low-concentration region on the surface of the low-concentration region, and the low-concentration region between the low-concentration region and the semiconductor substrate. It is characterized in that a region having the same conductivity type as that of the semiconductor substrate and having a higher concentration than that of the semiconductor substrate is formed in a region deeper into the substrate than the region.

Further, in the method for manufacturing a nonvolatile semiconductor memory of the present invention, after the floating gate of the memory cell is formed, at least the floating gate is used as a mask to form a region having a higher concentration than that of the semiconductor substrate. Ions of the first impurity are implanted into the semiconductor substrate, then ions of the second impurity having a conductivity type opposite to that of the semiconductor substrate are implanted into the semiconductor substrate, and then the second impurities are implanted at different dose amounts.
Ions of impurities of are implanted into the semiconductor substrate, then a silicon oxide film is deposited on the side surface of the floating gate,
At least the floating gate is used as a mask to implant a second impurity ion into the semiconductor substrate to form a source or a drain.

(Operation) According to the nonvolatile memory cell having the above-described impurity concentration distribution, the drain electric field becomes low due to the presence of the low concentration region during the read operation, and the channel current flows in the low concentration region, and the floating current flows. The efficiency of electron injection into the gate is reduced, and the occurrence rate of erroneous writing is reduced. In addition, during a write operation in which a high voltage is applied to the drain and the control gate, a high drain electric field is generated in the high concentration region adjacent to the drain, and the channel current passes through the high concentration region, so that hot carriers are not generated. Increase. Furthermore, the presence of the high-concentration region of the same conductivity type as the semiconductor substrate makes it possible to suppress the occurrence of a channel path in the deep part of the channel region between the source and drain when a high voltage is applied to the drain. Therefore, a high electric field is easily generated in the drain portion.

(Embodiment) An N-channel EP according to an embodiment of the present invention will be described below with reference to the drawings.
The case of application to ROM will be described in detail.

FIGS. 1A to 1G show a sectional structure of a part of a semiconductor wafer in the EPROM manufacturing process. In this manufacturing process, first, as shown in FIG. 1A, a desired element isolation region 2 is formed on a semiconductor substrate 1 by a normal element isolation method, and a gate insulating film 3 is formed in the element region. Next, after performing ion implantation for controlling the threshold voltage of the cell in a desired area of the planned cell area, as shown in FIG. 1 (b), the first polycrystalline silicon film 4 is formed on the entire surface of the substrate by the LPCVD method (decompression). Formed to a thickness of 2000Å by vapor phase epitaxy,
A silicon oxide film 5 is formed on the polycrystalline silicon film 4 by a thermal oxidation method so as to have a thickness of 150Å. Furthermore, after forming the silicon nitride film 6 to a thickness of 150Å by the LPCVD method, an EPROM cell (memory cell) is formed.
A resist pattern 7 having a desired pattern is formed to form the floating gate, and the silicon nitride film 6, the silicon oxide film 5, and the first polycrystalline silicon film 4 are processed by using the resist pattern 7 as a mask. At this time, the cross-sectional structure of the memory cell region for forming the memory cell is
The cross-sectional structure of the peripheral region, which is typically shown by the left side portion of FIG.
As shown by the right side portion of FIG. 2B, the first polycrystalline silicon film 4, the silicon oxide film 5, the silicon nitride film 6 are formed.
Have been removed respectively. Next, after removing the resist pattern 7 and performing ion implantation of desired impurities for threshold control according to the type of MIS FET (insulated gate type field effect transistor) used in the peripheral circuit, the peripheral region The gate oxide film 3 is removed and the substrate 1 is washed. next,
The entire substrate is thermally oxidized to form a silicon oxide film 3'to a thickness of 300Å on the substrate as shown in FIG. 1 (c), and at the same time, the first polycrystalline silicon film 4 in the memory cell region is formed. 10 on the silicon nitride film 6 formed above
The silicon oxide film 8 is formed so as to have a thickness of about 15Å. At this time, a silicon oxide film 9 is formed on the side surface of the first polycrystalline silicon film 4 by oxidation thereof. Then LP
The second polycrystalline silicon film 10 is formed on the entire surface of the substrate by the CVD method.
To have a thickness of 3000Å. Then the first
As shown in FIG. 3D, L is formed on the second polycrystalline silicon film 10.
The oxynitride film 11 is formed to have a thickness of 1000Å by the PCVD method. The processing conditions at this time were such that the vacuum degree was 200 Pa, the reaction gas was SiH ₂ Cl ₂ , N ₂ O and NH _{3 so} that the flow rate ratio was 100: 250: 500, and the temperature was 800 ° C. is there. Here, in the cross section shown in FIG. 1 (d), the memory cell region shows a cross section along the line AA ′ in the cross section shown in FIG. 1 (c), and thereafter, FIG. A cross section in the same direction as d) is shown. Then, using a known exposure technique, a desired resist pattern (not shown)
And a resist pattern for the word line in the memory cell region and a resist pattern for the polycrystalline silicon gate of the peripheral circuit FET are formed at the same time. Using this resist pattern as a mask, as shown in FIG. The nitride film 11, the second polycrystalline silicon film 10, the silicon oxide film 8, the silicon nitride film 6 and the silicon oxide film 5 are selectively etched. Next, the resist pattern is removed, and after cleaning the substrate, the peripheral area is covered with a resist,
Using the oxynitride film 11 as a mask, the first polycrystalline silicon film 4 in the memory cell region is selectively etched. In this way, the memory cell region word line (control gate) made of the second polycrystalline silicon film 10 and the memory cell region floating gate made of the peripheral region / gate electrode and the first polycrystalline silicon film 4 are formed. It Next, using the control gate and the floating gate 4 as a mask, 80
Boron (B) ions were implanted at a dose of 5 × 10 ¹² cm ^-2 with an accelerating voltage of keV, and subsequently 2 × 10 ¹⁴ cm ^{-2 at} 40 keV.
Arsenic (As) ions are implanted, and 1 at 50 keV
^Implant arsenic (As) ions of × 10 ¹³ cm ^-2 . At this time, ion implantation can be performed also in the N-channel MOS FET formation portion in the peripheral region, similarly to the memory cell region.
Next, the silicon oxide films 3 and 3'exposed after the etching of the second and first polycrystalline silicon films 10 and 4 are removed, and the entire surface of the substrate is washed. Next, as shown in FIG. 1 (f), a silicon oxide film 12 is formed on the surface of the silicon substrate by 300
It is formed in an O ₂ atmosphere at 950 ° C. so as to have a thickness of Å, and a silicon oxide film 13 is formed on the substrate surface by the LPCVD method.
It is formed to have a thickness of 0Å. Next, the silicon oxide film 12 is etched by anisotropic dry etching to leave the silicon oxide film 13 on the side surface of the polycrystalline silicon pattern. Next, after cleaning the substrate, the source region and the drain region of the N-channel MOS FET in the peripheral region and the source region and the drain region of the memory cell transistor in the memory cell region are provided with a dose amount of 5 × 10 ¹⁵ cm ^-2 at 40 keV. Inject arsenic ions (or phosphorus ions).
Next, the entire substrate is covered with SiO ₂ by a CVD method as an insulating film for coating.
Form the film to a thickness of 3000Å, and then add PSG
(Phosphorus silicate glass) film is formed to have a thickness of 10000Å, annealed at 950 ° C for 30 minutes for activation, and then a contact hole for electrode wiring is opened to form a desired aluminum wiring to form an EPROM. Form. The EPROM cell in the EPROM thus formed has a sectional structure as shown in FIG. That is, two types of N ⁻ diffusion layers 14 and 15 having different diffusion depths and different impurity concentrations are formed in a double layer on the substrate below the source side edge portion and the drain side edge portion of the floating gate 4. There is. The N ⁻ diffusion layers 14 and 15 have a lower concentration than the N ⁺ diffusion layers 16 and 17 in the source / drain regions and are in contact with the source / drain regions, respectively. In this case, the N ⁻ diffusion layer 15 on the upper side (substrate surface side) has a higher impurity concentration than the N ⁻ diffusion layer 14 on the lower side. Further, a P ⁺ diffusion layer 18 is formed in contact with the channel regions of the N ⁻ diffusion layers 14 and 15.

In the above structure, a typical impurity concentration distribution under the gate edge on the drain side is the depth when the depth of the substrate is represented by X and the horizontal position along the substrate surface is represented by Y as shown in FIG. 2 (a). The direction is as shown in FIG. 2 (b), and the horizontal direction is as shown in FIG. 2 (c). The rate of change of the N-type impurity concentration in the depth direction is characterized in that it gradually increases as the substrate depth increases and has a maximum value P at a certain depth, as shown in FIG. In addition, in FIGS. 2B and 2C, the concentration of the P-type impurity (boron) decreases as the substrate depth increases, and the concentration decreases from the drain toward the channel side.

According to the EPROM cell having the above structure, since the high-concentration P ⁺ diffusion layer 18 is formed between the source 16 and the drain 15 and the channel region, so-called punch-through occurs even if a high drain voltage is applied. It is difficult for the phenomenon called electrons to flow in the deep part of the substrate. Therefore, a high voltage can be applied to the drain during the write operation, the drain electric field can be increased, and the efficiency of injecting electrons into the floating gate 4 can be increased. further,
On the channel side of the source / drain, an N ⁻ diffusion layer 15 having a slightly higher concentration exists inside the low concentration N ⁻ diffusion layer 14. As a result, during a read operation with a low gate voltage, the electrons traveling in the channel are less affected by the gate potential at the gate edge portion, and the low concentration N
^- down deep direction of the substrate at the diffusion layer 14, the N ^- comes to pass through the diffusion layer 14. Therefore, the drain electric field is lowered, and hot electrons are generated more deeply in the substrate, so that the arrival rate of electrons to the floating gate 4 is reduced. On the other hand, during the write operation, since a high gate voltage is applied, the electrons traveling in the channel are more strongly affected by the gate potential under the gate edge, and thus continue to flow on the substrate surface.
It passes through the high concentration N ⁻ diffusion layer 15. As a result, the electrons pass through a portion of a higher electric field, and the location where hot electrons are generated shifts to the surface side. Therefore, the efficiency of injecting electrons into the floating gate 4 is increased, and the writing characteristic is improved.

Further, according to the manufacturing process as described above, the EPROM cell having the above effects can be realized by a combination of known manufacturing techniques. Moreover, since the oxynitride film 11 is used as a mask when selectively etching the first polycrystalline silicon film 4 in the step shown in FIG. 1 (e), for example, a SiO ₂ film is used as a mask. As compared with the above case, the side etch amount of the polycrystalline silicon film 4 can be reduced, and there is an advantage that the workability is improved.

Note that the present invention is not limited to the above embodiment,
^{As the} step of forming the diffusion layers 14 and 15, arsenic and arsenic are ion-implanted in the above-mentioned embodiment, but phosphorus (P) arsenic may be ion-implanted. In this case, the typical impurity distribution under the gate edge on the drain side is as shown in FIG. 4 in the X direction and the second impurity distribution in the Y direction.
It is similar to that shown in FIG. In the above case, E
The cross-sectional structure of the PROM cell is shown in Fig. 5.
Compared with the above embodiment shown in (g), the N ⁻ diffusion layer 14
And the N ⁺ diffusion layers 16 and 17, the depth relation and the distribution of the impurity concentration in the depth direction under the gate edge are slightly different, and the other parts are the same, and therefore the same reference numerals are given.

Further, in the above-described embodiment, the N ⁻ diffusion layers 14 and 15 are provided on the drain side and the source side, respectively, but they may be provided only on the drain side as shown in FIG. In this case, as a manufacturing process, the SiO ₂ film 1 by the CVD method is formed on the side surface of the polycrystalline silicon pattern for the floating gate 4.
A layer of mask is added before forming 3 and arsenic is added to the source side of the memory cell region only, for example, 40 keV, 2 × 10 ¹⁵ c
This can be achieved by implanting ions at a high dose of m ^-2 . According to such an EPROM cell structure, since the N ⁻ diffusion layers 14 and 15 on the source side do not exist, there is an advantage that the parasitic resistance due to this is reduced and the memory cell current is increased. In addition, the source and drain are used in reverse for writing and reading (that is, the source side N ⁺ diffusion layer 16 is used as a drain during writing, and the N ⁻ diffusion layers 14 and 15 are provided for reading). The drain side N ⁺ diffusion layer 17 is used as the drain)
It is possible to improve the reliability of the EPROM cell.

Further, the nonvolatile semiconductor memory of the present invention is not limited to a memory integrated circuit, but can be an on-chip memory device such as a memory-embedded device.
Applicable to memory as well, not only EPROM but also batch erase type E ² P
Of course, it can be applied to ROM and the like.

[Effects of the Invention] As described above, according to the present invention, it is possible to prevent malfunction during a read operation, increase hot carriers during a write operation, and suppress occurrence of a channel path in a deep portion of a channel region. Thus, it is possible to provide a non-volatile semiconductor memory having excellent write characteristics and a method for manufacturing the same.

[Brief description of drawings]

1 (a) to 1 (g) are views showing a part of a wafer cross section in each step according to an embodiment of a method for manufacturing a nonvolatile semiconductor memory of the present invention, and FIGS. 2 (a) and 2 (b). , (C) are diagrams showing the impurity concentration distribution in the substrate depth direction below the gate edge of the drain and in the direction along the substrate surface in the EPROM cell of FIG. 1 (g).
FIG. 5 is a diagram showing the rate of change of the N-type impurity concentration in FIG. 2 (a), FIG. 5 is a sectional view showing an EPROM cell according to another embodiment of the present invention, and FIG. 4 is a diagram showing the cell of FIG. FIG. 6 is a diagram showing the impurity concentration distribution in the substrate depth direction below the gate edge of the drain,
FIG. 7 is a sectional view showing an EPROM cell according to still another embodiment of the present invention, and FIG. 7 is a sectional view showing a conventional EPROM cell. 1 ... P-type semiconductor substrate, 3, 5, 6, 8 ... Insulating film, 4 ... Floating gate, 10 ... Control gate, 11
... Oxynitride film, 12, 13 ... Silicon oxide film, 14, 15 ... N ^- diffusion layer, 16, 17 ... N ⁺ diffusion layer, 18 ... P ⁺ diffusion layer

Claims (3)

[Claims] 1. A semiconductor substrate of a first conductivity type, and the first substrate formed on a surface region of the semiconductor substrate at positions separated from each other to serve as a source or drain region, respectively.
The first and second semiconductor regions of the second conductivity type opposite to the conductivity type and the insulating film formed on the channel region between the first and second semiconductor regions are separated from each other by the insulating film. And a floating gate and a control gate provided on the channel region side of the at least one of the first and second semiconductor regions, and the second conductivity type having a lower concentration than the first or second semiconductor region. Of the third semiconductor region and a surface region of the third semiconductor region.
A fourth semiconductor region of the second conductivity type having a higher concentration than that of the semiconductor region, and a region deeper from the substrate surface than the third semiconductor region between the third semiconductor region and the semiconductor substrate. ,
A non-volatile semiconductor memory comprising: a fifth semiconductor region having the same conductivity type as that of the semiconductor substrate and having an impurity concentration higher than that of the substrate. 2. A step of forming a polycrystalline silicon gate pattern to be a floating gate of a non-volatile memory cell on an insulating film on a semiconductor substrate, and at least the same conductive type as the semiconductor substrate using the polycrystalline silicon gate pattern as a mask. A first ion implantation step of implanting first impurity ions, and a second ion implantation step of implanting second impurity ions of a conductivity type opposite to that of the semiconductor substrate, and then the second ion implantation step. Third ion implantation step of implanting ions of the second impurity at a dose lower than that of the ion implantation step of, and then forming a silicon oxide film on the side surface of the floating gate, and at least after the step. Using the polycrystalline silicon gate pattern as a mask, ions of the second impurity having a dose higher than that of the second ion implantation step described above are used. The fourth to be injected
2. A method for manufacturing a non-volatile semiconductor memory, comprising: 3. Boron ions are implanted in the first ion implantation step, arsenic ions are implanted in the second ion implantation step, and arsenic ions or phosphorus ions are implanted in the third ion implantation step. The method for manufacturing a nonvolatile semiconductor memory according to claim 2, wherein arsenic ions or phosphorus ions are implanted in the fourth ion implantation step.