JPH05343703A - Manufacture of nonvolatile memory - Google Patents

Manufacture of nonvolatile memory

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Publication number
JPH05343703A
JPH05343703A JP17498092A JP17498092A JPH05343703A JP H05343703 A JPH05343703 A JP H05343703A JP 17498092 A JP17498092 A JP 17498092A JP 17498092 A JP17498092 A JP 17498092A JP H05343703 A JPH05343703 A JP H05343703A
Authority
JP
Japan
Prior art keywords
memory
forming
film
region
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17498092A
Other languages
Japanese (ja)
Other versions
JP3397804B2 (en
Inventor
Katsuhiko Nishiwaki
克彦 西脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP17498092A priority Critical patent/JP3397804B2/en
Publication of JPH05343703A publication Critical patent/JPH05343703A/en
Application granted granted Critical
Publication of JP3397804B2 publication Critical patent/JP3397804B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Non-Volatile Memory (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To reduce a leakage current caused by a parasitic MOS transistor in a bird's beak region, by forming a first conductivity-type impurity layer once again after a memory gate electrode is formed. CONSTITUTION:In an element isolation region 13, impurity ions are implanted and a first impurity layer 11 is formed. A selective oxidization step is carried out to form an element isolation insulating film 15. A memory gate insulating film 19 is formed, and a memory nitride film 21 and a top insulating film 23 are formed, and moreover a memory electrode 25 is formed. After impurity ions are implanted in a semiconductor substrate 33, the memory gate electrode 25 is oxidized to form a mask oxide film 27 in a heat treatment step. At the same time, a first conductivity type impurity is diffused in the semiconductor substrate 33 by using this heat treatment step. Consequently, a second impurity layer 29, which is of the same conductivity type as that of the first impurity layer 11 and has an impurity density higher than this impurity layer 11, is formed right under a bird's beak.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、不揮発性メモリの製造
方法に関し、とくにメモリ特性の向上と安定化および高
信頼性を備える不揮発性メモリの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile memory, and more particularly to a method for manufacturing a non-volatile memory having improved and stable memory characteristics and high reliability.

【0002】[0002]

【従来の技術】従来例の不揮発性メモリの製造方法を、
図3を用いて説明する。図3は、メモリトランジスタの
チャネル幅方向の断面図を示す。
2. Description of the Related Art A conventional non-volatile memory manufacturing method is described below.
This will be described with reference to FIG. FIG. 3 shows a cross-sectional view of the memory transistor in the channel width direction.

【0003】まず第1導電型の半導体基板33に、この
半導体基板33と同じ導電型の第1の不純物層11を素
子分離領域13に形成する。さらに選択酸化を行い、素
子分離領域13に二酸化シリコン膜からなる素子分離絶
縁膜15を形成する。この素子分離絶縁膜15の形成時
に、素子領域17と素子分離領域13との境界に、鳥の
くちばしのような形状を有するバーズビークが形成され
る。
First, a first conductivity type semiconductor substrate 33 is formed with a first conductivity type impurity layer 11 of the same conductivity type as the semiconductor substrate 33 in the element isolation region 13. Further, selective oxidation is performed to form an element isolation insulating film 15 made of a silicon dioxide film in the element isolation region 13. At the time of forming the element isolation insulating film 15, a bird's beak having a shape like a bird's beak is formed at the boundary between the element region 17 and the element isolation region 13.

【0004】その後、素子領域17に、二酸化シリコン
膜からなるメモリゲート絶縁膜19と、窒化膜からなる
メモリナイトライド膜21と、二酸化シリコン膜からな
るトップ絶縁膜23と、多結晶シリコン膜からなるメモ
リゲート電極25とを順次形成する。
Thereafter, in the element region 17, a memory gate insulating film 19 made of a silicon dioxide film, a memory nitride film 21 made of a nitride film, a top insulating film 23 made of a silicon dioxide film, and a polycrystalline silicon film. The memory gate electrode 25 is sequentially formed.

【0005】その後、メモリゲート電極25を熱酸化す
ることによってマスク酸化膜27を形成する。その後、
このメモリゲート電極25をマスクとして、第2の導電
型のソースおよびドレインを形成し、不揮発性メモリ素
子を形成する。
After that, the mask oxide film 27 is formed by thermally oxidizing the memory gate electrode 25. afterwards,
Using the memory gate electrode 25 as a mask, a second conductivity type source and drain are formed to form a nonvolatile memory element.

【0006】[0006]

【発明が解決しようとする課題】不揮発性メモリは、メ
モリゲート電極25に充分高い正電圧を印加すると、半
導体基板33のシリコン単結晶の伝導帯の電子が、メモ
リゲート絶縁膜19をトンネル現象によって通り、メモ
リナイトライド膜21にトラップされる。その結果、メ
モリトランジスタのしきい値電圧が変化して、メモリ特
性を得ている。
In the non-volatile memory, when a sufficiently high positive voltage is applied to the memory gate electrode 25, electrons in the conduction band of the silicon single crystal of the semiconductor substrate 33 tunnel through the memory gate insulating film 19 by a tunneling phenomenon. Therefore, it is trapped in the memory nitride film 21. As a result, the threshold voltage of the memory transistor changes and the memory characteristic is obtained.

【0007】従来例の製造方法による不揮発性メモリに
おいても、前述したようにメモリゲート電極25に充分
高い正電圧を印加し、メモリナイトライド膜21中に負
の電荷を蓄積させる。このときメモリトランジスタのし
きい値電圧は、エンハンス動作となる。
Also in the nonvolatile memory manufactured by the conventional manufacturing method, a sufficiently high positive voltage is applied to the memory gate electrode 25 to accumulate negative charges in the memory nitride film 21, as described above. At this time, the threshold voltage of the memory transistor becomes an enhancing operation.

【0008】この状態で、メモリゲート電極25に電圧
を徐々に印加すると、素子領域17ではしきい値が高く
なっているので電流は流れないが、素子領域17と素子
分離領域13との境界のバーズビーク領域の寄生MOS
トランジスタは、低いメモリゲート電極の印加電圧で電
流が流れ、リーク電流となる。
In this state, when a voltage is gradually applied to the memory gate electrode 25, no current flows because the threshold value in the element region 17 is high, but the boundary between the element region 17 and the element isolation region 13 does not flow. Parasitic MOS in bird's beak region
A current flows through the transistor at a low voltage applied to the memory gate electrode, which causes a leak current.

【0009】図2に示す従来例におけるゲート電圧とド
レイン電流との関係を示すグラフの破線31に、この一
例を示す。メモリトランジスタの低いゲート電圧で、リ
ーク電流となるドレイン電流が流れてる。
An example of this is shown by a broken line 31 in the graph showing the relationship between the gate voltage and the drain current in the conventional example shown in FIG. A drain current, which is a leak current, is flowing at a low gate voltage of the memory transistor.

【0010】この図2のグラフに示すように、低いゲー
ト電圧でリーク電流が生じると、メモリ特性において書
き込み幅が狭くなるという問題点が発生する。
As shown in the graph of FIG. 2, when a leak current is generated at a low gate voltage, there arises a problem that the writing width becomes narrow in the memory characteristic.

【0011】本発明の目的は、前述の課題点を解決する
ことであり、バーズビーク領域の寄生MOSトランジス
タに起因するリーク電流を低減して、安定した特性を有
する不揮発性メモリの製造方法を提供することである。
An object of the present invention is to solve the above-mentioned problems and to provide a method for manufacturing a nonvolatile memory having stable characteristics by reducing the leak current caused by a parasitic MOS transistor in a bird's beak region. That is.

【0012】[0012]

【課題を解決するための手段】この目的を達成するため
に本発明の不揮発性メモリの製造方法は、下記記載の製
造方法を採用する。
In order to achieve this object, the manufacturing method of the nonvolatile memory of the present invention employs the manufacturing method described below.

【0013】本発明の不揮発性メモリの製造方法は、第
1導電型の半導体基板の素子分離領域に第1導電型の第
1の不純物層を形成する工程と、選択酸化を行うことに
より素子分離領域に二酸化シリコン膜からなる素子分離
絶縁膜を形成する工程と、素子領域に二酸化シリコン膜
からなるメモリゲート絶縁膜を形成する工程と、メモリ
ゲート絶縁膜上にメモリナイトライド膜を形成する工程
と、メモリナイトライド膜の上に二酸化シリコン膜から
なるトップ絶縁膜を形成する工程と、メモリゲート電極
を形成する工程と、メモリゲート電極の整合した領域の
半導体基板に第1導電型の第2の不純物層を形成する工
程と、メモリゲート電極の整合した領域の半導体基板に
第2導電型のソース領域およびドレイン領域を形成する
工程と、二酸化シリコンを主体とする多層配線用絶縁膜
を形成する工程と、ホトリソグラフィーとエッチングに
より多層配線用絶縁膜にコンタクト窓を形成する工程
と、配線金属を形成する工程を有することを特徴とす
る。
The method of manufacturing a nonvolatile memory according to the present invention comprises a step of forming a first impurity layer of a first conductivity type in an element isolation region of a semiconductor substrate of a first conductivity type, and element isolation by performing selective oxidation. A step of forming an element isolation insulating film made of a silicon dioxide film in the region, a step of forming a memory gate insulating film made of a silicon dioxide film in the element region, and a step of forming a memory nitride film on the memory gate insulating film A step of forming a top insulating film made of a silicon dioxide film on the memory nitride film, a step of forming a memory gate electrode, and a second conductivity type second film on the semiconductor substrate in a region aligned with the memory gate electrode. A step of forming an impurity layer, a step of forming a second conductivity type source region and a drain region in the semiconductor substrate in a region where the memory gate electrodes are aligned, And having a step of forming an insulating multilayer wiring film mainly made of Con, forming a contact window in the insulating film for multilayer wiring by photolithography and etching, the step of forming a wiring metal.

【0014】[0014]

【作用】本発明における不揮発性メモリの製造方法にお
いては、メモリゲート電極形成後、第1導電型の不純物
層を再度形成することで、バーズビーク部の不純物濃度
を高くしている。このためバーズビーク領域の不純物濃
度を高くすることによって、寄生MOSのトランジスタ
の低いゲート電圧側での動作を抑制させ、リーク電流を
低減する。
In the method of manufacturing a nonvolatile memory according to the present invention, the impurity concentration of the bird's beak portion is increased by forming the impurity layer of the first conductivity type again after forming the memory gate electrode. Therefore, by increasing the impurity concentration in the bird's beak region, the operation of the parasitic MOS transistor on the low gate voltage side is suppressed and the leak current is reduced.

【0015】[0015]

【実施例】以下図面を用いて本発明の実施例を説明す
る。図1(a)、(b)は本発明の不揮発性メモリの製
造方法の各工程における、メモリトランジスタのメモリ
ゲート電極のチャネル方向での断面図を示し、図1
(c)はメモリトランジスタの平面図を示す。
Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B are cross-sectional views in the channel direction of a memory gate electrode of a memory transistor in each step of the method for manufacturing a nonvolatile memory according to the present invention.
(C) shows a plan view of the memory transistor.

【0016】まずはじめに図1(a)に示すように、導
電型がP型の半導体基板33に、化学気相成長法(CV
D法)により、厚さ75nm程度の窒化膜(図示せず)
を形成し、ホトリソグラフィ−とエッチングにより、素
子領域17にのみ、窒化膜からなる耐酸化膜を形成す
る。
First, as shown in FIG. 1A, a P type semiconductor substrate 33 is formed on a semiconductor substrate 33 by chemical vapor deposition (CV).
A nitride film (not shown) having a thickness of about 75 nm by the D method).
Then, an oxidation resistant film made of a nitride film is formed only in the element region 17 by photolithography and etching.

【0017】その後、この窒化膜をイオン注入の阻止膜
として、素子分離領域13にイオン注入法によりボロン
の不純物イオンをたとえば4×1013atoms/cm
- 2のイオン注入量で半導体基板33の素子分離領域1
3に導入し、第1の不純物層11を形成する。
Thereafter, using this nitride film as a blocking film for ion implantation, impurity ions of boron are implanted into the element isolation region 13 by ion implantation, for example, 4 × 10 13 atoms / cm 3.
- isolation region 1 of the semiconductor substrate 33 by ion implantation of 2
Then, the first impurity layer 11 is formed.

【0018】その後、素子領域17上に形成した窒化膜
を耐酸化膜として用いて、水蒸気雰囲気中で温度100
0℃時間160分の選択酸化を行うことにより、素子分
離領域13に二酸化シリコン膜からなる素子分離絶縁膜
15を厚さ750nm形成する。その後、耐酸化膜とし
て用いた窒化膜は、除去する。
After that, the nitride film formed on the element region 17 is used as an oxidation resistant film, and the temperature is set to 100 in a water vapor atmosphere.
By performing selective oxidation at 0 ° C. for 160 minutes, an element isolation insulating film 15 made of a silicon dioxide film having a thickness of 750 nm is formed in the element isolation region 13. After that, the nitride film used as the oxidation resistant film is removed.

【0019】つぎに酸化性雰囲気中において、酸化処理
を行って素子領域17の表面に、厚さ3nm程度の二酸
化シリコン膜からなるメモリゲート絶縁膜19を形成す
る。
Then, an oxidation treatment is performed in an oxidizing atmosphere to form a memory gate insulating film 19 made of a silicon dioxide film having a thickness of about 3 nm on the surface of the element region 17.

【0020】その後、化学気相成長法(CVD法)にて
窒化膜からなるメモリナイトライド膜21を厚さ12n
m形成する。
After that, a memory nitride film 21 made of a nitride film is formed to a thickness of 12 n by chemical vapor deposition (CVD method).
m.

【0021】その後、メモリナイトライド膜21を、水
蒸気雰囲気中にて酸化することにより、二酸化シリコン
からなるトップ絶縁膜23を厚さ4nm程度形成する。
After that, the memory nitride film 21 is oxidized in a water vapor atmosphere to form a top insulating film 23 made of silicon dioxide with a thickness of about 4 nm.

【0022】その後、CVD法にてメモリゲート電極2
5として多結晶シリコン膜を450nm程度の膜厚で形
成する。
After that, the memory gate electrode 2 is formed by the CVD method.
5, a polycrystalline silicon film is formed with a film thickness of about 450 nm.

【0023】その後、フォトリソグラフィーとエッチン
グとにより、メモリゲート電極25をパターニングす
る。
Then, the memory gate electrode 25 is patterned by photolithography and etching.

【0024】次に図1(b)、(C)に示すように、メ
モリゲート電極25をイオン注入の阻止膜として用い、
イオン注入法によりボロンからなる不純物イオンを、注
入量1×1013atoms/cm- 12の条件で半導体基
板33に導入する。
Next, as shown in FIGS. 1B and 1C, the memory gate electrode 25 is used as a blocking film for ion implantation,
Impurity ions consisting of boron by the ion implantation method, the injection amount 1 × 10 13 atoms / cm - introducing the 12 semiconductor substrate 33 under the conditions of.

【0025】その後、酸化性雰囲気中で温度1000℃
時間20分でメモリゲート電極25を酸化することによ
って、マスク酸化膜27を膜厚20nm程度形成する。
Thereafter, the temperature is 1000 ° C. in an oxidizing atmosphere.
By oxidizing the memory gate electrode 25 for 20 minutes, a mask oxide film 27 having a film thickness of about 20 nm is formed.

【0026】このマスク酸化膜27を形成する熱処理を
利用して、前述のイオン注入法によりバーズビーク領域
に導入した第1導電型の不純物であるボロンを、半導体
基板33に拡散させる。
By utilizing the heat treatment for forming the mask oxide film 27, the boron, which is the first conductivity type impurity introduced into the bird's beak region by the ion implantation method described above, is diffused into the semiconductor substrate 33.

【0027】この結果、第1の不純物層11と同じ導電
型で第1の不純物層11よりさらに不純物濃度の高い第
2の不純物層29をバーズビークの直下の領域に形成す
る。
As a result, a second impurity layer 29 having the same conductivity type as that of the first impurity layer 11 and a higher impurity concentration than that of the first impurity layer 11 is formed in the region immediately below the bird's beak.

【0028】次にメモリゲート電極25をイオン注入の
阻止膜として、半導体基板33と逆導電型の不純物とし
て、たとえばリン、ヒ素などの不純物イオンを、イオン
注入量3×1015atoms/cm- 12程度の条件でイ
オン注入を行って、半導体基板33にソース領域および
ドレイン領域(図示せず)を形成する。
[0028] Next, the memory gate electrode 25 as a blocking film for ion implantation, an impurity of the semiconductor substrate 33 and the opposite conductivity type, for example phosphorus, impurity ions such as arsenic ion implantation amount 3 × 10 15 atoms / cm - 12 Ion implantation is carried out under the conditions described above to form a source region and a drain region (not shown) in the semiconductor substrate 33.

【0029】以後の工程は一般的な方法により、二酸化
シリコンを主体とする多層配線用絶縁膜を形成して、フ
ォトリソグラフィーとエッチングにより多層配線用絶縁
膜にコンタクト窓を形成し、その後配線金属としてアル
ミニウム(Al)を形成することによって不揮発性メモ
リを形成する。
In the subsequent steps, a multi-layer wiring insulating film mainly composed of silicon dioxide is formed by a general method, a contact window is formed in the multi-layer wiring insulating film by photolithography and etching, and then as a wiring metal. A nonvolatile memory is formed by forming aluminum (Al).

【0030】[0030]

【発明の効果】以上の説明で明らかなように、本発明の
不揮発性メモリの製造方法において、寄生MOSトラン
ジスタが形成される、バーズビーク領域の不純物濃度を
高くすることによって、よりいっそう寄生MOSトラン
ジスタのしきい値電圧は高くなる。
As is apparent from the above description, in the method of manufacturing a nonvolatile memory of the present invention, the impurity concentration of the bird's beak region in which the parasitic MOS transistor is formed is increased to further increase the parasitic MOS transistor. The threshold voltage becomes high.

【0031】本発明のメモリトランジスタのゲート電圧
とドレイン電流との関係を、図2のグラフに示す。図2
に示すように、本発明の特性を示す実線35のように、
低いゲート電圧でのリーク電流となるドレイン電流は発
生しない。この結果、メモリ特性において、メモリゲー
ト電極に正電圧を印加した場合、よりエンハンス動作と
なり、書き込み幅が増加する。このため記憶保持時間の
増加と、プログラム時間の短縮とが可能となり、従来と
比較してメモリ特性および信頼性が向上し、より安定し
た特性を有する不揮発性メモリ素子を得ることができ
る。
The relationship between the gate voltage and the drain current of the memory transistor of the present invention is shown in the graph of FIG. Figure 2
As shown by the solid line 35 indicating the characteristics of the present invention,
No drain current, which is a leak current at a low gate voltage, is generated. As a result, in the memory characteristics, when a positive voltage is applied to the memory gate electrode, the operation becomes more enhanced and the writing width increases. Therefore, it is possible to increase the storage retention time and shorten the programming time, improve the memory characteristics and reliability as compared with the conventional one, and obtain a non-volatile memory element having more stable characteristics.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例における不揮発性メモリの製造
方法を示す図面である。
FIG. 1 is a diagram showing a method for manufacturing a nonvolatile memory according to an embodiment of the present invention.

【図2】本発明と従来例におけるメモリトランジスタの
ゲ−ト電圧とドレイン電流との関係を示すグラフであ
る。
FIG. 2 is a graph showing a relationship between a gate voltage and a drain current of a memory transistor according to the present invention and a conventional example.

【図3】従来例における不揮発性メモリの製造方法を示
す断面図である。
FIG. 3 is a cross-sectional view showing a method for manufacturing a nonvolatile memory in a conventional example.

【符号の説明】[Explanation of symbols]

11 第1の不純物層 13 素子分離領域 17 素子領域 19 メモリゲ−ト絶縁膜 21 メモリナイトライド膜 23 トップ絶縁膜 25 メモリゲート電極 29 第2の不純物層 11 First Impurity Layer 13 Element Separation Region 17 Element Region 19 Memory Gate Insulation Film 21 Memory Nitride Film 23 Top Insulation Film 25 Memory Gate Electrode 29 Second Impurity Layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型の半導体基板の素子分離領域
に第1導電型の第1の不純物層を形成する工程と、選択
酸化を行うことにより素子分離領域に二酸化シリコン膜
からなる素子分離絶縁膜を形成する工程と、素子領域に
二酸化シリコン膜からなるメモリゲート絶縁膜を形成す
る工程と、メモリゲート絶縁膜上にメモリナイトライド
膜を形成する工程と、メモリナイトライド膜の上に二酸
化シリコン膜からなるトップ絶縁膜を形成する工程と、
メモリゲート電極を形成する工程と、メモリゲート電極
の整合した領域の半導体基板に第1導電型の第2の不純
物層を形成する工程と、メモリゲート電極の整合した領
域の半導体基板に第2導電型のソース領域およびドレイ
ン領域を形成する工程と、二酸化シリコンを主体とする
多層配線用絶縁膜を形成する工程と、ホトリソグラフィ
ーとエッチングにより多層配線用絶縁膜にコンタクト窓
を形成する工程と、配線金属を形成する工程を有するこ
とを特徴とする不揮発性メモリの製造方法。
1. A step of forming a first impurity layer of a first conductivity type in an element isolation region of a semiconductor substrate of a first conductivity type, and element isolation comprising a silicon dioxide film in the element isolation region by performing selective oxidation. Forming an insulating film, forming a memory gate insulating film made of a silicon dioxide film in the element region, forming a memory nitride film on the memory gate insulating film, and forming a memory nitride film on the memory nitride film. A step of forming a top insulating film made of a silicon film,
Forming a memory gate electrode; forming a second impurity layer of the first conductivity type on the semiconductor substrate in a region where the memory gate electrode is aligned; and forming a second conductivity layer on the semiconductor substrate in a region where the memory gate electrode is aligned. A source region and a drain region of the mold, a step of forming an insulating film for a multi-layer wiring mainly composed of silicon dioxide, a step of forming a contact window in the insulating film for a multi-layer wiring by photolithography and etching, and a wiring A method of manufacturing a non-volatile memory, comprising a step of forming a metal.
JP17498092A 1992-06-09 1992-06-09 Manufacturing method of nonvolatile memory Expired - Fee Related JP3397804B2 (en)

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JP17498092A JP3397804B2 (en) 1992-06-09 1992-06-09 Manufacturing method of nonvolatile memory

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JP17498092A JP3397804B2 (en) 1992-06-09 1992-06-09 Manufacturing method of nonvolatile memory

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JPH05343703A true JPH05343703A (en) 1993-12-24
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2004084314A1 (en) * 2003-03-19 2006-06-29 富士通株式会社 Semiconductor device and manufacturing method thereof
JP5047786B2 (en) * 2005-04-27 2012-10-10 スパンション エルエルシー Manufacturing method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2004084314A1 (en) * 2003-03-19 2006-06-29 富士通株式会社 Semiconductor device and manufacturing method thereof
JP4721710B2 (en) * 2003-03-19 2011-07-13 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US8304310B2 (en) 2003-03-19 2012-11-06 Fujitsu Semiconductor Limited Manufacture method of semiconductor device
JP5047786B2 (en) * 2005-04-27 2012-10-10 スパンション エルエルシー Manufacturing method of semiconductor device

Also Published As

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