KR950011027B1 - Making method of semiconductor memory device - Google Patents

Abstract

No content.

Description

Manufacturing method of semiconductor memory device

1 is a cross-sectional view taken along a line A-A of FIG. 2 showing a memory cell of an EEPROM as a first embodiment to which the present invention is applied.

2 is a plan view of the memory cell of the first embodiment.

3 is an equivalent circuit diagram of a memory cell array of the first embodiment.

4 to 16 are cross-sectional views or plan views in the manufacturing process of the memory cell of the first embodiment.

17 and 18 are cross-sectional views of memory cells according to another embodiment of the present invention, respectively.

19 to 23 are cross-sectional views in the manufacturing process of the memory cell of the embodiment of FIG.

24 to 27 are cross-sectional views of memory cells according to another embodiment of the present invention, respectively.

28 is a cross-sectional view taken along the line A-A of FIG. 27;

29 is an equivalent circuit diagram of a memory cell array of the embodiment of FIG.

30 to 35 are plan views or cross-sectional views in the manufacturing process of the memory cell of the embodiment of FIG.

36 is a sectional view of a memory cell of another embodiment of the present invention.

37 to 41 are sectional views in the manufacturing process of the memory cell of the embodiment of FIG.

42 to 44 are cross sectional views of memory cells according to another embodiment of the present invention, respectively.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device. In particular, a memory cell includes a MISFET having a floating gate electrode and a control gate electrode, and is an electrically erasable ROM (Read Only Memory) device, that is, an EEPROM (Electrically Erasable and Programmable ROM). The present invention relates to a valid technology.

EEPROM memory cells, which consist of MISFETs (Metal Inaslator Semiconductor Field Effect Trensistors) with floating gate electrodes and control gate electrodes, are described, for example, in the Technical Digest, pp. 468-pp. 417.

In the memory cell, a strong electric field of 10 MV / cm or more is applied to the thin oxide layer to tunnel the electrons from the substrate to the floating gate through the thin oxide layer under the floating gate, or to tunnel the electrons to the substrate from the floating gate.

In order to tunnel electrons sufficient to write or erase information, it is necessary to have a large overlap area between the floating gate and the control gate. The memory cell is composed of two elements, a memory transistor and a select transistor. For this reason, the memory cell is about five times larger than a memory cell of an EPROM having the same floating gate and control gate. Thus, in order to make the cell size small, having a floating gate electrode and a control gate electrode, injection (light) of electrons to the floating gate is performed by injection of hot electrons generated at the edge of the drain region, and emission of electrons from the floating gate (erasing) ) Is proposed as a one-element memory cell that is tunneled to the source region (Technical Digest, pp. 616-619, 1985 International Electron Devices Meeting).

Since the memory cell performs light by generating hot electrons at the edge of the drain region in a state where a drain current flows, it is necessary to generate many thermal carriers when the drain junction breaks down.

On the other hand, in erasing, it is necessary to apply a voltage of about 10 V or more to the source region to create a tunnel between the floating gate and the source region. For this reason, the breakdown voltage between the source region and the substrate should be 10 V or more, so as not to cause an avalanche breakdown during erasing.

According to our investigation, it is difficult to have the same structure as the source region and the drain region of the MISFET which is a memory cell, and it is necessary to have a structure suitable for each.

In addition, since the light of the memory cell uses hot electrons, power consumption at the time of writing is large.

According to our research, in order to reduce power consumption and short write time, that is, to improve light efficiency with a small current, the edge of the drain region needs to have a structure in which hot electrons are likely to occur.

On the other hand, the EEPROM is in the direction of writing and erasing with a single 5V power supply, and it is common to generate high voltages for writing and erasing by a boost circuit provided in the same chip. For this reason, it is necessary to improve the light efficiency as a small current.

An object of the present invention is to provide a method of manufacturing a semiconductor memory device having a memory cell which has good write efficiency and is surely erased.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device having a memory cell with improved erase characteristics by increasing the breakdown voltage between the source region and the substrate.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device having a memory cell capable of high speed operation.

An outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the method of manufacturing a semiconductor memory device according to an embodiment of the present invention includes a control gate electrode, a floating gate electrode, a second gate insulating film formed between two gate electrodes, and a first gate formed between the semiconductor substrate and the floating gate electrode. A memory cell comprising an insulating film, first and second semiconductor regions formed in the semiconductor substrate, and channel regions formed between the first and second semiconductor regions in the semiconductor substrate, wherein the memory cells are formed from the floating gate electrode to the first semiconductor region. The carrier is discharged by tunneling through the first gate insulating film, by tunneling through a predetermined potential in the second semiconductor region, and a predetermined potential is applied to the second semiconductor region. A method for manufacturing a semiconductor memory device for reading information in a semiconductor region, the method comprising: a semiconductor substrate of a first conductivity type Forming a floating gate electrode on the first gate insulating film on the second gate insulating film, a second gate insulating film on the floating gate electrode, and a control gate electrode on the second gate insulating film so that both ends thereof overlap each other; Forming a first semiconductor region of the second conductivity type in the semiconductor substrate by introducing impurities into the semiconductor substrate in a self-aligning manner, and introducing impurities into the semiconductor substrate by introducing impurities in a self-aligning manner to the other end of the control gate electrode. The second conductive region of the second conductivity type is formed so that the overlap amount between the second semiconductor region and the floating gate electrode is smaller than the overlap amount between the first semiconductor region and the floating gate electrode.

In addition, according to the embodiment described above, the method of manufacturing the semiconductor memory device according to the present invention includes the floating gate electrode on the first gate insulating film on the first conductive semiconductor substrate and the second gate on the floating gate electrode. Forming a control gate electrode on both the insulating film and the second gate insulating film so that both ends thereof overlap each other; and introducing impurities into one end of the control gate electrode and the floating gate electrode in a self-aligned manner to form a second conductive layer in the semiconductor substrate. A step of forming a first semiconductor region of a type, and a self-aligned impurity introduced into both ends of the control gate electrode and the floating gate electrode, and having a higher impurity concentration and a smaller junction length than the first semiconductor region in the semiconductor substrate. The same impurity is introduced into the first semiconductor region while the second conductive region of the second conductivity type is formed. In the semiconductor substrate on the side of the first and second semiconductor regions, impurities are introduced into the semiconductor substrates on the side of the first and second semiconductor regions by self-aligning impurities at both ends of the process and control gate electrode and floating gate electrode. A second conductive type having a deeper junction depth than the second semiconductor region is provided with a step of forming a third semiconductor region.

In addition, a method of manufacturing a semiconductor memory device according to still another embodiment of the present invention includes a control gate electrode, a floating gate electrode, a second gate insulating film formed between two gate electrodes, and a first gate formed between a semiconductor substrate and a floating gate electrode. A memory cell comprising an insulating film, first and second semiconductor regions formed in the semiconductor substrate, a channel region formed between the first and second semiconductor regions in the semiconductor substrate, and a MISFET constituting a peripheral circuit. A method of manufacturing a semiconductor memory device in which carriers are discharged from a gate electrode to a first semiconductor region by tunneling through a first gate insulating film, wherein the semiconductor is formed in a memory cell formation region of a semiconductor substrate of a first conductivity type. Floating gate electrode on first gate insulating film on substrate, second gate insulating film on floating gate electrode On the second gate insulating film, the control gate electrodes are formed so that both ends thereof overlap each other, and in the peripheral circuit forming region of the semiconductor substrate, a gate elimination film of the MISFET on the semiconductor substrate and a gate electrode of the MISFET on the gate insulating film are formed. Forming a first semiconductor region of a second conductivity type in the semiconductor substrate by introducing impurities self-aligned to one end of the control gate electrode and the floating gate electrode, following the memory cell formation region of the semiconductor substrate; In the peripheral circuit forming region of the semiconductor substrate, a second conductive type and source of MISFET having impurity concentration lower than that of the first semiconductor region in the semiconductor substrate by introducing impurities into both ends of the gate electrode in a self-aligned manner; Forming a first region to be used as a drain region, forming a peripheral circuit of the semiconductor substrate In the inverse and memory cell regions, sidewall spacers are formed self-aligning to both ends of the gate electrode of the MISFET, and sidewall spacers are formed self-aligning at both ends of the control gate electrode and the floating gate electrode. In the peripheral circuit forming region and the memory cell region of the semiconductor substrate, impurities are introduced into each end portion of the gate electrode of the MISFET, and both ends of the control gate electrode and the floating gate electrode in a self-aligned manner, so that impurities are removed from the first region. And forming a third semiconductor region of the second conductivity type having a high concentration and a deep junction depth.

According to the above means, it is possible to manufacture a memory cell which has a high speed and is efficiently improved in writing and erasing in the semiconductor memory device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

Best Mode for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 show an EEPROM as a first embodiment to which the present invention is applied. FIG. 1 is a cross-sectional view taken along line AA of the memory cell array shown in FIG. 2, and FIG. 2 is a part of the memory cell array. 3 is an equivalent circuit diagram of a memory cell array. In FIG. 2, in order to make the configuration of the memory cell easier to see, an insulating film other than the field insulating film is not shown, and a part of the conductor layer is omitted, and the semiconductor region 9, the insulating film 12, and the semiconductor region ( A part of 11) is omitted.

The outline of this EEPROM will be explained with reference to FIG.

The memory cell Qm is composed of a MISFET having a floating gate electrode and a control gate electrode. The control gate electrode of the MISFET Qm is connected to the word line WL. The drain region of the MISFET Qm is connected to the data line DL, and the source region of the MISFET Qm is connected to the ground potential line GL. The data line DL and the ground line GL are parallel to each other and are formed in the direction intersecting the word line WL. That is, the memory cell array is composed of memory cell Qm, word line WL, data line DL and ground line GL.

One end of the word line WL is connected to an X decoder X-DEC which is a word line selection circuit. One end of the data line DL is connected to the drive circuit DR of the data line DL, and the other end thereof is connected to the input / output circuits DOB and DIB through the n-channel MISFET Qc constituting the column switch circuit. The output of the Y decoder Y-DEC, which is a data line selection circuit, is supplied to the gate electrode of the MISFET Qc. The ground line GL is supplied with the output of the CMOS inverter circuit IV consisting of p-channel MISFET Qs ₁ and n-channel MISFET Qs ₂ . The erase signal is applied to the input terminal of the inverter circuit IV, that is, the gate electrode of the MISFET Qs ₁ and Qs ₂ . Is supplied. The output circuit DOB including the sense amplifier circuit amplifies the signal given to the data line DL selected in the read operation, and outputs it to the external terminal I / O for input / output. In the write operation, the input circuit DIB supplies a signal supplied to an external terminal to the data line DL. Circuits other than the memory cell array, i.e., peripheral circuits, are composed of CMOS circuits such as inverter circuit IV to perform a static operation.

The EEPROM is written, read and erased as follows.

Inverter circuit IV signal The ground potential Vss of the circuit, for example, 0 V, is applied to the ground line GL through the MISFET Qs ₂ which is turned on by the high level of the signal. The erase potential Vpp, for example, 14V, is applied at the time of erasing information through the MISFET Qs ₁ which is turned on by the low level of. When erasing information, all word lines WL and all data lines DL are signaled. Low level is achieved by the circuits X-DEC and Y-DEC. In other words, in this embodiment, the contents of all the memory cells Qm are erased at once.

In the write operation, the power supply potential Vcc (for example, 5 V) is supplied from the write circuit DIB to one selected data line DL. Prior to this, all data lines DL are plied to the ground potential Vss (for example, 0V) of the circuit in advance by the driving circuit DR. In the read operation, all the data lines DL are precharged to the power supply potential Vcc in advance by the driving circuit DR. Thereafter, another potential appears in the data line DL in the memory of the selected memory cell Qm.

In the write operation, a high voltage Vpp (e.g. 14V) equal to or greater than the power supply voltage Vcc is supplied to the selected word line WL by the decoder X-DEC. In the read operation, a high level signal of the power supply voltage Vcc (or less) is applied to the selected word line WL at the decoder X-DEC. When the threshold value of the MISFET of the memory cell Qm is lower than the selection level of the word line WL, the potential of the data line DL decreases at the potential Vcc by turning on the MISFET Qm. If the threshold level of the MISFET Qm is higher than the selection level of the word line WL, the data line DL maintains the precharge level by turning off the MISFET Qm.

The write operation, that is, injection of the column carrier, is performed only in one memory cell to which the potential Vpp is applied to the word line WL and the potential Vcc is applied to the data line DL. In other memory cells, no thermal carrier is injected.

In addition, the high potential Vpp may be supplied from an external terminal during write operation, or may be generated from the power supply voltage Vcc by a built-in booster circuit.

As shown in FIGS. 1 and 2, the memory cell MISFET Qm has a first gate insulating film 4, a floating gate electrode 5, a second gate insulating film 6, a control gate electrode 7, and n ^+. It consists of the type semiconductor region 9, the n ⁺ type semiconductor region 10, and the n ⁻ type semiconductor region 11. The first gate insulating film 4 is made of a silicon oxide film by thermal oxidation of the surface of the semiconductor substrate 1, and has a film thickness of about 100 GPa. The floating gate electrode 5 is made of a polycrystalline silicon film and is provided on the first gate insulating film 4. The second gate insulating film 6 is formed of a silicon oxide film by thermal oxidation of the surface of the polysilicon film, which is the floating gate electrode 5, and has a film thickness of about 250 to 350 kPa. The control gate electrode 7 is made of, for example, a polycrystalline silicon film of the second layer, and is formed on the surface of the second gate insulating film 6. The control gate electrodes 7 of several MISFET Qm are integrally formed to form a word line WL and extend on the field insulating film 2.

The drain region is composed of an n ⁺ type semiconductor region 9 and an n ⁺ type semiconductor region 10. Drain regions of two memory cells connected to the same data line DL through the same connection hole 14 are integrally formed. The edge on the channel region side of the drain region is constituted by the n ⁺ type semiconductor region 9 having a shallow junction depth of about 0.1 mu m. For this reason, the overlap below the floating gate electrode 5 in the drain region is taken. In addition, compared with the case where the semiconductor region 9 is a semiconductor region having a low impurity concentration, the electric field at the edge of the channel region side of the drain region at the time of writing can be strengthened. The length in the channel length direction of the n ⁺ type semiconductor region 9 is defined by a sidewall spacer (insulating film) 12 made of a silicon oxide film. The portion falling from the channel region of the drain region is composed of the n ⁺ type semiconductor region 10 having a deep junction of about 0.25 μm. The source region is composed of an n ⁺ type semiconductor region 9, an n ⁺ type semiconductor region 10, and an n ⁻ type semiconductor region 11.

The n ⁺ semiconductor regions 9, 10 and n ⁻ type semiconductor regions 11 constituting these source regions constitute the ground potential line GL. The ground potential line GL extends between two memory cells connected to the same data line DL through two adjacent connection holes 14 in the direction in which the word line WL extends. The edge on the channel region side of the source region is constituted by the shallow n ⁺ type semiconductor region 9, and the overlap to the bottom of the floating gate electrode 5 is reduced. The length in the channel length direction of the n ⁺ type semiconductor region 9 is defined by the sidewall spacers 12. The surface portion of the portion away from the channel region is composed of the n ⁺ type semiconductor region 10 having a deep junction. An n ⁻ type semiconductor region 11 is provided between the n ⁺ type semiconductor region 9 and the n ⁺ type semiconductor region 10 and the semiconductor substrate 1, in particular, the channel region of the MISFET Qm. This increases the breakdown voltage of the junction between the source region and the semiconductor substrate 1.

The surface of the semiconductor substrate 1 exposed by the field insulating film 2 and the floating gate electrode 5 and the surface of the floating gate electrode 5 and the control gate electrode 7 are exposed by the silicon oxide film 8. Covering. A sidewall spacer 12 made of a silicon oxide film is provided on the silicon oxide film 8 on the side of the floating gate electrode 5 and the control gate electrode 7.

Reference numeral 13 is an insulating film made of, for example, a silicate glass (PSG) film, and covers the semiconductor substrate 1. The insulating film 13 on the portion over the n ⁺ type semiconductor region 10 that is part of the drain region is selectively removed to form the connection hole 14. The connection hole 14 is connected to the n ⁺ type semiconductor region 10 that is part of the drain region of the data line DL made of an aluminum film. The junction depth of the portion to which the data line DL of the n ⁺ type semiconductor region 10 is connected is deeper than other portions. Although not shown, a protective film composed of, for example, a PSG film by CVD and a silicon nitride film formed thereon is covered. The write of information to the memory cell generates a thermal carrier at the edge of the n ⁺ type semiconductor region 9 which is a part of the drain region by applying the above-mentioned potential to each region, thereby causing double column electrons to float. By injection). The information is erased as described above, and is discharged by electrons held in the floating gate electrode 5 through the first gate insulating film 4 to the n ⁺ type semiconductor region 9 which is a source region through a tunnel. .

In the erasing operation, it is preferable that the threshold voltage of the memory element after erasing is substantially constant at a positive value (enhanced type), for example, about 1V. In the case where the erased MISFET Qm is an enhancement type, the memory cell can be a device type consisting of the MISFET Qm. For this reason, in this embodiment, in the erase operation, a low potential of about 0.5 V to 1.5 V is applied to all the data lines DL in the driving circuit DR. This potential is determined in consideration of the rise of the floating gate potential due to coupling with the erasing potential Vpp of the ground potential line GL, the substrate effect, and the threshold voltage after erasing the MISFET Qm.

According to the memory cell of this embodiment, the n ^- type semiconductor region 11 is formed between the n ⁺ -type semiconductor regions 9 and 10 constituting the source region and the semiconductor substrate 1 to break between them. Since the down voltage becomes high, the erase voltage applied to the source region at the time of erasing information can be increased. This makes it possible to improve characteristics such as erasing time of information or reliability of erasing. Since the edge of the source region is composed of the n ⁺ type semiconductor region 9 with a shallow junction, the overlap of the floating gate electrode 5 becomes smaller, so that the capacitance between the source region and the floating gate electrode 5 can be reduced. There is a number. As a result, the voltage applied to the first gate insulating film 4 can be increased by the voltage applied to the n ⁺ type semiconductor region 9 constituting the source region at the time of erasing the information, thereby improving the erasing characteristic of the information. You can do it.

The edge between the drain region and the floating region of the floating gate electrode 5 can be reduced by forming an edge on the channel region side of the drain region with a shallow junction of n ⁺ type semiconductor region 9, so that the read speed of information can be improved. have.

By setting the semiconductor region 9 having the shallow junction of the edge of the drain region to n ⁺ type, the electric field of the drain region edge at the time of writing can be stronger as compared with the case where the n ^- type is formed. As a result, since the heat carrier can be generated efficiently, the write voltage can be reduced.

By forming the edge of the drain region with the n ⁺ type semiconductor region 9 having a shallow junction, the overlap to the lower portion of the floating gate electrode 5 becomes small, so that the short channel effect can be prevented.

The manufacturing method of the memory cell of the first embodiment will be described.

4 to 16 except for FIG. 7 are sectional views in the manufacturing process of the first part and the same part, and FIG. 7 is a plan view in the manufacturing process of the second part and the same part.

As shown in FIG. 4, a silicon oxide film 18 is formed by thermal oxidation of the main surface of the p ⁻ type semiconductor substrate 1, and a silicon nitride film 19 by CVD is selectively formed thereon. . The field insulating film 2 is formed by thermally oxidizing a predetermined surface of the semiconductor substrate 1 using the silicon nitride film 19 as a mask. The p-type channel stopper 3 is formed by ion implantation using the silicon nitride film 19 as a mask prior to forming the field insulating film 2 by introducing p-type impurities such as boron. After the field insulating film 2 is formed, the silicon nitride film 19 and the silicon oxide film 18 are removed.

Next, as shown in FIG. 5, the surface of the semiconductor substrate 1 exposed by the field insulating film 2 is thermally oxidized to form the first gate insulating film 4 of the above-described film thickness made of a silicon oxide film. .

Next, as shown in FIG. 6, in order to form the floating gate electrode 5, the polycrystalline silicon film 5 is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. In order to reduce the resistance of the polycrystalline silicon film 5, n-type impurities such as phosphorus (P) are introduced by thermal diffusion, ion implantation, or the like.

Next, as shown in FIG. 7, the direction in which the data gate DL extends at a predetermined interval by the floating gate electrode 5 by etching using the polycrystalline silicon film 5 as a resist film (not shown). Pattern to extend. That is, in this etching process, the polycrystalline silicon film 5 is patterned in the pattern which integrated the floating gate electrodes 5 of several memory cells connected to the same data line DL. The polycrystalline silicon film 5 formed in the peripheral circuit region is removed. After patterning the polycrystalline silicon film 5, the mask made of a resist film is removed.

Next, as shown in FIG. 8, the surface of the polycrystalline silicon film 5 is oxidized to form a second gate insulating film 6 made of a silicon oxide film. The film thickness is about 250 ~ 350Å. This oxidation process forms a gate insulating film of the MISFET constituting the peripheral circuit. Next, in order to form the control gate electrode 7 and the word line WL, a polycrystalline silicon film 7 is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. In order to reduce the resistance of the polycrystalline silicon film 7, n-type impurities such as phosphorus are introduced by thermal diffusion, ion implantation, or the like.

Next, as shown in FIG. 9, the polycrystalline silicon film 7 is etched by etching using a mask made of a resist film (not shown) to form the control gate electrode 7 and the word line WL. This etching process also forms the gate electrode of the MISFET of the peripheral circuit. Following the etching, the second gate insulating film 6 exposed by the floating gate electrode 7 is etched. In addition, the polycrystalline silicon film 5 is etched to form the floating gate electrode 5. After this series of etching, the mask made of the resist film is removed. In addition, the gate electrode of the control gate electrode roll gate electrode 7, the word line WL and the MISFET of the peripheral circuit is a high melting point metal film such as Mo, W, Ta, Ti, or the like, or a silicide film thereof or a polycrystalline silicon film. Or it may be a two-layer film in which a silicide film is laminated.

Next, as shown in FIG. 10, the exposed surfaces of the floating gate electrode 5 and the control gate electrode 7 (word line WL) are thermally oxidized to form a silicon oxide film 8. By this oxidation, the surface of the semiconductor substrate 1 exposed by the floating gate 5 and the control gate electrode 7 is oxidized to form a silicon oxide film 8.

Next, as shown in FIG. 11, a mask 20 made of a resist film for forming the n ⁻ type semiconductor region 11 is formed on the semiconductor substrate 1. The mask 20 also covers the peripheral circuit area. Next, an n-type impurity, for example, phosphorus is introduced into the exposed portion of the semiconductor substrate 1 by ion implantation at a dose of about 1 × 10 ¹² 1 × 10 ¹⁴ atoms / cm ² , and the n ⁻ -type semiconductor region (11) is formed. After the ion implantation, the mask 20 is removed. Thereafter, the n ⁻ type semiconductor region 11 may be extended by annealing so as to have a deeper junction than the n ⁺ type semiconductor region 10 formed later.

Next, as shown in FIG. 12, with the floating gate electrode 5 and the control gate electrode 7 as a mask, 1 × of n-type impurities, for example, arsenic, are deposited on the surface of the semiconductor substrate 1 by ion implantation. The n ⁺ type semiconductor region 9 is formed by introducing a dose of about 10 ¹⁵ atoms / cm ² .

During ion implantation, the peripheral circuit region is covered with a mask made of a resist film, and ion implantation is carried out only in the memory cell region, and the memory cell region is covered with a mask made of a resist film, and n-type impurities, for example, are covered in the peripheral circuit region. For example, by implanting phosphorus at a dose of about 1 × 10 ¹³ atoms / cm ² , the source and drain regions of the n-channel MISFET constituting the peripheral circuit may be LDD (Lightlly Doped Drain). In this case, the mask made of the resist film provided in the peripheral circuit region is removed after ion implantation.

Next, as shown in FIG. 13, the silicon oxide film 12 for forming the sidewall spacers 12 is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD.

Next, as shown in FIG. 14, the silicon oxide film 12 is etched by reactive ion etching (RIE) until the surface of the semiconductor substrate 1 is exposed to form sidewall spacers 12. Next, as shown in FIG. Sidewall spacers 12 are also formed on the side of the gate electrode of the MISFET for forming the peripheral circuit. The surface of the semiconductor substrate 1 exposed to the etching is oxidized again to form a silicon oxide film 8.

Next, as shown in FIG. 15, n-type impurities, for example, arsenic, are formed by ion implantation using the floating gate electrode 5, the control gate electrode 7, and the sidewall spacer 12 as a mask. The n ⁺ type semiconductor region 10 is formed by introducing a dose of about 10 ¹⁶ atoms / cm ² . This ion implantation process also forms a high-concentration layer in the source drain region of the n-channel MISFET in the peripheral circuit. In addition, the region where the p-channel MISFET of the peripheral circuit is formed is covered by a mask made of a resist film so that the n-type impurities are not introduced. The mask made of this resist film is removed after ion implantation. Although not shown after the formation of the n-channel MISFET, the n-channel MISFET region and the memory cell Qm region of the peripheral circuit are covered with a mask made of a resist film, and p-type impurities are formed in the p-channel MISFET region of the peripheral circuit by ion implantation. For example, boron is introduced to form a source drain region of the p-channel MISFET. The mask made up of the n-channel MISFET and the resist film covering the memory cell Qm region is removed after the p-type impurity is introduced.

Next, as shown in FIG. 16, an insulating film 13 made of a PSG film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. Thereafter, the data lines DL made of the connecting holes 14 and the aluminum film 15 shown in FIGS. 1 and 2 and the final protective film (not shown) are formed.

As described above, according to the manufacturing method of the present embodiment, the memory cell can be formed in substantially the same process as the n-channel MISFET forming the peripheral circuit.

The n ⁻ type region 11 formed only on the source side may be formed as shown in FIG. 17. That is, the n ⁻ type semiconductor region 11 is formed shallow, so that only the n ⁺ type semiconductor region 9 is covered (included) by the n ⁻ type semiconductor region 11, and the lower portion of the n ⁺ type semiconductor region 10. Prevents the n ⁻ type semiconductor region 11 from being formed. Since the depth of the n ⁻ type semiconductor region 1 is shallow, the diffusion into the channel region is also small. Therefore, the variation of the threshold value of the memory cell MISFET Qm is reduced, thereby improving the electrical characteristics. In addition, since the short channel effect is reduced, the characteristics of the memory cell are improved.

^n-type semiconductor region 11 is n the process of claim 11 degrees of the ^{embodiment-may} be formed shallow, so as to cover only the n ⁺ -type semiconductor region 9 as the type semiconductor region 11 as described above. Therefore, the memory cell Qm of this embodiment can also be formed in substantially the same process as the n-channel MISFET of the peripheral circuit.

18 is a sectional view of a memory cell of another embodiment of the present invention.

In this embodiment, the edge on the channel region side of the source region is composed of a relatively low concentration n-type semiconductor region 21, and the edge on the channel region side of the drain region is a high concentration n ⁺ type semiconductor region 9 with a shallow junction. It is composed. An avalanche breakdown voltage between the source region, that is, the n ⁺ -type semiconductor region 10 and the n-type semiconductor region 21 and the semiconductor substrate 1, wherein the edge of the source region is composed of the n-type semiconductor region 21. This is high. This can increase the erase voltage applied to the source region at the time of erasing the information. In addition, the n-type semiconductor region 21 is formed to a depth of about 0.2㎛.

On the other hand, since the channel region side of the drain region is the n ⁻ type semiconductor region 9, the electric field applied between the n ⁺ type semiconductor region 9 and the semiconductor substrate 1 can be strengthened. Therefore, the generation of thermal carriers at the time of writing information can be increased.

The length in the channel longitudinal direction of the n ⁺ type semiconductor region 9 and the n type semiconductor region 21 is defined by the sidewall spacers 12.

Next, a manufacturing method of the memory cell of the embodiment of FIG. 18 will be described. 19 through 23 are cross-sectional views of memory cells in the manufacturing process.

As shown in FIG. 19, the floating gate electrode 5, the second gate insulating film 6, the control gate electrode 7 (word line WL), and the silicon oxide film 8 are formed as in the first embodiment. .

Next, as shown in FIG. 20, a mask 22 made of a resist film is formed on the semiconductor substrate 1 so as to cover the drain region of the memory cell MISFET Qm. The mask 22 is provided so as to cover the region where the p-channel MISFET forming the peripheral circuit is formed. Next, the n-type impurity, for example, phosphorus, is introduced at a dose of about 1 × 10 ¹⁵ to 1 × 10 ¹⁵ atoms / cm ² by ion implantation to form the n-type semiconductor region 21. The mask 22 is then removed.

Next, as shown in FIG. 21, a mask 23 made of a resist film is formed on the semiconductor substrate 1 so as to cover the source region and the ground line region of the memory cell Qm. The mask 23 is formed so as to cover the p-channel MISFET region and the n-channel MISFET region constituting the peripheral circuit. Next, n-type impurities such as arsenic are introduced at a dose of about 1 × 10 ¹⁵ atoms / cm ² by ion implantation to form the n ⁺ type semiconductor region 9. After ion implantation, the mask 23 is removed.

Next, as shown in FIG. 22, a sidewall spacer 12 made of a silicon oxide film is formed. Sidewall spacers 12 are also formed on the gate electrode sides of the n-channel MISFET and p-channel MISFET of the main circuit.

Next, after covering the area where the p-channel MISFET of the peripheral circuit is provided with a mask made of a resist film, as shown in FIG. 23, n-type impurities, for example, arsenic, are about 1 x 10 ¹⁶ atoms / cm ² by ion implantation. Is introduced in the dose amount to form the n ⁺ -type semiconductor region 10. The n ⁺ type semiconductor region 10 is also formed in the source drain region of the n-channel MISFET of the peripheral circuit. After ion implantation, the mask made of the resist film covering the p-channel MISFET region of the peripheral circuit is removed.

In the process so far, the MISFET Qm, which is a memory cell, is composed of an n-type semiconductor region 21 having an edge of a source region and an n ⁺ type semiconductor region 9 of edge yarns of a drain region. In the n-channel MISFET of the peripheral circuit, the edge of the source drain region is composed of the n-type semiconductor region 21.

The mask 23 shown in FIG. 21 is formed so as to cover only the entire region of the p-channel MISFET region and the drain region of the n-channel MISFET region in the peripheral circuit region, and to expose the source region of the n-channel MISFET. Also good. In this way, in the n-channel MISFET of the peripheral circuit, the edge of the source region is composed of the n ⁺ type semiconductor region 9, and the edge of the drain region is composed of the n type semiconductor region 21. The electric field of the drain region edge is relaxed, and the transconductance gm is high because the edge of the source region is n ⁺ type.

Subsequent manufacturing processes are the same as in the first embodiment.

24 is a cross-sectional view of a memory cell of still another embodiment of the present invention.

In this embodiment, the edge on the channel region side of the source region is composed of the n-type semiconductor region 21, the edge of the drain region is composed of the n ⁺ -type semiconductor region 9, and the n ⁺ -type semiconductor region 9 The p-type semiconductor region 24 is provided under the. In the p-type semiconductor region 24, the edge on the channel region side is defined by the floating gate electrode 5 and the control gate electrode 7, and the length in the gate width direction is defined by the field insulating film 2. The p-type semiconductor region 24 is provided only below the n ⁺ -type semiconductor region 9, and is not provided below the n ⁺ -type semiconductor region 10. For this reason, the generation efficiency of the heat carrier at the drain region edge can be improved.

The p-type semiconductor region 24 may be formed by implanting p-type impurities such as boron (B) before forming the n ⁺ -type semiconductor region 9 in the ion implantation process in FIG. In this manner, the p-type semiconductor region 24 can be formed with almost no increase in steps.

When the p-type semiconductor region 24 is formed by the process shown in FIG. 21, the p-type semiconductor region 24 is also formed at the edge of the drain region of the n-channel MISFET constituting the peripheral circuit. The p-type semiconductor region 24 in this peripheral circuit is effective for reducing the extension of the depletion layer in the drain region. In other words, it is effective in preventing punch through. In addition, in order to prevent the p-type semiconductor region 24 of the n-channel MISFET of the peripheral circuit from being formed, the resist mask 23 formed by the process shown in FIG. 21 may be formed by not only the p-channel MISFET region but also the n-channel MISFET of the peripheral circuit region. The p-type semiconductor region 24 may be formed only in the memory cell region by the ion implantation after it is completely covered. After the mask is removed, the n ⁺ type semiconductor region 9 is formed of a mask consisting of a resist film having a pattern exposing a drain region of a memory cell and a drain region of an n-channel MISFET of a peripheral circuit, and then formed by ion implantation. Do it. In this manner, the p-type semiconductor region 24 can be formed only in the memory cell. The p-type region 24 formed only on the drain side may be formed as shown in FIG.

In this embodiment, the p-type semiconductor region 24 is formed not only on the bottom of the n ⁺ type semiconductor region 9 in the drain region but also on the side surface A on the channel side. The p-type semiconductor region 24 is not provided below the n ⁺ -type semiconductor region 10. By forming the p-type semiconductor region 24 on the side surface A on the channel region side of the n ⁺ -type semiconductor region 9, the electric field at the edge of the drain region is strengthened to generate the efficiency of thermal carrier generation when information is written. You can increase it.

The p-type semiconductor region 24 in the present embodiment can be formed in the drain region of the n-channel MISFET of the peripheral circuit similarly to the p-type semiconductor region 24 in the embodiment of FIG. In addition, it can be made not to form in a peripheral circuit.

26 is a cross-sectional view of another memory cell of the present invention.

This embodiment is an n ⁺ type semiconductor region 10 having a drain region is formed of only n ⁺ type semiconductor region 10 having a junction depth of about 0.25㎛, a source region of the memory cell Qm is deep enough bonding 0.25㎛ And the n ⁻ type semiconductor region 11 provided to cover it. In the n ⁺ type semiconductor region 10, the density distribution is moderate in the case of deep mismatching. In addition, by covering the n ⁻ type semiconductor region 11, the concentration distribution of the source region is further relaxed. Therefore, since the junction breakdown voltage between the source region and the semiconductor substrate 1 is high, the information erasing characteristic is improved.

The n ⁻ type semiconductor region 11 can be formed in the same manner as the n ⁻ type semiconductor region 11 in FIG. 11 of the first embodiment. In the peripheral circuit region, the mask 20 shown in FIG. 11 opens the drain region of the n-channel MISFET and covers the source region and the p-channel MISFET region so that the n-channel MISFET of the peripheral circuit has a double drain structure. It can be formed.

27 is a plan view of a portion of a memory cell array according to still another embodiment of the present invention, FIG. 28 is a sectional view taken along the line A-A of FIG. 27, and FIG. 29 is an equivalent circuit diagram of the memory cell array of FIG. In FIG. 29, the configuration of the peripheral circuit is substantially the same as in the example of FIG.

This embodiment is provided with a MISFET Q _T for selecting a memory cell connected in series separately from the memory element Qm, and these two constitute one memory cell with the MISFET.

27 to 29, the MISFET, which is the memory element Qm, is formed of the first gate insulating film 4, the floating gate electrode 5, and the silicon oxide film, which are made of a silicon oxide film like the memory cells of the first embodiment. 2 gate insulating film 6, control gate electrode 7, n ⁺ type semiconductor region 9 and 10 as source region and n ⁻ type semiconductor region 11, n ⁺ type semiconductor region 9 as drain region And (10). The newly prepared MISFET Q _T includes a gate insulating film 6 made of a silicon oxide film by oxidation of the surface of the semiconductor substrate 1, for example, a gate electrode 26 made of a polycrystalline silicon film of a second layer, a source, and a drain region. The n ⁻ type semiconductor region 25 constituting the edge of the channel region side of the transistor is composed of the n ⁻ type semiconductor region 10 constituting a portion away from the channel region of the source and drain regions. A plurality of Q _T gate electrodes 26 are integrally formed to form a first word line WL ₁ extending in a direction crossing the direction in which the data line DL extends. In parallel with this, the second word line WL _{2 in} which the control gate electrodes 7 of several MISFETQm are integrally formed extends. MISFET Q _T shares the n ⁺ type semiconductor region 10 with MISFET Qm so that MISFET Q _T and Qm are connected in series. In two memory cells connected to the same data line DL through the same connection hole 14, the n ⁺ type semiconductor region 10, which is part of the drain region of each selected MISFET Q _T , is integrally formed. As shown in FIG. 27, the channel width of the MISFET Q _T is larger than that of the MISFET Qm which is a storage element. Each ground potential line GL formed integrally with the source region of the MISFET Qm and extending in the same direction as the direction in which the word lines WL ₁ and WL ₂ extend is connected to the inverter circuit as in the example shown in FIG. .

When writing information, the potential of each ground line GL becomes the ground potential Vss of the circuit. The first word line WL ₁ connected to the selected memory cell becomes the power supply voltage Vcc. The other first word line WL ₁ is the ground potential Vss. The second word line W ₂ connected to the selected memory cell is at the write potential Vpp, and the other second word line WL ₂ is at the floating state or the ground potential Vss. The data line DL connected to the selected memory cell becomes the power supply voltage Vcc, and the other data lines DL become the ground potential Vss.

GL is the ground potential Vss of the circuit when reading information. The first word line WL ₁ connected to the selected memory cell becomes the power supply potential Vcc. The other word lines WL ₁ become the ground potential Vss. All of the second word lines WL ₂ become the power supply potential Vcc. When the threshold voltage after the erasing of the memory element MISFET Qm is negative (for example, -3V), the ground potential Vcc is set. The data line DL is biased at about 1 to 2 V by a driving circuit DR (not shown) consisting of a static circuit. According to the contents of the selected memory cell, a change in potential generated in the data line DL is detected, amplified and output.

When the information is erased, all the ground lines GL become the erase potential Vpp. All second word lines WL ₂ become the ground potential Vss. The first word line and the data line DL become the ground potential Vss or floating. If these conditions are set, the information of all the memory cells is collectively erased.

According to the configuration of the memory cell of this embodiment, since the memory cell is composed of the MISFET Q _T and the memory element Qm, it is not necessary to make the threshold voltage at the time of erasing constant, so that the configuration of the erase circuit can be simplified.

By forming the edges of the source and drain regions of the MISFET Q _{T in} the n ⁻ type semiconductor region 25, generation of thermal carriers can be reduced.

The memory element in this embodiment is the memory cell described in the first embodiment, but the memory cell may be applied to any of the above-described embodiments.

The manufacturing method of the memory cell of the embodiment of FIGS. 27 to 29 will be described. 30 to 35 are plan views or cross-sectional views of memory cells in the manufacturing process.

As shown in FIGS. 4 and 5, the surface of the semiconductor substrate 1 is oxidized to form the field insulating film 2 and the insulating film 4 of the first gate having a film thickness of about 100 GPa. Next, as in the sixth diagram, a polycrystalline silicon film serving as the floating gate electrode 5 is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. This polycrystalline silicon film is patterned by the etching using the mask which consists of a resist film as shown in FIG. In this etching, the floating gate electrodes 5 of two memory cells which are connected to the same data line DL and have the ground line GL in common are patterned in one pattern. Therefore, the surface portion of the substrate 1 on which the gate electrode 26 (first word line WL ₁ ) is provided is exposed at the polycrystalline silicon film 5.

Next, the exposed surface of the polycrystalline silicon film 5 and the surface of the semiconductor substrate 1 exposed by the polycrystalline silicon film 5 are oxidized to oxidize the second gate insulating film 6 and the gate insulating film 6 of the MISFET Q _T. ). In the process of forming the gate insulating film 6, the gate insulating film of the MISFET constituting the peripheral circuit can also be formed. Then, in order to form the control gate electrode 7 (second word line WL ₂ ) and gate electrode 26 (second word line WL ₂ ), and the gate electrode of the MISFET of the peripheral circuit, for example, a semiconductor by CVD. A polycrystalline silicon film is formed on the entire surface of the substrate 1, and patterned by etching using a mask made of a resist film, and the gate electrodes 7 and 26 are formed as shown in FIG. In this etching process, the gate electrode of the MISFET of the peripheral circuit can also be formed. The gate electrodes 7 and 26 may be formed by laminating the high melting point metal film or the silicide film on a high melting point metal film such as Mo, W, Ta, Ti or the like, or a silicide film thereof or a polycrystalline silicon film. Next, the exposed surfaces of the gate electrodes 5, 7, 26 and the semiconductor substrate 1 are oxidized to form a silicon oxide film 8.

Next, as shown in FIG. 32, a mask 27 made of a resist film for forming the n ⁻ type semiconductor region 11 is formed on the semiconductor substrate 1. The mask 27 is provided in a pattern exposing the source region of the memory element Qm in the memory cell region, and in a pattern covering the entire region in the peripheral circuit region. Next, n-type impurities, for example, phosphorus, are introduced to the surface of the semiconductor substrate 1 exposed by the mask 27 by ion implantation to form the n ⁻ -type semiconductor region 11. The mask 27 is then removed.

Next, as shown in FIG. 33, n-type impurities such as arsenic or phosphorus are formed on the surface of the semiconductor substrate 1 by ion implantation using the gate electrodes 5, 7 and 26 as masks. Introduced to form an n ⁻ -type semiconductor region 25.

In this ion implantation process, the low concentration layer of the source and drain regions of the n-channel MISFET constituting the peripheral circuit can be formed. The region where the p-channel MISFET is provided is covered with a mask made of a resist film. This mask is removed after the ion implantation.

Next, as shown in FIG. 34, a mask 28 made of a resist film for forming an n ⁺ type semiconductor region 9 constituting a part of the source and drain regions of the memory element Qm is formed on the semiconductor substrate 1. To form. The mask 28 is provided in a pattern covering the source and drain regions of the MISFET Q _{T in} the memory cell region, and the peripheral circuit region is provided in a pattern covering all the regions. Next, the gate peripheral circuit area is provided in a covering pattern. Next, an n-type impurity, for example, arsenic, is introduced into the surface of the semiconductor substrate 1 exposing the gate electrodes 5 and 7 by the mask 28 as a mask for ion implantation to form an n ⁺ type. The semiconductor region 9 is formed. After ion implantation, the mask 28 is removed.

Next, as shown in FIG. 35, the sidewall spacers 12 are formed by reactive ion etching (RIE) the silicon oxide film formed on the entire surface of the substrate 1 by, for example, CVD. The sidewall spacers 12 are formed on the gate electrodes of both the n-channel MISFET and the p-channel MISFET constituting the peripheral circuit. Next, after covering the p-channel MISFET region with a mask made of a resist film, n-type impurities such as arsenic are formed by ion implantation using the sidewall spacers 12 and the gate electrodes 5, 7 or 26 as masks. Is introduced to the surface of the semiconductor substrate 1 to form the n ⁺ type semiconductor region 10. The high concentration region of the source and drain regions of the n-channel MISFET for constituting the peripheral circuit is also formed at the same time. After ion implantation, the mask made of a resist film covering the p-channel region is removed. Then, the n-channel MISFET region of the memory cell region and the peripheral circuit is covered with a mask made of a resist film, and p-type impurities such as boron are introduced into the p-channel MISFET region to form a p ⁺ type semiconductor region, which is a source and drain region. . The mask made of a resist film is removed after ion implantation.

Since the subsequent steps are the same as the manufacturing method of the first embodiment, the description is omitted.

As described above, the MISFET Q _T of the memory cell and the MISFET Qm of the memory element can be formed in almost the same process.

In addition, the n-channel MISFET and the memory cell constituting the peripheral circuit can be formed in the same process.

36 is a cross-sectional view of a memory cell of still another embodiment of the present invention.

In this embodiment, the memory cell is composed of one MISFET, and the n ^- type semiconductor region 11 having a deep aggregation is provided in its source region, and the p-type semiconductor region 24 having a deep junction is provided in the drain region. The edge on the channel region side of the source and drain regions is composed of an n ⁺ type semiconductor region 9 having a shallow junction of about 0.1 mu m. The portion isolated from the channel region is the n ⁻ type semiconductor region 10 having a deep junction of about 0.25 μm. The n ⁻ type semiconductor region 11 has a deeper aggregation than the n ⁺ type semiconductor regions 9 and 10 which are part of the source and drain regions. In the channel region on the source side, a region 11 of low impurity concentration exists between the n ⁺ type semiconductor region 9 and the semiconductor substrate 1. Since the n ⁻ type semiconductor region 11 is provided, the junction breakdown voltage between the source region and the semiconductor substrate 1 is high. Therefore, the erasing voltage Vpp applied to the source region at the time of erasing the information can be increased to about 13 V, so that the erasing time can be shortened. In addition, erasure can be reliably performed.

On the other hand, in the drain region, the p-type semiconductor region 24 reaches the lower portions of the n ⁺ -type semiconductor regions 9 and 10. In the channel region, the p-type semiconductor region 24 is formed between the p-type semiconductor region 9 and the semiconductor substrate 1 to strengthen the electric field generated between the drain semiconductor substrate 11. The generation efficiency of the thermal carrier at the time of writing information can be improved, and the drain voltage at the time of writing can be reduced to about 5V or less. Next, the manufacturing method of the memory cell of this embodiment will be described. 37 to 41 are cross-sectional views of memory cells in the manufacturing process.

As shown in FIG. 37, like the first embodiment, the first gate insulating film 4, the floating gate electrode 5, the second gate insulating film 6, the control gate electrode 7 (word line WL), and oxidation The silicon film 8 is formed.

Thereafter, a mask 29 made of a resist film for forming the n ⁻ type semiconductor region 11 is formed on the semiconductor substrate 1. The mask 29 is formed in a pattern that exposes the source region and the ground line GL of the memory cell. The peripheral circuit area is all covered by the mask 29. Next, by implanting the ion, the semiconductor substrate 1 exposing the n-type impurities, for example, phosphorus, in the mask 29 and the gate electrodes 5 and 7 with a dough weight of 10 ¹³ to 10 ¹⁴ atoms / cm ² . N ^- type semiconductor region 11 is formed on the surface of? The mask 29 is removed after ion implantation.

Next, as shown in FIG. 38, the source region and the ground line GL region of the memory cell are covered with a mask 30 made of a resist film. The mask 30 is provided to cover all of the peripheral circuit area. Next, a p-type impurity, for example, boron, is introduced at a dose of 2 to 5 x 10 ¹² atoms / cm ² on the surface of the semiconductor substrate 1 exposed by the mask 30 and the gate electrodes 5 and 7. The p-type semiconductor region 24 is formed. The mask 30 is then removed. After that, the n ⁻ type semiconductor region 11 and the p type semiconductor region 24 may be extended by annealing.

Next, as shown in FIG. 39, n-type impurities such as arsenic are introduced into the surface of the semiconductor substrate 1 by ion implantation using the gate electrodes 5 and 7 as masks, and then n ⁺ -type. The semiconductor region 9 is formed. In this on-injection step, the peripheral circuit region is covered with a mask made of a resist film. The ion implantation may be performed in two separate times. That is, in one ion implantation, n-type impurities are introduced at low concentration into the n-channel MISFET region of the memory cell region and the peripheral circuit. In the second ion implantation, the peripheral circuit region may cover the entire region with a mask made of a resist film, and n-type impurities may not be introduced into the peripheral circuit region. In this way, a shallow junction n ⁺ type semiconductor region 9 can be formed in the memory cell region, and a shallow junction n ⁻ type semiconductor region can be formed in the n-channel MISFET region of the peripheral circuit.

Next, as shown in FIG. 40, the sidewall spacer 12 is formed by performing RIE on the silicon oxide film formed on the entire surface of the substrate 1 by, for example, CVD. Sidewall spacers 12 are also formed on the side of the gate electrode of the MISFET of the peripheral circuit.

Next, as shown in FIG. 41, after covering the p-channel MISFET region with a mask made of a resist film, n-type impurities such as arsenic are introduced by ion implantation to form the n ⁺ -type semiconductor region 24. As shown in FIG. The n ⁺ type semiconductor region 24 is also formed in a portion isolated from the source and drain regions of the n-channel MISFET of the peripheral circuit. The mask made of a resist film covering the p-channel MISFET region is removed after ion implantation. Next, after covering the n-channel MISFET region of the memory cell region and the peripheral circuit with a mask made of a resist film, p-type impurities such as boron are introduced into the p-channel MISFET region to form a p ⁺ -type semiconductor region, which is a source and drain region. . After ion implantation, the mask made of a resist film covering the memory cell region and the n-channel MISFET region of the peripheral circuit is removed.

As described above, the n-channel MISFET of the memory cell and the peripheral circuit can be formed in approximately the same process.

42 is a cross-sectional view of a memory cell of still another embodiment of the present invention.

In this embodiment, the n ⁻ type semiconductor region 11 is provided only around the n ⁺ type semiconductor region 9 provided at the edge of the channel region side of the source region, and n is provided at the edge of the channel region side of the drain region. ^The p-type semiconductor region 24 is provided only around the ⁺ type semiconductor region 9. By providing the n ⁻ type semiconductor region 11 at the edge in the source region, the breakdown voltage of the junction between the source region and the semiconductor substrate 1 can be increased and the erase voltage can be increased. In addition, since the n ⁻ type semiconductor region 11 has the same junction depth as that of the n ⁺ type semiconductor region 10 and the overlap with the channel region is small, the variation of the threshold value is small and the electrical characteristics of the memory cell are improved.

On the other hand, the electric force applied between the edge of the drain region and the semiconductor substrate 1 by the p-type semiconductor region 24 becomes strong. Therefore, the generation efficiency of the heat carrier is improved and the light characteristics are improved. In addition, since the p-type semiconductor region 24 is as shallow as the n ⁺ -type semiconductor region 10, the overlap to the channel region is small. Since the variation of the threshold value is small, the electrical characteristics of the memory cell are improved.

In addition, since there is no p-type semiconductor region 24 under the n ⁺ -type semiconductor region 10, the parasitic capacitance of the drain region is small. The n ⁻ type semiconductor region 11 and the p type semiconductor region 24 in the present embodiment are formed in the same manner as the n ⁻ type semiconductor region 11 of FIG. 37 and the p type semiconductor region 24 of FIG. 38. You can do it.

43 is a sectional view of a memory cell in still another embodiment of the present invention.

In this embodiment, the n ⁻ type semiconductor region 11 having a deep junction reaching the bottom of the n ⁺ type semiconductor region 10 is provided in the source region, and the p type semiconductor region 31 is provided in the channel region. The n ⁻ type semiconductor region 11 has reached the channel region. The semiconductor region is not provided below the n ⁺ type semiconductor region 9 constituting the edge of the drain region. The n ⁻ type semiconductor region 11 increases the breakdown voltage of the junction between the source region and the semiconductor substrate 1. On the other hand, the electric field applied to the edge of the drain region following the p-type semiconductor region 31 can be strengthened.

The p-type semiconductor region 31 may use an ion implantation process for introducing a p-type impurity, for example boron, into the channel region to adjust the threshold of the memory cell. In order to form the p-type semiconductor region 31, the ion implantation dose may be about 2 to 5 x 10 ¹² atoms / cm ² . In addition, ion implantation for adjusting the threshold value of the MISFET of the peripheral circuit may be performed separately from the memory cell.

44 is a sectional view of a memory cell of still another embodiment of the present invention.

This embodiment provides a p-type semiconductor region 24 having a deep junction so as to surround the n ⁺ -type semiconductor regions 9 and 10 constituting the drain region, and an n ⁻ -type semiconductor region ( 32). Since the p-type semiconductor region 24 is formed surrounding the n ⁺ -type semiconductor region 9, elongation of the depletion layer at the edge of the drain region is suppressed. Therefore, the generation efficiency of the thermal carrier at the drain edge at the time of writing can be improved.

On the other hand, since the n ⁻ type semiconductor region 32 has an edge at the channel side of the source region, the electric field is relaxed. Therefore, the erase voltage applied to the source region at the time of erasing the information can be increased.

Ion implantation for forming the n ⁻ -type semiconductor region 32 is performed by, for example, arsenic at a dough weight of 10 ¹¹ to 10 ¹² atoms / cm ² . In addition, the 36 degrees, a 42 [deg.] To the MISFET Qm The memory cell is carried out 44 degrees may be subjected to so as to form one memory cell MISFET Q _T with two steps degrees to 29 degrees embodiment memory cell of claim 27.

As mentioned above, although this invention was demonstrated concretely by the Example, this invention is not limited to the said Example, Of course, it can change in various ways in the range which does not deviate from the summary.

The external terminals for data input and output are (4), (8), (16)... Etc. may be provided. In this case, one address signal (4), (8), (16)... Corresponds to the memory cell. The memory cell may be formed in a p ⁺ type well region formed in an n ⁻ type semiconductor substrate. In addition, the conductivity type of each semiconductor region may be reversed.

The present invention can be widely applied to ROM or nonvolatile memory which can be electrically written and erased.

Claims (14)

A control gate electrode, a floating gate electrode, a second gate formed between the two gate electrodes, an insulating film, a first gate insulating film formed between the semiconductor substrate and the floating gate electrode, first and second semiconductor regions formed in the semiconductor substrate, A memory cell comprising a channel region formed between first and second semiconductor regions in the semiconductor substrate, the memory cell tunneling through the first gate insulating film of a carrier from the floating gate electrode to the first semiconductor region; 1. A method of manufacturing a semiconductor memory device, which executes a process and reads information in a second semiconductor region by applying a predetermined potential to the second semiconductor region, the method comprising: a first gate on a semiconductor substrate of a first conductivity type; A floating gate electrode on the insulating film, a second gate insulating film on the floating gate electrode, and the Forming a control gate electrode on the second gate insulating film so that both ends thereof overlap each other; introducing impurities into the semiconductor substrate self-aligningly to one end of the control gate electrode to form a second conductivity type in the semiconductor substrate. Forming a first semiconductor region of said second semiconductor region, said second semiconductor region of said second conductivity type in said semiconductor substrate being introduced into said semiconductor substrate by introducing impurities into the other end of said control gate electrode. And forming an overlap amount with the gate electrode to be smaller than the overlap amount between the first semiconductor region and the floating gate electrode. The method of claim 1, further comprising: forming sidewall spacers in a self-aligning manner with respect to both ends of the control gate electrode and the floating gate electrode, wherein the control gate electrode, the floating gate electrode, and the sidewall spacer A semiconductor memory device including a step of introducing impurities in both ends to form a second semiconductor region of a second conductivity type having a higher impurity concentration and a deeper junction depth than the second semiconductor region in the semiconductor substrate; Manufacturing method. The method of claim 1, wherein impurities are introduced into the other ends of the control gate electrode and the floating gate electrode in a self-aligned manner to at least a portion of the channel region on the side of the second semiconductor region. A method of manufacturing a semiconductor memory device comprising the step of forming a fourth semiconductor region of a first conductivity type having a higher impurity concentration than a semiconductor substrate. The method of claim 3, further comprising forming sidewall spacers in a self-aligning manner with respect to both ends of the control gate electrode and the floating gate electrode, wherein the control gate electrode, the floating gate electrode, and the sidewall spacer The third conductive region of the second conductivity type in which the impurity concentration is higher than that of the second semiconductor region and deeper than the second and fourth semiconductor regions is introduced into the semiconductor substrate by introducing impurities at both ends. Method of manufacturing a semiconductor memory device comprising the step of forming a. The method of claim 1, wherein the second semiconductor region is formed to have a shallower junction depth than the first semiconductor region. A control gate electrode, a floating gate electrode, a second gate insulating film formed between the two gate electrodes, a first gate insulating film formed between the semiconductor substrate and the floating gate electrode, first and second semiconductor regions formed in the semiconductor substrate, and A memory cell comprising a channel region formed between a first semiconductor region and a second semiconductor region in the semiconductor substrate, wherein the memory cell passes through the first gate insulating film to release carriers from the floating gate electrode to the first semiconductor region; A method of manufacturing a semiconductor memory device which executes one tunneling and reads information in a second semiconductor region by applying a predetermined potential to the second semiconductor region, the method comprising: A floating gate electrode on one gate insulating film, a second gate on the floating gate electrode, and Forming a control gate electrode on both ends of the control gate electrode on the second gate insulating film, and introducing impurities into one end of the control gate electrode and the floating gate electrode in a self-aligned manner to form a second Forming a first semiconductor region of a conductivity type, introducing impurities self-aligningly to both ends of the control gate electrode and the floating gate electrode, and having a higher impurity concentration in the semiconductor substrate than the first semiconductor region and Forming a second semiconductor region of a shallow second conductivity type and introducing the same impurities into the first semiconductor region, and sidewall spacers are self-aligned to both ends of the control gate electrode and the floating gate electrode. Forming process, the control gate electrode, floating gate electrode and side A third conductivity type third conductive layer having a deeper junction depth than the first and second semiconductor regions in the semiconductor substrate on the side of the first and second semiconductor regions by introducing impurities self-aligned to both ends of the wall spacer; A method of manufacturing a semiconductor memory device comprising the step of forming a semiconductor region. The method of claim 6, wherein impurities are introduced into the other ends of the control gate electrode and the floating gate electrode in a self-aligned manner so that at least a portion of the channel region is at least on the second semiconductor region side. A method of manufacturing a semiconductor memory device comprising the step of forming a fourth semiconductor region of a first conductivity type having a higher impurity concentration than a semiconductor substrate. A control gate electrode, a floating gate electrode, a second gate insulating film formed between the two gate electrodes, a first gate insulating film formed between the semiconductor substrate and the floating gate electrode, first and second semiconductor regions formed in the semiconductor substrate, and A memory cell comprising a channel region formed between a first semiconductor region and a second semiconductor region in a semiconductor substrate, and a MISFET constituting a peripheral circuit, wherein the memory cell emits carriers from the floating gate electrode to the first semiconductor region. A method of manufacturing a semiconductor memory device in which a semiconductor memory device is formed by tunneling through a first gate insulating film, wherein the floating gate is formed on a first gate insulating film on the semiconductor substrate in a memory cell formation region of a semiconductor substrate of a first conductivity type. An electrode, a second gate insulating film and the second gate on the floating gate electrode Control gate electrodes are formed on the smoke film so that both ends thereof overlap each other, and in the peripheral circuit formation region of the semiconductor substrate, a gate insulating film of the MISFET is formed on the semiconductor substrate and a gate electrode of the MISFET is formed on the gate insulating film. In the step of forming a memory cell of the semiconductor substrate, impurities are introduced into each of the ends of the control gate electrode and the floating gate electrode in a self-aligned manner to form a first semiconductor region of a second conductivity type in the semiconductor substrate. In the peripheral circuit forming region of the semiconductor substrate, the second conductive type having impurity concentration lower than that of the first semiconductor region in the semiconductor substrate by introducing impurities self-aligned to both ends of the gate electrode. In addition, a first region to be used as a source and a drain region of the MISFET is formed. In the step, the peripheral circuit forming region of the semiconductor substrate and the memory cell region, sidewall spacers are formed in self-alignment with respect to both ends of the gate electrode of the MISFET, and both ends of the control gate electrode and the floating gate electrode. Forming sidewall spacers in self-alignment with each other; in both peripheral circuit formation regions and memory cell regions of the semiconductor substrate, both ends of the gate electrode of the MISFET and both ends of the control gate electrode and the floating gate electrode; And forming a third semiconductor region of a second conductivity type having a higher impurity concentration and a deeper junction depth than the first region by introducing impurities in a self-aligned manner. 10. The method of claim 8, wherein the forming of the first semiconductor region is performed by using a mask covering a portion of the memory cell forming region on the peripheral circuit forming region and one side of the control gate electrode and the floating gate electrode. A method of manufacturing a semiconductor memory device, wherein the impurities are introduced in a self-aligned manner to an end portion of the semiconductor memory device. 9. The semiconductor device according to claim 8, wherein in the memory cell formation region of the semiconductor substrate, impurities are introduced into the semiconductor substrate by self-alignment with respect to the other ends of the control gate electrode and the floating gate electrode. A method for manufacturing a semiconductor memory device comprising the step of forming a second conductive semiconductor region. 10. The method of claim 8, wherein in the step of forming the first semiconductor region, impurities are introduced into the semiconductor substrate by self-alignment with respect to the other ends of the MISFET and the floating gate electrode. A method of manufacturing a semiconductor memory device, wherein a region is formed simultaneously with the first semiconductor region. 12. The semiconductor device according to claim 11, wherein in the memory cell formation region of the semiconductor substrate, impurities are introduced into the other ends of the control gate electrode and the floating gate electrode in a self-aligned manner so that at least the And forming a fourth semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor substrate in a portion on the side of the second semiconductor region deeper than the second semiconductor region. The method of claim 8, wherein the third semiconductor region is formed deeper than the fourth semiconductor region. The method of claim 12, wherein the forming of the fourth semiconductor region is performed by applying a mask on the peripheral circuit forming region and a portion of the memory cell forming region to cover the control gate electrode and the floating gate electrode. A method of manufacturing a semiconductor memory device for introducing the impurities consistently.