JP2544570B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a MISFET in which a memory cell has a floating gate electrode and a control gate electrode.
An electrically erasable semiconductor memory device, that is,
EEPROM (Electrically Erasa)
ble and programmable ROM).

[0002]

2. Description of the Related Art EEPR composed of a MISFET having a floating gate electrode and a control gate electrode
The memory cell of the OM is, for example, a technical digest (T) of the 1984 International Electronic Device Conference 1984 IEDM.
ech. Digest), PP. 468-471.

In the memory cell, electrons are tunnel-injected from the substrate into the floating gate or tunnel electrons are ejected from the floating gate to the substrate through the thin oxide film under the floating gate.
It is necessary to apply a strong electric field of MV / cm or more. Therefore, it is necessary to increase the overlapping area of the floating gate and the control gate. Also, the memory cell is
It is composed of two elements, a memory transistor and a select transistor.

As described above, the memory cell is an EPRO having the same floating gate and control gate.
5 times larger than M cell, high integration and large capacity EPR
Not suitable for OM.

Therefore, in order to reduce the cell size, it has a floating gate electrode and a control gate electrode, and injects (writes) electrons into the floating gate.
Has been proposed as a one-element type memory cell in which hot electrons generated at the end of the drain region are used to discharge (erase) electrons from the floating gate by tunneling to the source region (1985 International Electron Device Conference 1984 IEDM Technical Digest (Te
ch. Digest), PP. 616-619).

[0006]

The technical problems of the memory cell are as follows.

In the EEPROM, writing and erasing are also performed by a single 5V power supply, and it is becoming general that a high voltage for writing and erasing is generated by a booster circuit provided in the same chip.

However, since the memory cell performs writing by generating hot electrons at the end of the drain region while flowing a drain current, a relatively large current is required, which is a high voltage generated by the booster circuit. However, the current capacity is too small to apply.

Therefore, it is necessary to realize a memory cell which can be sufficiently written even when the drain voltage at the time of writing is 5 V or more of the external power supply. Further, for erasing, it is necessary to apply a voltage of 10 V or more to the source region to cause a tunnel between the floating gate and the source region, so the withstand voltage between the source region and the substrate is 10 V or more, and avalanche occurs during erasing. It is necessary not to do it.

An object of the present invention is to provide a memory cell capable of writing even at a low drain voltage.

Another object of the present invention is to provide a memory cell capable of high speed operation.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the drain region of the memory cell composed of the MISFET having the floating gate electrode and the control gate electrode is formed of a high concentration layer, and the end of the source region on the channel region side is made low concentration. Further
Side wall when forming the source or drain
Use spacers. Or with the substrate on the drain region side
A region having the same conductivity type and a higher concentration than that of the substrate is formed.

[0015]

According to the above-mentioned means, the electric field at the end of the drain region becomes strong, so that the generation of hot electrons is increased, whereby the write voltage can be reduced. Moreover, since the avalanche breakdown voltage between the source region and the semiconductor substrate is increased, the erase efficiency can be improved.

[0016]

[Embodiment 1] FIG. 1 is a sectional view of the memory cell array shown in FIG. 2 taken along the line AA, FIG. 2 is a plan view of a part of the memory cell array, and FIG. 3 is an equivalent circuit of the memory cell array. Is. Note that FIG. 2 does not show an insulating film other than the field insulating film in order to make the configuration of the memory cell easier to see.

First, the outline of the circuit of the memory cell array will be described with reference to FIG.

In FIG. 3, reference numeral 15 is a Y decoder, 16 is an X decoder, and 17 is a sense amplifier. Qm is a memory cell, which is composed of a MISFET having a floating gate electrode and a control gate electrode. The control gate electrode is connected to the word line WL.
The drain region is connected to the data line DL, and the source region is connected to the ground line GL. Qs ₁ and Qs ₂ apply the ground potential Vss of the circuit, for example, 0 V to the ground line GL at the time of writing and reading information, and erase potential V at the time of erasing information.
pp is a switch element for applying, for example, 14V. When writing and reading information, MISFETQ
s ₁ is turned off and MISFET Qs ₂ is turned on. At the time of erasing information, the MISFET Qs ₁ is rendered conductive and the MISFET Qs ₂ is rendered non-conductive. The data line DL is applied with a power supply potential Vcc, for example, 5 V at the time of writing and reading, and the ground potential Vs at the time of erasing.
s For example, 0 V is applied. A write potential Vpp, for example, 14V is applied to the word line WL during writing, and a Vcc potential, for example, 5V is applied during reading. At the time of erasing, the ground potential Vss is set to 0 V, for example.

As shown in FIGS. 1 and 2, the MISFET, which is a memory cell, includes a first gate insulating film 4, a floating gate electrode 5, a second gate insulating film 6, a control gate electrode 7, an n + type semiconductor region 9, It is composed of an n + type semiconductor region 10 and an n− type semiconductor region 11. The first gate insulating film 4 is a silicon oxide film formed by surface oxidation of the semiconductor substrate 1 and has a film thickness of about 100 Å.
The floating gate electrode 5 is made of a polycrystalline silicon film and is provided so as to adhere to the first gate insulating film 4.
The second gate insulating film 6 and the floating gate electrode 5 are made of a silicon oxide film formed by oxidation of the surface of the polycrystalline silicon film, and have a film thickness of about 250 to 350 Å.
The control gate electrode 7 is made of, for example, a second-layer polycrystalline silicon film, and is deposited on the surface of the second gate insulating film 6. Further, it is formed integrally with the word line WL and extends over the field insulating film 2.

The drain region is composed of the n + type semiconductor region 9 and n.
+ Type semiconductor region 10 and the same data line D
The drain regions of two memory cells connected to L through the same connection hole 14 are integrated. The end of the drain region on the channel region side is constituted by the n + type semiconductor region 9 having a shallow junction depth of about 0.1 μm. Therefore, the surrounding of the drain region to the lower portion of the floating gate electrode 5 is small. Further, in the channel length direction of the n + type semiconductor region 9, the electric field at the end of the drain region on the channel region side at the time of writing information can be strengthened as compared with the case where the semiconductor region 9 is of the n− type. The length is defined by the sidewall spacer 12 made of a silicon oxide film. The portion of the drain region separated from the channel region is 0.
N + type semiconductor region 10 having a deep junction of about 25 μm
It consists of

The source regions are n + type semiconductor regions 9 and n +.
It is composed of a type semiconductor region 10 and an n − type semiconductor region 11. The n + type semiconductor regions 9 and 10 and the n− type semiconductor region 11 forming these source regions are formed between two memory cells connected to the same data line DL through two adjacent connection holes 14. A ground line (ground line) GL is formed by extending in the direction in which the word line WL extends. The end of the source region on the channel region side is formed by the shallow n + type semiconductor region 9 having a junction to reduce the surrounding of the floating gate electrode 5 to the lower part. n +
The length of the type semiconductor region 9 in the channel length direction is defined by the sidewall spacer 12. The surface part of the part isolated from the channel region is interposed between the n + type semiconductor region 9 and the n + type semiconductor region 10 having a deep junction and the semiconductor substrate 1, so that the n− type semiconductor region 11 is formed.
Is provided. The n − type semiconductor region 11 reaches the surface of the semiconductor substrate 1 in the channel region. Therefore, the junction breakdown voltage between the n + type semiconductor region 9 and the semiconductor substrate 1 is increased.

The surface of the semiconductor substrate 1 exposed from the field insulating film 2 and the floating gate electrode 5, the floating gate electrode 5, and the control gate electrode 7.
A silicon oxide film 8 adheres and covers the exposed surface of. Sidewall spacers 12 made of a silicon oxide film are provided by adhering to the silicon oxide film 8 on the side surfaces of the floating gate electrode 5 and the control gate electrode 7.

13 is, for example, phosphorus silicate glass (PS
G) is an insulating film made of a film and covers the semiconductor substrate 1. N + type semiconductor region 10 which is a part of the drain region
By selectively removing the insulating film 13 on the upper part of the connection hole 14
Is formed. The data line DL made of an aluminum film is connected to the n + type semiconductor region 10 which is a part of the drain region through the connection hole 14. The junction depth of the portion of the n + type semiconductor region 10 to which the data line DL is connected is
It is deeper than the other parts. Although not shown, the data line DL is covered with a protective film made of, for example, a PSG film formed by CVD and a silicon nitride film formed thereon.

To write information to the memory cell, by applying the above-mentioned potential to each region, hot carriers are generated at the end of the n + type semiconductor region 9 in a part of the drain region, and hot electrons among them are generated. This is done by injecting into the floating gate electrode 5. Information is erased by the floating gate electrode 5 as described above.
The electrons held in the first tunnel
This is done by discharging to the n + type semiconductor region 9 through the gate insulating film 4. During the erase operation, Vt of the memory element after erase is set to be approximately constant at about 1V.
Since the h control circuit operates, a one-element type memory cell can be realized.

As described above, according to the memory cell of this embodiment, the following effects can be obtained.

(1) By providing the n − type semiconductor region 11 between the n + type semiconductor regions 9 and 10 forming the source region and the semiconductor substrate 1, the junction breakdown voltage between them is increased, and thus the information The erase voltage applied to the source region during erase can be increased. As a result, characteristics such as information erasing time and erasing reliability can be improved.

(2) The end portion of the source region has a shallow junction n +
Since it is configured by the type semiconductor region 9, the sneaking into the lower portion of the floating gate electrode 5 is reduced, so that the capacitance between the source region and the floating gate electrode 5 can be reduced.

(3) According to the above (2), the voltage generated in the first gate insulating film 4 by the voltage applied to the n + type semiconductor region 9 forming the source region at the time of erasing information can be increased. The erasing property can be improved.

(4) Since the end of the drain region on the channel region side is formed by the shallow junction n + type semiconductor region 9, the drain region and the floating gate electrode 5 are formed.
Since the capacity during the period is reduced, the information reading speed can be improved.

(5) Since the semiconductor region 9 having the shallow junction at the end of the drain region is of n + type, the electric field at the end of the drain region at the time of writing can be strengthened as compared with the case of n− type. it can. As a result, the write voltage can be reduced.

(6) Since the end of the drain region is formed of the n + type semiconductor region 9 having a shallow junction, the sneaking into the lower portion of the floating gate electrode 5 becomes small, so that the short channel effect can be prevented. it can.

Next, a method of manufacturing the memory cell will be described.

4 to 16 are sectional views or plan views in the manufacturing process of the same portion of the memory cell as in FIG.

As shown in FIG. 4, a predetermined surface of the semiconductor substrate 1 is oxidized by using a silicon oxide film 18 formed by oxidation of the p-type semiconductor substrate 1 and a silicon nitride film 19 formed by, for example, CVD as a thermal oxidation mask. The field insulating film 2 is formed by. The p-type channel stopper 3 is formed by ion implantation before forming the field insulating film 2.
It is formed by introducing a type impurity such as boron (B). After forming the field insulating film 2, the silicon nitride film 19 and the silicon oxide film 18 are removed.

Next, as shown in FIG. 5, the surface of the semiconductor substrate 1 exposed from the field insulating film 2 is oxidized to form a first gate insulating film 4 made of a silicon oxide film.

Next, as shown in FIG. 6, in order to form the floating gate electrode 5, a polycrystalline silicon film 5 is formed on the entire surface of the semiconductor substrate 1 by, eg, CVD. An n-type impurity such as phosphorus (P) is introduced into the polycrystalline silicon film 5 by thermal diffusion, ion implantation or the like.

Next, as shown in FIG. 7, the polycrystalline silicon film 5 is extended by the etching of the resist film so as to extend in the direction in which the data line DL extends with a predetermined width of the floating gate electrode 5. Pattern. That is, in this patterning step, the polycrystalline silicon film 5 is patterned into a pattern in which the floating gate electrodes 5 of a plurality of memory cells connected to the same data line DL are integrated. The polycrystalline silicon film formed in the peripheral circuit region is removed. After patterning the polycrystalline silicon film 5, the mask made of the resist film is removed.

Next, as shown in FIG. 8, the surface of the polycrystalline silicon film 5 is oxidized to form a second gate insulating film 6 made of a silicon oxide film. The film thickness is about 250 to 350 Å. In this oxidation step, the gate insulating film of the MISFET forming the peripheral circuits such as the buffer circuit, the decoder circuit and the sense amplifier is formed. Next, in order to form the control gate electrode 7 and the word line WL, for example, C
A polycrystalline silicon film 7 is formed on the entire surface of the semiconductor substrate 1 by VD. An n-type impurity such as phosphorus (P) is introduced into the polycrystalline silicon film 7 by thermal diffusion, ion implantation, or the like.

Next, as shown in FIG. 9, the polycrystalline silicon film is etched by etching using a mask made of a resist film to form the control gate electrode 7 and the word line WL. In this etching process, the gate electrode of the MISFET of the peripheral circuit is also formed. Following the etching, the second gate insulating film 6 exposed from the floating gate electrode 5 is etched. Further, the polycrystalline silicon film 5 is etched to form the floating gate electrode 5. After this series of etching, the mask made of the resist film is removed. The control gate electrode 7, the word line WL, and the gate electrode of the MISFET of the peripheral circuit are formed of a refractory metal film such as Mo, W, Ta, or Ti, a silicide film thereof, or a polycrystalline silicon film. Alternatively, a two-layer film in which a silicide film is laminated may be used.

Next, as shown in FIG. 10, the exposed surfaces of the floating gate electrode 5 and the control gate electrode 7 (word line WL) are oxidized to form a silicon oxide film 8. During this oxidation, the surface of the semiconductor substrate 1 exposed from the floating gate electrode 5 and the control gate electrode 7 is oxidized to form a silicon oxide film 8.

Next, as shown in FIG. 11, the semiconductor substrate 1
A mask 20 made of a resist film for forming the n − type semiconductor region 11 is formed on the top. The mask 20 also covers the peripheral circuit region. Next, an n-type impurity such as phosphorus (P) is formed on the exposed surface portion of the semiconductor substrate 1 by ion implantation.
Is introduced at about 1 × 10 ¹³ to 1 × 10 ¹⁴ atoms / cm ² to form the n − type semiconductor region 11. The mask 20 is removed after the ion implantation. Thereafter, the n− type semiconductor region 11 may be stretched by annealing so as to have a deeper junction than the n + type semiconductor region 10 formed later.

Next, as shown in FIG. 12, using the floating gate electrode 5 and the control gate electrode 7 as a mask, the surface of the semiconductor substrate 1 is ion-implanted with an n-type impurity such as arsenic (As) at 1 × 10 ¹⁵ atoms / c.
About n ^{2 is} introduced to form the n + type semiconductor region 9. At the time of this ion implantation, the peripheral circuit region is covered with a mask made of a resist film so that only the memory cell region is ion-implanted. Further, the memory cell region is covered with a mask made of a resist film and the peripheral circuit region is n-type. The source and drain regions of the N-channel MISFET constituting the peripheral circuit are LDD (Li) by ion-implanting impurities such as phosphorus (P) at about 1 × 10 ¹³ atoms / cm ^2.
It is also possible to have a ghtly Doped Drain) structure. In this case, the mask made of the resist film provided in the peripheral circuit region is removed after the ion implantation.

Next, as shown in FIG. 13, the semiconductor substrate 1
A silicon oxide film 12 for forming the sidewall spacers 12 is formed on the entire upper surface by, for example, CVD.

Next, as shown in FIG. 14, the silicon oxide film 12 is etched by reactive ion etching (RIE) until the surface of the semiconductor substrate 1 is exposed to form sidewall spacers 12. Sidewall spacers 12 are also formed on the sides of the gate electrode of the MISFET for forming the peripheral circuit. The surface of the semiconductor substrate 1 exposed by the etching is oxidized again to form a silicon oxide film 8.

Next, as shown in FIG. 15, using the floating gate electrode 5, the control gate electrode 7 and the sidewall spacer 12 as a mask, 1 × 10 ¹⁶ atm of an n-type impurity such as arsenic (As) is ion-implanted.
The n + type semiconductor region 10 is formed by introducing about oms / cm ² . In this ion implantation step, high-concentration layers of the source and drain regions of the N-channel MISFET of the peripheral circuit are also formed. The region of the peripheral circuit where the P-channel MISFET is formed is covered with a mask made of a resist film so that the n-type impurities are not introduced. The mask made of the resist film is removed after ion implantation. After forming the N-channel MISFET, although not shown, the N-channel MISFET region and the memory cell region of the peripheral circuit are covered with a mask made of a resist film, and the P-channel MIS of the peripheral circuit is ion-implanted.
A p-type impurity such as boron (B) is introduced into the FET region to form the source and drain regions of the P-channel MISFET. The mask made of the resist film covering the N-channel MISFET and the memory cell region is removed after the p-type impurity is introduced.

Next, as shown in FIG. 6, an insulating film 13 made of a PSG film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. After that, the connection hole 14 shown in FIGS. 1 and 2, the data line DL made of an aluminum film, and a final protective film (not shown) are formed.

As described above, according to the manufacturing method of this embodiment, the N-channel MI which constitutes the peripheral circuits such as the address buffer circuit, the decoder circuit, the sense amplifier circuit, etc.
A memory cell can be formed in substantially the same process as the SFET.

[Embodiment 2] FIG. 17 is a cross-sectional view of a memory cell in Embodiment 2.

In the second embodiment, the n − type semiconductor region 11 is shallowly formed so that only the n + type semiconductor region 9 is covered with the n − type semiconductor region 11, and the lower part of the n + type semiconductor region 10 is n − type. This is so that the semiconductor region 11 is not formed. Since the depth of the n − type semiconductor region 11 is shallow, diffusion into the channel region is also small. Therefore, the variation in the threshold value of the MISFET, which is a memory cell, is reduced and the electrical characteristics are improved. Further, since the short channel effect is reduced, the characteristics of the memory cell are improved.

The n − type semiconductor region 11 may be formed shallowly so as to cover only the n + type semiconductor region 9 as described above in the step of FIG. 11 described in the method of the first embodiment. . Therefore, the memory cell of this embodiment can also be formed in substantially the same process as the N-channel MISFET of the peripheral circuit.

[Third Embodiment] FIG. 18 is a sectional view of a memory cell according to a third embodiment.

In the third embodiment, the end of the source region on the channel region side is composed of a relatively low concentration n-type semiconductor region 21,
The end of the drain region on the side of the channel region is composed of a high-concentration n + type semiconductor region 9 having a shallow junction. Since the end of the source region is composed of the n-type semiconductor region 21, the source region, that is, the n + -type semiconductor regions 10 and n.
The avalanche breakdown voltage between the type semiconductor region 21 and the semiconductor substrate 1 is increased. This makes it possible to increase the erase voltage applied to the source region when erasing information. The n-type semiconductor region 21 is formed to a depth of about 0.2 μm.

On the other hand, the channel region side of the drain region is n
Since it is the + type semiconductor region 9, the electric field applied between the n + type semiconductor region 9 and the semiconductor substrate 1 can be strengthened.

Therefore, the generation of hot carriers at the time of writing information can be increased.

N + type semiconductor region 9 and n type semiconductor region 2
The length of 1 in the channel length direction is defined by the sidewall spacer 12.

Next, a method of manufacturing the memory cell of this embodiment will be described.

19 to 23 are sectional views of the memory cell in the manufacturing process.

As shown in FIG. 19, the floating gate electrode 5, the second gate insulating film 6, the control gate electrode 7 (word line WL), and the silicon oxide film 8 are formed as in the first embodiment.

Next, as shown in FIG. 20, a mask 22 made of a resist film is formed on the semiconductor substrate 1 so as to cover the drain region of the MISFET which is a memory cell. The mask 22 is provided so as to cover a region where a P-channel MISFET forming a peripheral circuit such as a buffer circuit, a decoder circuit, or a sense amplifier circuit is formed. Next, by ion implantation, an n-type impurity such as phosphorus (P) is added at 1 × 10 ¹⁴ to
The n-type semiconductor region 21 is formed by introducing about 1 × 10 ¹⁵ atoms / cm ² . After that, the mask 22 is removed.

Next, as shown in FIG. 21, a mask 23 made of a resist film is formed on the semiconductor substrate 1 so as to cover the source region and the ground line region of the memory cell. The mask 23 is formed so as to cover the P-channel MISFET region and the N-channel MISFET region that form the peripheral circuit. Next, an n-type impurity such as arsenic (As) is introduced by ion implantation at about 1 × 10 ¹⁵ atoms / cm ² to form the n + -type semiconductor region 9. After ion implantation,
The mask 23 is removed.

Next, as shown in FIG. 22, sidewall spacers 12 made of a silicon oxide film are formed. The sidewall spacer 12 is an N channel M of the peripheral circuit.
It is also formed on the side of the gate electrode of the ISFET and the P-channel MISFET.

Next, the P-channel MISFET of the peripheral circuit
23 is covered with a mask made of a resist film, and then an n-type impurity such as arsenic (As) is ion-implanted at 1 × 10 ¹⁶ atoms / c as shown in FIG.
About n ^{2 is} introduced to form the n + type semiconductor region 10. n
The + type semiconductor region 10 is an N channel MISF of the peripheral circuit.
It is also formed in the source and drain regions of ET. After the ion implantation, the mask made of the resist film covering the P-channel MISFET region of the peripheral circuit is removed.

Through the steps up to this point, MI which is a memory cell is
In the SFET, the end of the source region is composed of the n-type semiconductor region 21, and the end of the drain region is composed of the n + -type semiconductor region 9. In addition, the peripheral channel N-channel MISFE
In T, the ends of the source and drain regions are n-type semiconductor regions 2
It is composed of 1.

The mask 23 shown in FIG. 21 is formed so as to cover only the entire region of the P-channel MISFET region and the drain region of the N-channel MISFET region in the peripheral circuit region, and the source region of the N-channel MISFET is formed. You may form so that it may be exposed. In this way, in the N-channel MISFET of the peripheral circuit, the end of the source region is composed of the n + type semiconductor region 9 and the end of the drain region is composed of the n type semiconductor region 21. The electric field at the end of the drain region is relaxed, and the end of the source region is n +
Since it is a mold, the transconductance is enhanced.

The subsequent manufacturing process is similar to that of the first embodiment.

[Embodiment 4] FIG. 24 is a sectional view of a memory cell according to Embodiment 4.

In the fourth embodiment, the end of the source region on the channel region side is composed of the n-type semiconductor region 21, the end of the drain region is composed of the n + -type semiconductor region 9, and the n + -type semiconductor region 9 is further composed. The p-type semiconductor region 24 is provided in the lower part. The end of the p-type semiconductor region 24 on the channel region side is defined by the floating gate electrode 5 and the control gate electrode 7, and the length in the gate width direction is defined by the field insulating film 2. p-type semiconductor region 24
Is provided only under the n + type semiconductor region 9,
It is not provided below the n + type semiconductor region 10. Therefore, the generation efficiency of hot carriers at the end of the drain region can be increased.

The p-type semiconductor region 24 may be formed by implanting a p-type impurity such as boron (B) in the ion implantation step in FIG. 21 of the manufacturing process of the embodiment 3 before forming the n + -type semiconductor region 9. . By doing so, the p-type semiconductor region 24 can be formed without increasing the number of steps.

If the p-type semiconductor region 24 is formed in the step shown in FIG. 21, the N-channel MISF forming the peripheral circuit is formed.
The p-type semiconductor region 24 is also formed at the end of the drain region of ET. The p-type semiconductor region 24 in this peripheral circuit
Is effective in reducing the extension of the depletion layer in the drain region. That is, it is effective for preventing punch-through. In order to prevent the p-type semiconductor region 24 from being formed in the N channel MISFET of the peripheral circuit, the resist mask 23 formed in the step shown in FIG. 21 is used not only in the P channel MISFET region of the peripheral circuit region but also in the N channel. The p-type semiconductor region 24 may be formed only in the memory cell region by ion implantation after completely covering the MISFET. The n + type semiconductor region 9 is formed by removing the mask and forming a mask made of a resist film having a pattern to newly expose the drain region of the memory cell and the drain region of the N-channel MISFET of the peripheral circuit, and then performing ion implantation. do it. By doing so, the p-type semiconductor region 24 can be formed only in the memory cell.

[Fifth Embodiment] FIG. 25 is a cross-sectional view of a memory cell according to a fifth embodiment.

In the fifth embodiment, the P-type semiconductor region 24 is formed not only on the bottom of the n + -type semiconductor region 9 of the drain region but also on the side surface A on the channel side. p-type semiconductor region 2
4 is not provided below the n + type semiconductor region 10. p on the side surface A of the n + type semiconductor region 9 on the channel region side.
By forming the type semiconductor region 24, the electric field at the end of the drain region is strengthened, and the generation efficiency of hot carriers at the time of writing information can be increased.

The p-type semiconductor region 24 in the fifth embodiment.
Can be formed in the drain region of the N-channel MISFET of the peripheral circuit in the same step as the p-type semiconductor region 24 in the fourth embodiment. Further, it may not be formed in the peripheral circuit.

[Sixth Embodiment] FIG. 26 is a sectional view of a memory cell according to a sixth embodiment.

In the sixth embodiment, the drain region of the memory cell is formed only by the n + type semiconductor region 10 having a deep junction of about 0.25 μm, and the source region is formed only by the n + type semiconductor region 10 having a deep junction of about 0.25 μm. And the source region is an n + type semiconductor region 10 having a deep junction of about 0.25 μm and an n− type semiconductor region 11 provided so as to cover the n + type semiconductor region 10.
It is composed of and. Since the n + type semiconductor region 10 has a deep junction, the concentration distribution is gentle. Further, since the n − type semiconductor region 11 is provided so as to cover it, the concentration distribution of the source region is further relaxed. Therefore,
The junction breakdown voltage between the source region and the semiconductor substrate 1 is increased, and the information erasing characteristic is improved.

The n--type semiconductor region 11 is shown in FIG.
The n-type semiconductor region 11 of FIG.
In the peripheral circuit region, the mask 20 shown in FIG.
By opening the drain region of the N-channel MISFET and covering the source region and the P-channel MISFET region, the N-channel MFET of the peripheral circuit can be formed in a double drain structure only in the drain region.

[Embodiment 7] FIG. 27 is a plan view of a part of the memorial array of Embodiment 7, FIG. 28 is a sectional view taken along the line AA of FIG. 27, and FIG. 29 is an equivalent circuit of a memory cell array.

In the seventh embodiment, the selection M is performed separately from the storage element Qm.
ISFETQr is provided, and one of these two MISFETs is provided.
One memory cell is configured.

27 to 29, the storage element Qm
The MISFET is a first gate insulating film 4 made of a silicon oxide film, a floating gate electrode 5, a second gate insulating film 6 made of a silicon oxide film, a control gate electrode 7, a source region as in the memory cell of the first embodiment. N + type semiconductor regions 9 and 10 and n− type semiconductor region 1
1 and n + type semiconductor regions 9 and 10 which are drain regions. The newly provided selective MISFET includes a gate insulating film 6 made of a silicon oxide film formed by oxidation of the surface of the semiconductor substrate 1, for example, a gate electrode 26 made of a second-layer polycrystalline silicon film, and a channel region side of a source / drain region. The n-type semiconductor region 25 forming the end portion of the n-type semiconductor region 25 and the n + type semiconductor region 10 forming the part of the source / drain region separated from the channel region. The gate electrode 26 extends in a direction intersecting the direction in which the data line DL extends to form the first word line WL ₁ . In parallel with this, the second word line WL ₂ formed integrally with the control gate electrode 7 extends. The n + type semiconductor region 10 forming a part of the drain region of the selected MISFET Qr at the time of reading is also common to the n + type semiconductor region 10 being a part of the source region of the MISFET Qm at the time of reading. In the two memory cells connected to the same data line DL through the same connection hole 14, the selection MISFE of each memory cell is selected.
N + type semiconductor region 1 which is a part of the drain region of TQr
0 is united. As shown in FIG. 27, the selection MI
The channel width of SFETQr is MISFE which is a memory element.
It is larger than that of TQm. MISFET Qm
Of the word lines WL ₁ and WL ₂
29, each ground line GL is connected to N-channel MISFETs Qs ₁ and Qs ₂ as shown in FIG.

When writing information, all MISF
ETQs ₂ becomes conductive and all MISFETQ
s ₁ becomes non-conducting and each ground line GL is set to the ground potential Vss of the circuit, for example, 0V. The first word line WL ₁ connected to the selected memory cell is set to Vpp, for example, 13V. The other first word lines WL ₁ have the ground potential Vss, for example, 0V. The second word line W ₂ connected to the selected memory cell is set to the write potential Vpp, eg, 13V, and the other second word lines WL ₂ are floating or ground potential Vss, eg, 0V.
The data line DL connected to the selected memory cell is H
The level is set to, for example, 5 V, and the other data lines DL are set to the ground potential Vss.

At the time of reading information, MISFET
Qs ₁ is turned off, MISFET Qs ₂ is turned on, and the ground line GL is set to the ground potential Vss of the circuit, for example, 0V. The first word line WL ₁ connected to the selected memory cell is set to the power supply potential. Other word lines WL ₁
Is set to the ground potential Vss. The second word line WL ₂ forming the memory element is set to the power supply potential Vcc of all, but is set to the ground potential Vss when Vth after erasing the memory element is negative, for example, −3V. The data line DL connected to the selected memory cell is applied with about 1 V, and the other data lines DL are set to Vss or floating state.

When erasing information, all MISFETs Q
s ₁ is made conductive, and all MISFETs Qs ₂ are made non-conductive. That is, all the ground lines GL have the erase potential Vpp.
For example, it is set to 13V. All the second word lines WL ₂ are set to the ground potential Vss. First word line and data line D
L is set to ground potential or floating. When these conditions are set, information of all memory cells is collectively erased.

As described above, the following effects can be obtained by the configuration of the memory cell of this embodiment.

(1) Select memory cell MISFETQr
And the storage element Qm,
Since it is not necessary to keep th substantially constant, the configuration of the erase circuit can be simplified.

(2) Since the ends of the source and drain regions of the selective MISFET Qr are made up of the n--type semiconductor region 25, the generation of hot carriers can be reduced.

Although the memory element in this embodiment is composed of the memory cell described in Embodiment 1, Embodiment 2
Any of the memory cells of the sixth embodiment may be applied.

Next, a method of manufacturing the memory cell of this embodiment will be described.

30 to 35 are plan views or sectional views of the memory cell in the manufacturing process.

As shown in FIG. 30, after the first gate insulating film 4 (not shown) having a film thickness of about 100 Å is formed by oxidizing the surface of the semiconductor substrate 1, the entire surface of the semiconductor substrate 1 is formed by, for example, CVD. A polycrystalline silicon film to be the floating gate electrode 5 is formed on the film, and this is patterned by etching using a film made of a resist film. In this etching, the floating gate electrodes 5 of the two memory cells connected to the same data line DL and sharing the ground line GL are integrally patterned. Therefore, the gate electrode 26 (first word line W
The surface portion provided with L ₁ ) is exposed from the polycrystalline silicon film 5.

Next, the exposed surface of the polycrystalline silicon film 5 and the surface of the semiconductor substrate 1 exposed from the polycrystalline silicon film 5 are oxidized to oxidize the second gate insulating film 6 and the selective MI.
The gate insulating film 6 of the SFET Qr is formed. In the step of forming the gate insulating film 6, the gate insulating film of the MISFET forming the peripheral circuit such as the decoder circuit can be formed.
After this, the control gate electrode 7 (second word line WL
₂ ) and the gate electrode 26 (second word line WL ₂ ), and in order to form the gate electrode of the MISFET of the peripheral circuit, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD, and this is formed from the resist film. 31. As shown in FIG. 31, gate electrodes 7 and 26 are formed by patterning by etching using the mask. The gate electrode of the MISFET of the peripheral circuit can also be formed by this etching process. The gate electrodes 7 and 26 are M
The refractory metal film or the silicide film may be formed on the refractory metal film of o, W, Ta, Ti or the like or the silicide film thereof or the polycrystalline silicon film. Next, the exposed surfaces of the gate electrodes 5, 7, 26 and the semiconductor substrate 1 are oxidized to form a silicon oxide film 8.

Next, as shown in FIG. 32, a mask 2 made of a resist film for forming the n--type semiconductor region 11 is formed.
7 is formed on the semiconductor substrate 1. The mask 27 is provided in a pattern that exposes the source region of the storage element Qm at the time of reading information in the memory cell region, and is provided in a pattern that covers the entire region in the peripheral circuit region. next,
An n-type impurity such as phosphorus (P) is introduced into the surface of the semiconductor substrate 1 exposed from the mask 27 by ion implantation to form the n + -type semiconductor region 11. After this, mask 2
Remove 7.

Next, as shown in FIG. 33, the semiconductor substrate 1
An n-type impurity such as arsenic (As) or phosphorus is introduced into the surface of the substrate by ion implantation using the gate electrodes 5, 7 and 26 as a mask to form an n-type semiconductor region 25. In this ion implantation process, N channel M that constitutes the peripheral circuit
It is possible to form low concentration layers in the source and drain regions of the ISFET. The region where the P-channel MISFET is provided is covered with a mask made of a resist film. This mask is removed after the ion implantation.

Next, as shown in FIG. 34, the storage element Qm
Of the resist film for forming the n + type semiconductor region 9 forming part of the source and drain regions of
Are formed on the semiconductor substrate 1. The mask 28 is provided in a pattern that covers the source and drain regions of the select MISFET Qr in the memory cell region, and is provided in a pattern that covers the entire peripheral circuit region. Next, the gate electrodes 5 and 7
Is used as an ion implantation mask to introduce an n type impurity such as arsenic (As) into the surface of the semiconductor substrate 1 exposed from the mask 28 by ion implantation to form an n + type semiconductor region 9. The mask 28 is removed after the ion implantation.

Next, as shown in FIG. 35, for example, CVD
Silicon oxide film and reactive ion etching (RI
The sidewall spacer 12 is formed by using E).
The sidewall spacer 12 is an N that constitutes a peripheral circuit.
It is formed on the gate electrodes of both the channel MISFET and the P-channel MISFET. Next, P channel MI
After covering the SFET region with a mask made of a resist film, the sidewall spacer 12 and the gate electrodes 5 and 7 are formed.
Alternatively, an n-type impurity such as arsenic (As) is introduced into the surface of the semiconductor substrate 1 by ion implantation using 26 as a mask to form the n + -type semiconductor region 10. The high-concentration regions of the source and drain regions of the N-channel MISFET for forming the peripheral circuit are also formed at the same time. After the ion implantation, the mask made of the resist film covering the P channel region is removed. Thereafter, the memory cell region and the N-channel MISFET region of the peripheral circuit are covered with a mask made of a resist film, and a p-type impurity such as boron (B) is introduced into the P-channel MISFET region to form a p + type semiconductor region which is a source / drain region. To form. The mask made of the resist film is removed after the ion implantation.

Since the subsequent steps are the same as those in the manufacturing method of the first embodiment, description thereof will be omitted.

As described above, the memory cell selection M
The ISFET Qr and the MISFET Qm that is a memory element can be formed in the same process.

In addition, the N channel MI which constitutes the peripheral circuit
The SFET and the memory cell can be formed in the same process.

[Embodiment 8] FIG. 36 is a sectional view of a memory cell.

In this embodiment, one memory cell is used as one MISFE.
It is configured by T, the source region thereof is provided with an n − type semiconductor region 11 having a deep junction, and the drain region is provided with a p type semiconductor region 24 having a deep junction. The ends of the source and drain regions on the channel region side are formed by the n + type semiconductor region 9 having a shallow junction of about 0.1 μm. The portion separated from the channel region is composed of the n + type semiconductor region 10 having a deep junction of about 0.25 μm. n
The − type semiconductor region 11 has a deeper junction than the n + type semiconductor regions 9 and 10 which are part of the source and drain regions. In the channel region, the n + type semiconductor region 9
And the semiconductor substrate 1. Since the n − type semiconductor region 11 is provided, the junction breakdown voltage between the source region and the semiconductor substrate 1 is high. Therefore,
Erase voltage Vpp applied to the source region when erasing information
Can be increased to about 13 V, so that the erasing time can be shortened. In addition, erasure can be performed reliably.

On the other hand, in the drain region, the p-type semiconductor region 24 reaches below the n + -type semiconductor regions 9 and 10. In the channel region, p type semiconductor region 24 is interposed between n + type semiconductor region 9 and semiconductor substrate 1. The configuration is such that the electric field generated between the drain region and the semiconductor substrate 1 is strengthened. The generation efficiency of hot carriers at the time of writing information is improved, and the writing voltage can be reduced to 5 V or less.

Next, a method of manufacturing the memory cell of this embodiment will be described.

37 to 41 are sectional views of the memory cell in the manufacturing process.

As shown in FIG. 37, as in the first embodiment,
The first gate insulating film 4, the floating gate electrode 5, the second gate insulating film 6, the control gate electrode 7 (word line WL), and the silicon oxide film 8 are formed. After this, n-
A mask 29 made of a resist film for forming the type semiconductor region 11 is formed on the semiconductor substrate 1. The mask 29 is formed in a pattern in which the source region of the memory cell and the ground line GL are exposed. The peripheral circuit region is entirely covered with the mask 29. Next, an n-type impurity such as a phosphorus (P) dose amount of 10 ¹³ to 10 ¹⁴ atoms / cm ² is introduced into the surface of the semiconductor substrate 1 exposed from the mask 29 and the gate electrodes 5 and 7 by ion implantation to n−. The type semiconductor region 11 is formed. The mask 29 is removed after the ion implantation.

Next, as shown in FIG. 38, the source region of the memory cell and the ground line GL region are covered with a mask 30 made of a resist film. The mask 30 is provided so as to cover the entire peripheral circuit region. Then, the surface of the semiconductor substrate 1 exposed from the mask 30 and the gate electrodes 5 and 7 is a p-type impurity such as a boron (B) dose amount of 2 × 10 ^{12 to} 5 × 10 ^12.
The p-type semiconductor region 24 is formed by introducing atoms / cm ² . After that, the mask 30 is removed. After that, the n − type semiconductor region 11 and the p type semiconductor region 24 may be expanded by annealing.

Next, as shown in FIG. 39, using the gate electrodes 5 and 7 as a mask, an n-type impurity such as arsenic (As) is introduced into the surface of the semiconductor substrate 1 by ion implantation to obtain n.
A + type semiconductor region 9 is formed. In this ion implantation step, the peripheral circuit region is covered with a mask made of a resist film. The ion implantation is performed twice, and the first ion implantation is performed with a low concentration of n-type impurities in the N-channel MISF of the memory cell region and the peripheral circuit.
It is also possible to introduce into the ET region and cover the entire peripheral circuit region with a mask made of a resist film in the second ion implantation so that the n-type impurity is not introduced into the peripheral circuit region. In this way, the shallow junction n + type semiconductor region 9 can be formed in the memory cell region, and the shallow junction n− type semiconductor region can be formed in the N channel MISFET region of the peripheral circuit.

Next, as shown in FIG. 40, for example, CVD
The side wall spacers 12 are formed by using the silicon oxide film and RIE. Sidewall spacers 12 are also formed on the sides of the gate electrode of the MISFET in the peripheral circuit.

Next, as shown in FIG. 41, the P channel M
After covering the ISFET region with a mask made of a resist film, an n-type impurity such as arsenic (A
s) is introduced to form the n + type semiconductor region 24. n +
The type semiconductor region 24 is an N-channel MISFE of the peripheral circuit.
It is also formed in the source and drain regions of T separated from the channel region. The resist mask covering the P-channel MISFET region is removed after the ion implantation. Next, after covering the memory cell region and the N-channel MISFET region of the peripheral circuit with a mask made of a resist film, a p-type impurity such as boron (B) is introduced into the P-channel MISFET region to form the p + -type source and drain regions. A semiconductor region is formed. After the ion implantation, the N-channel MIS of the memory cell area and the peripheral circuit is formed.
The mask made of the resist film covering the FET region is removed.

As described above, the memory cell and the N-channel MISFET of the peripheral circuit can be formed in the same process.

[Ninth Embodiment] FIG. 42 is a sectional view of a memory cell according to a ninth embodiment.

In this embodiment, the n− type semiconductor region 11 is provided only around the n + type semiconductor region 9 provided at the end of the source region on the channel region side, and the n− type semiconductor region 11 is provided at the end of the drain region on the channel region side. The p-type semiconductor region 24 is provided only around the provided n + -type semiconductor region 9. By providing the n − type semiconductor region 11 at the end of the source region, the junction breakdown voltage between the source region and the semiconductor substrate 1 is increased, and the erase voltage can be increased. Also, n
Since the − type semiconductor region 11 has a junction depth similar to that of the n + type semiconductor region 10 and the wraparound to the channel region is small, the threshold variation is small and the electrical characteristics of the memory cell are improved.

On the other hand, the p-type semiconductor region 24 strengthens the electric field applied between the end of the drain region and the semiconductor substrate 1. Therefore, the generation efficiency of hot carriers is improved and the write characteristics are improved. Further, the p-type semiconductor region 24 is n +
Since it is as shallow as the type semiconductor region 10, the wraparound to the channel region is small. The change in threshold value is small, and the electrical characteristics of the memory cell are improved.

Since there is no p-type semiconductor region 24 below the n + -type semiconductor region 10, the parasitic capacitance of the drain region is small.

The n-type semiconductor region 11 and the p-type semiconductor region 24 in this embodiment can be formed by the same method as the n-type semiconductor region 11 and the p-type semiconductor region 24 in the eighth embodiment.

[Embodiment 10] FIG. 43 is a sectional view of a memory cell according to Embodiment 10.

In Example 10, the n − type semiconductor region 11 having a deep junction reaching the lower part of the n + type semiconductor region 10 is provided in the source region, and the p type semiconductor region 3 is provided in the channel region.
1 is provided. The n− type semiconductor region 11 reaches the channel region. No semiconductor region is provided below the n + type semiconductor region 9 forming the end of the drain region. The junction breakdown voltage between the source region and the semiconductor substrate 1 is increased by the n − type semiconductor region 11. On the other hand, the p-type semiconductor region 31 can strengthen the electric field applied to the end of the drain region.

For the p-type semiconductor region 31, an ion implantation process of introducing a p-type impurity such as boron (B) into the channel region in order to adjust the threshold value of the memory cell can be used. The dose amount of the ion implantation for forming the p-type semiconductor region 31 is 2 × 10 ^{12 to} 5 × 10 ¹² atom.
It may be about s / cm ² . The MIS of the peripheral circuit
The ion implantation for adjusting the threshold value of the FET may be performed separately from the memory cell.

[Embodiment 11] FIG. 44 is a sectional view of a memory cell according to Embodiment 11.

In the eleventh embodiment, the p-type semiconductor region 24 having a deep junction is provided so as to surround the n + -type semiconductor regions 9 and 10 forming the drain region, and the n-type semiconductor region 32 is provided in the channel region. It is a thing. Since the p-type semiconductor region 24 is formed so as to surround the n + -type semiconductor region 9, the extension of the depletion layer at the end of the drain region is suppressed. Therefore, the generation efficiency of hot carriers at the drain end during writing can be increased.

On the other hand, the end of the source region on the channel side is
The electric field is relaxed due to the presence of the n − type semiconductor region 32.
Therefore, the erasing voltage applied to the source region when erasing information can be increased. Ion implantation for forming the n − type semiconductor region 32 is performed, for example, with arsenic (As) in a dose amount of 10 ¹¹ to 10 ¹² atoms / cm ² .

The memory cells of the eighth to eleventh embodiments may be constituted by one MISFET Qr and two selection MISFETs Qr as in the memory cell of the seventh embodiment.

Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. .

[0121]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

Since the junction breakdown voltage between the source region of the MISFET which is a memory cell and the semiconductor substrate is increased, the erase voltage Vpp applied at the time of erasing information can be increased. Thereby, the erasing efficiency can be improved.

Further, since the electric field at the end of the drain region of the MISFET which is the memory cell is configured to be strong, the write characteristic can be improved.

[Brief description of drawings]

FIG. 1 is a plan view taken along the line AA of FIG.

FIG. 2 is a plan view of the memory cell according to the first embodiment.

FIG. 3 is an equivalent circuit of the memory cell array of the first embodiment.

FIG. 4 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 5 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 6 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 7 is a plan view of the memory cell in the manufacturing process of the first embodiment.

FIG. 8 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 9 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 10 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 11 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 12 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 13 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 14 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 15 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 16 is a cross-sectional view of the memory cell in the manufacturing process of Example 1.

FIG. 17 is a cross-sectional view of the memory cell according to the second embodiment.

FIG. 18 is a cross-sectional view of a memory cell of Example 3.

FIG. 19 is a cross-sectional view in the manufacturing process of the memory cell of Example 3.

FIG. 20 is a cross-sectional view in the manufacturing process of the memory cell of Example 3.

FIG. 21 is a cross-sectional view in the manufacturing process of the memory cell according to the third embodiment.

FIG. 22 is a cross-sectional view in the manufacturing process of the memory cell according to the third embodiment.

FIG. 23 is a cross-sectional view in the manufacturing process of the memory cell of Example 3.

FIG. 24 is a cross-sectional view of a memory cell of Example 4.

FIG. 25 is a cross-sectional view of a memory cell of Example 5.

FIG. 26 is a cross-sectional view of a memory cell of Example 6.

FIG. 27 is a plan view of the memory cell according to the seventh embodiment.

28 is a cross-sectional view taken along the line AA of FIG.

FIG. 29 is an equivalent circuit of the memory cell array of the seventh embodiment.

FIG. 30 is a plan view in the manufacturing process of the memory cell of Example 7.

FIG. 31 is a cross-sectional view in the manufacturing process of the memory cell of Example 7.

FIG. 32 is a cross-sectional view in the manufacturing process of the memory cell of Example 7.

FIG. 33 is a cross-sectional view in the manufacturing process of the memory cell of Example 7.

FIG. 34 is a cross-sectional view in the manufacturing process of the memory cell of Example 7.

FIG. 35 is a cross-sectional view in the manufacturing process of the memory cell of Example 7.

FIG. 36 is a cross-sectional view of the memory cell of Example 8.

FIG. 37 is a cross-sectional view in the manufacturing process of the memory cell of Example 8.

FIG. 38 is a cross-sectional view in the manufacturing process of the memory cell of Example 8.

FIG. 39 is a cross-sectional view in the manufacturing process of the memory cell of Example 8.

FIG. 40 is a cross-sectional view in the manufacturing process of the memory cell of Example 8.

FIG. 41 is a cross-sectional view in the manufacturing process of the memory cell of Example 8.

FIG. 42 is a cross-sectional view of the memory cell of Example 9.

FIG. 43 is a cross-sectional view of the memory cell of Example 10.

FIG. 44 is a cross-sectional view of the memory cell of Example 11.

[Explanation of reference numerals] 1 ... Semiconductor substrate, 2 ... Field insulating film, 3 ... Channel stopper region, 4 ... First gate insulating film, 5 ...
Floating gate electrode, 6 ... Second gate insulating film,
7 ... Control gate electrode, 8 ... Silicon oxide film, 9, 10 ... N + type semiconductor region (constituting a part of source and drain), 11 ... N− type semiconductor Region (constituting a part of the source region), 12 ... Sidewall spacer, 13 ... Insulating film, 14 ... Connection hole, 15, 16
.... Decoder, 17 ..., Sense amplifier, Qm ... Memory cell, DL ... Data line, WL ... Word line, GL ...
Ground wire, 18 ..., Base film (silicon oxide film), 19 ...
Thermal oxidation mask (silicon nitride film), 20, 22, 23,
27, 28, 29, 30 ... Resist film, 21 ... N-
Type semiconductor region (constituting a part of the source region), 24 ...
..P-type semiconductor region (enhancing the electric field at the end of the drain region), 25 ... n-type semiconductor region (constituting a part of the source and drain of the selected MISFET), 26 ...
The gate electrode of the ISFET, 31 ... P-type semiconductor region (intensifies the electric field at the end of the drain region), 32 ... N-type semiconductor region (constituting a part of the source region).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Kume 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Toshihisa Tsukada 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Hideaki Yamamoto 1-280, Higashi Koikekubo, Kokubunji, Tokyo Hitachi Co., Ltd. Central Research Laboratory (56) References JP 61-127179 (JP, A) JP 62-119796 (JP) , A) JP-A-57-114282 (JP, A)

Claims (23)

(57) [Claims] 1. A control gate electrode, a floating gate electrode, a second gate insulating film formed between the two gate electrodes, and a first gate formed between a semiconductor substrate and the floating gate electrode. An insulating film,
A memory cell including a first and a second semiconductor region formed in the semiconductor substrate and a channel region formed between the first and the second semiconductor region in the semiconductor substrate; Carriers are discharged from the floating gate electrode to the first semiconductor region by tunneling through the first gate insulating film,
In a method of manufacturing a semiconductor memory device in which information is read from a second semiconductor region by applying a predetermined potential to the semiconductor region, a floating gate electrode on the first gate insulating film on a semiconductor substrate of a first conductivity type, A first step of forming a second gate insulating film on the floating gate electrode, and a control gate electrode on the second gate insulating film so that both ends thereof overlap each other; and after the first step, a second step of forming a first semiconductor region of a second conductivity type by introducing a self-aligning manner impurities in the semiconductor substrate in the semiconductor substrate with respect to one end portion of the control gate electrode, the first After the second step , impurities are introduced into the other end of the control gate electrode in a self-aligned manner to form a second semiconductor region of the second conductivity type in the semiconductor substrate. The band, a third step of the overlap amount between the second semiconductor region and said floating gate electrode is formed to be smaller than the amount of overlap between the first semiconductor region and said floating gate electrode, the third After the above step, the control gate electrode
And for both ends of the floating gate electrode
Fourth process for self-aligning formation of sidewall spacers
And, after the fourth step, the first semiconductor region or
For at least one of the second semiconductor regions,
Control gate electrode, floating gate electrode and
The semiconductor is self-aligned with the sidewall spacer.
By introducing impurities into the body substrate,
The second conductivity type of the first conductivity type having a high impurity concentration and a deep junction depth .
3. A method of manufacturing a semiconductor memory device, comprising: a third step of forming a semiconductor region . 2. The third semiconductor in the fifth step.
The region is formed at least on the side of the second semiconductor region.
The manufacturing of the semiconductor memory device according to claim 1, wherein
Build method. 3. The third semiconductor in the fifth step.
The regions are the first semiconductor region side and the second semiconductor region side.
It is formed in both of.
Manufacturing method of semiconductor memory device. 4. After the second step , impurities are introduced into the other ends of the control gate electrode and the floating gate electrode in a self-aligned manner so as to form at least the second semiconductor region side of the channel region. portion in the semiconductor memory according to any of claims 1 to 3, characterized in that it comprises a sixth step of forming a fourth semiconductor region of the first conductivity type having a higher impurity concentration than said semiconductor substrate Device manufacturing method. Wherein in the third step, the second semiconductor region, claims 1 to 4, characterized in that it is formed so that the junction depth than the first semiconductor region is shallower
A method for manufacturing a semiconductor memory device according to any one of items 1 to 5. 6. A control gate electrode, a floating gate electrode, a second gate insulating film formed between the two gate electrodes, and a first gate formed between the semiconductor substrate and the floating gate electrode. An insulating film,
A memory cell including a first and a second semiconductor region formed in the semiconductor substrate and a channel region formed between the first and the second semiconductor region in the semiconductor substrate; A method of manufacturing a semiconductor memory device, wherein the carrier is released from the floating gate electrode to the first semiconductor region by tunneling through the first gate insulating film, the method being the first method on a semiconductor substrate of a first conductivity type. A first step of forming a floating gate electrode on the gate insulating film, a second gate insulating film on the floating gate electrode, and a control gate electrode on the second gate insulating film so that both ends thereof overlap each other. If, after the above first step, self-aligned to one end of the control gate electrode and floating gate electrode A second step of forming a first semiconductor region of a second conductivity type in said semiconductor substrate by introducing impurities into, after the said second step, with respect to both end portions of the control gate electrode and floating gate electrode in the semiconductor substrate by introducing a self-aligning manner impurities Te, the impurity
A second conductivity type second semiconductor region having a higher impurity concentration and a shallower junction depth than that of the first semiconductor region before the introduction of Al .
The introducing shallower impurities than the junction depth of the first semiconductor region
3 step, after the 3rd step, a 4th step of forming side wall spacers in self-alignment with both ends of the control gate electrode and the floating gate electrode, and 4th step after the 4th step. , The first semiconductor region or
For at least one of the second semiconductor regions, the control gate electrode, the floating gate electrode, and
Impurities are introduced in a self-aligned manner with respect to the sidewall spacers so that the impurity concentration is higher than that of the first and second semiconductor regions and the junction depth is higher than that of the first and second semiconductor regions in the semiconductor substrate. A fifth step of forming a deep second conductivity type third semiconductor region, and a method of manufacturing a semiconductor memory device. 7. After the second step , impurities are introduced into the other ends of the control gate electrode and the floating gate electrode in a self-aligned manner, and at least the second semiconductor region side of the channel region is formed. 7. The method of manufacturing a semiconductor memory device according to claim 6, further comprising a sixth step of forming a fourth semiconductor region of the first conductivity type having a higher impurity concentration than that of the semiconductor substrate in the portion. 8. The third semiconductor in the fifth step.
The region is formed at least on the side of the second semiconductor region.
8. The method according to claim 6 or 7, characterized in that
Of manufacturing a semiconductor memory device. 9. The third semiconductor in the fifth step.
The regions are the first semiconductor region side and the second semiconductor region side.
7. The method according to claim 6 or claim 6, characterized in that
Item 8. A method of manufacturing a semiconductor memory device according to any one of items 7. 10. A control gate electrode, a floating gate electrode, a second gate insulating film formed between the two gate electrodes, and a first gate formed between the semiconductor substrate and the floating gate electrode. A memory cell including an insulating film, first and second semiconductor regions formed in the semiconductor substrate, and a channel region formed between the first and second semiconductor regions in the semiconductor substrate, and a peripheral circuit. The memory cell is configured to release carriers from the floating gate electrode to the first semiconductor region by tunneling through the first gate insulating film.
A method of manufacturing a semiconductor memory device, wherein information is read from a second semiconductor region by applying a predetermined potential to the semiconductor region, wherein the semiconductor cell is formed on the semiconductor substrate in a memory cell formation region of a first conductivity type semiconductor substrate. A floating gate electrode is formed on the first gate insulating film, a second gate insulating film is formed on the floating gate electrode, and a control gate electrode is formed on the second gate insulating film so that both ends thereof overlap each other, and A first step of forming a gate insulating film of a MISFET on the semiconductor substrate and a gate electrode of the MISFET on the gate insulating film in a peripheral circuit formation region of a semiconductor substrate; and, after the first step, In the memory cell formation region of the semiconductor substrate, with respect to one end of the control gate electrode and the floating gate electrode, In a peripheral circuit formation region of the semiconductor substrate after the second step of introducing impurities in a self-aligning manner to form a first semiconductor region of the second conductivity type in the semiconductor substrate and after the first step . An impurity is introduced into both ends of the gate electrode in a self-aligned manner to have a second conductivity type having a lower impurity concentration in the semiconductor substrate than the first semiconductor region, and the source and drain regions of the MISFET. After the third step of forming the first region used as a substrate and the second and third steps, in a peripheral circuit forming region of the semiconductor substrate, self-aligning with both ends of the gate electrode of the MISFET. forming a sidewall spacer, and forming a self-aligned manner sidewall spacer at opposite ends of the control gate electrode and floating gate electrode in the memory cell region 4 steps
And after the fourth step, in the peripheral circuit formation region of the semiconductor substrate, the gate electrode of the MISFET and its size are formed.
Introducing impurities in self-alignment with the sidewall spacer
However, in the memory cell area of the semiconductor substrate,
Control gate electrode, floating gate electrode and
Impurity is self-aligned with the sidewall spacer
And a fifth step of forming a third semiconductor region of the second conductivity type having a higher impurity concentration and a deeper junction depth in each region than in the first region. Method of manufacturing semiconductor memory device. 11. The semiconductor substrate according to the fifth step.
The third semiconductor region in the memory cell region of the plate is small.
At least the first semiconductor region is formed.
The method of manufacturing a semiconductor memory device according to claim 10. 12. The semiconductor substrate in the fifth step
The third semiconductor region in the memory cell region of the plate is
Control gate electrode, floating gate electrode
And both sides of the sidewall spacer
11. The semiconductor memory device according to claim 10, wherein
Manufacturing method of the device. 13. In the second step, in the step of forming the first semiconductor region, a mask covering the peripheral circuit forming region and a part of the memory cell forming region is used,
11. The method of manufacturing a semiconductor memory device according to claim 10 , wherein the impurities are introduced into one end of the control gate electrode and the floating gate electrode in a self-aligned manner. 14. In the third step, in the memory cell forming region of the semiconductor substrate, impurities are introduced in a self-aligned manner to the other end of the control gate electrode and the floating gate electrode. 11. The method of manufacturing a semiconductor memory device according to claim 10 , further comprising the step of forming a second semiconductor region of the second conductivity type therein. 15. The semiconductor substrate in the third step.
Forming the first region in the peripheral circuit formation region of the plate
At the same time, in the memory cell formation region of the semiconductor substrate,
Te, the control gate electrode, and by introducing a self-aligning manner impurities relative to the other end of the floating gate electrode, to claim 10, characterized in that a second semiconductor region in said semiconductor substrate A method for manufacturing the semiconductor memory device described. 16. After the third step, in the memory cell formation region of the semiconductor substrate, impurities are introduced in a self-aligned manner into the other end of the control gate electrode and the floating gate electrode, claims a fourth semiconductor region of a first conductivity type having at least the second semiconductor region side higher impurity concentration than the semiconductor substrate in a portion of the channel region, characterized in that it comprises a step of deeper than the second semiconductor region Item 16. A method of manufacturing a semiconductor memory device according to Item 15 . 17. the third semiconductor region, claim 1, characterized in that it is deeper than the fourth semiconductor region
7. The method for manufacturing a semiconductor memory device according to 6 . 18. The step of forming the fourth semiconductor region,
One of the peripheral circuit formation region and the memory cell formation region
17. The method of manufacturing a semiconductor memory device according to claim 16 , wherein the impurity is introduced into the control gate electrode and the floating gate electrode in a self-aligned manner by using a mask covering the portion . 19. A control gate electrode, a floating gate electrode, a second gate insulating film formed between the two gate electrodes, and a first gate formed between the semiconductor substrate and the floating gate electrode. A memory cell including an insulating film, first and second semiconductor regions formed in the semiconductor substrate, and a channel region formed between the first and second semiconductor regions in the semiconductor substrate, In the memory cell, carriers are released from the floating gate electrode to the first semiconductor region by tunneling through the first gate insulating film.
In a method of manufacturing a semiconductor memory device in which information is read from a second semiconductor region by applying a predetermined potential to the semiconductor region, a floating gate electrode on the first gate insulating film on a semiconductor substrate of a first conductivity type, A first step of forming a second gate insulating film on the floating gate electrode and a control gate electrode on the second gate insulating film so that both ends thereof overlap each other; and, after the first step, A second step of introducing an impurity into the semiconductor substrate in a self-aligning manner with respect to one end of the control gate electrode to form a first conductivity type first semiconductor region in the semiconductor substrate; After the step 2, the second conductivity type second semiconductor is introduced into the semiconductor substrate by introducing impurities into the other end of the control gate electrode in a self-aligned manner. A third step of forming a region such that an overlap amount between the second semiconductor region and the floating gate electrode is smaller than an overlap amount between the first semiconductor region and the floating gate electrode, After the second step, impurities are introduced into the other ends of the control gate electrode and the floating gate electrode in a self-aligned manner, and the semiconductor is introduced into at least the second semiconductor region side of the channel region. A method of manufacturing a semiconductor memory device, further comprising a fourth step of forming a third semiconductor region of the first conductivity type having an impurity concentration higher than that of a substrate. 20. After the third step, a fifth step of forming a sidewall spacer in a self-aligned manner with respect to the both ends of the control gate electrode and the floating gate electrode; and a fifth step. After that, in at least one of the first semiconductor region and the second semiconductor region, impurities are introduced into the semiconductor substrate in a self-aligned manner with respect to the control gate electrode, the floating gate electrode, and the sidewall spacer, 20. A sixth step of forming a third semiconductor region of the second conductivity type, the impurity concentration of which is higher than that of the second semiconductor region, and the junction depth of which is deeper than that of the second semiconductor region. Method. 21. The method of manufacturing a semiconductor memory device according to claim 20, wherein in the sixth step, the third semiconductor region is formed at least on the second semiconductor region side. 22. The semiconductor memory according to claim 20, wherein in the sixth step, the third semiconductor region is formed on both the first semiconductor region side and the second semiconductor region side. Device manufacturing method. 23. The first gate insulating film is formed with a substantially uniform thickness between the first semiconductor region and the second semiconductor region.
A method for manufacturing a semiconductor memory device according to any one of items 1 to 5.