JP2770416B2 - Semiconductor storage device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device, and more particularly, to a one-transistor memory cell including one transistor and one capacitor.

[Conventional technology]

In the MOS memory, a one-transistor type memory cell including one transistor for transfer and one capacitor for storing information has become mainstream with high integration.
In addition, transistors with a gate length of about 1 μm have been used with miniaturization and high performance of transistors.
In order to maintain the reliability of the transistor at that time, a structure in which the source and drain impurity diffusion layers are formed using two impurities is used.

Hereinafter, a conventional example will be described with reference to FIGS. 3 and 4. FIG. 4th
FIG. 1 is a circuit diagram of a part of a semiconductor memory circuit using one-transistor memory cells. In the figure, 41 is a sense amplifier, 42 is a transfer transistor, 43 is a storage capacitor, 44
Is a digit line, and 45 is a word line.

3 (a) to 3 (d) are cross-sectional views of a semiconductor chip for explaining an example of a conventional structure of one memory cell of FIG. 4 along a manufacturing process.

First, as shown in FIG. 3A, after a field oxide film 32 is formed on a P-type substrate 31 by a known selective oxidation method, a gate oxide film 33 is formed.

Next, as shown in FIG. 3 (b), a polycrystalline silicon film is grown by a CVD technique, and a storage capacitor counter electrode 34, a transfer transistor gate electrode 35, and other transistor gate electrodes are formed by a known photoetching technique. 36
To form

Next, as shown in FIG. 3C, arsenic and phosphorus are introduced by a self-aligned ion implantation technique to form N-type impurity layers 39 and 38 serving as a drain and a source.

Next, as shown in FIG. 3D, a wiring 40 using aluminum is formed by using a known technique to obtain a semiconductor memory circuit.

Here, the impurity diffusion layer 38 using arsenic and the impurity diffusion layer 39 using phosphorus have a depth introduced by ion implantation and diffusion by heat treatment after ion implantation, so that the impurity layer 37 using phosphorus uses arsenic. The impurity layer 36 is formed deeper in the substrate 31 than the impurity layer 36 (hereinafter, the depth is referred to as xj). Further, the impurity concentration of the impurity layer 37 formed by phosphorus is lower than that of the impurity layer 38 using arsenic.

That is, the presence of an n-type impurity layer having a low impurity concentration near the source below the gate electrode prevents the invention of hot electrons and increases the reliability of the transistor.

[Problems to be solved by the invention]

In the conventional semiconductor memory device described above, since the source and drain of both the transfer transistor and the other transistors are formed of two impurities of arsenic and phosphorus, xj is deep and ΔL of the transistor is large as shown in FIG. Therefore, there is a disadvantage that Lpoly cannot be shortened and there is nothing in miniaturization.

[Means for solving the problem]

According to the semiconductor recording device of the present invention, a first second conductivity type impurity layer in which a first second conductivity type impurity is selectively introduced into a surface portion of a first conductivity type region on a surface portion of a semiconductor substrate; Second
A one-transistor type memory cell having a transfer transistor having a conductive type impurity layer as a drain and a source, respectively, and a storage capacitor connected to the transfer transistor; the first second conductive type impurity layer and a second second conductive type memory cell;
Third and fourth conductive impurity layers formed in the same process as the conductive impurity layer, and third and fourth conductive impurity layers. A fifth second conductivity type impurity layer and a sixth second conductivity type impurity layer in which a second impurity different from the first impurity is selectively introduced into the layer in a self-alignment manner with them, respectively, And a double diffusion type transistor as a source. In this case, the first impurity and the second impurity can be arsenic and phosphorus, respectively.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (e) are cross-sectional views for explaining the structure of the first embodiment of the present invention along a manufacturing process.

First, as shown in FIG. 1A, a field oxide film 12 is formed to a thickness of 1 μm on a P-type substrate 11 by a known selective oxidation method, and then a gate oxide film 13 is formed to a thickness of 200 °.

Thereafter, as shown in FIG. 1 (b), a polycrystalline silicon film is grown by a CVD technique, and the storage capacitor counter electrode 14, the gate electrode 15 of the transfer transistor and other transistor electrodes are formed by using a known photo-etching technique. Form 16. At this time, the Lpoly2 dimension of the transfer transistor 15 is about 0.2 to 0.4
Set shorter by μm.

Next, as shown in FIG. 1 (c), 1 × with energy of 50keV by ion implantation of phosphorus to the transistor 16 with the exception of transfer transistor 15 of the photoresist 17 which is formed by a known photolithographic technique as a mask 10 ¹³ / The N-type impurity layer 18 is formed by introducing about ² cm ² .

Then, as shown in FIG. 1 (d), after removing the photoresist, arsenic is entirely implanted at 70 keV1 × 10 ¹⁶ /
The n-type impurity layer 19 is formed by introducing about ² cm ² .

Next, as shown in FIG. 1 (e), a wiring 20 using aluminum is formed using a known technique to obtain a semiconductor memory circuit.

That is, since phosphorus is not used as the impurity of the source and the drain of the transfer transistor, Lpoly of the transfer transistor can be shortened as compared with other transistors at the same Leff (execution channel length).

The current flowing through the transfer transistor is small due to only the transfer of electric charge to the capacitor of the memory cell, and it is less necessary to take measures against deterioration of the transistor due to hot carriers such as a transistor other than the transfer transistor (a double diffusion type transistor).

Recently, the digit line precharge level has been reduced to 1 / 2Vcc.
In many cases, the electric field applied between the source and the drain of the transfer transistor is also reduced, which eliminates the need for the transfer transistor to take measures against deterioration due to hot carriers.

FIG. 2 is a sectional view of a second embodiment of the present invention. Second
In this embodiment, the storage capacitor counter electrode 24 is formed of the first layer of polycrystalline silicon film, and the gate electrode 25 of the transfer transistor and the gate electrode 26 of the other transistors are formed of the second layer of polycrystalline silicon film. I have. Further, since the transfer transistor 25 overlaps the storage capacitor counter electrode 24, there is an advantage that the memory cell can be made smaller.

〔The invention's effect〕

As described above, according to the present invention, by using only arsenic for forming the source and drain of the transfer transistor of the memory cell, Lpoly of the transfer transistor can be reduced, and the area of the memory cell can be reduced.

That is, according to the present invention, a highly integrated semiconductor memory device can be provided without deteriorating the reliability of the entire semiconductor memory circuit. In the embodiment, an example using only the N-type transistor has been described. However, the same applies to the case where only the P-type transistor is used and the case where both the N-type and P-type transistors are used.

[Brief description of the drawings]

1 (a) to 1 (e) are longitudinal sectional views for explaining a first embodiment of the present invention along the manufacturing steps, and FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention. FIG. 3 shows (a) to (d).
FIG. 1 is a longitudinal sectional view for explaining a conventional example along a manufacturing process, and FIG. 4 is a circuit diagram of a part of a semiconductor memory circuit using a transistor type memory cell. 11,21,31 ... P-type semiconductor substrate, 12,22,32 ... Field oxide film, 13,23,33 ... Gate oxide film, 14,24,34 ... Storage capacitor counter electrode, 15,25, 35: Transfer transistor gate electrode, 16, 26, 36 ... Transistor electrode excluding transfer transistor, 17: Photoresist, 18, 28, 38
N-type impurity layer formed using phosphorus, 19, 29, 39... N-type impurity layer formed using arsenic, 20, 30, 40... Aluminum wiring, 41... Sense amplifier, 42. Transfer transistor, 43 storage capacitor, 44 digit line, 45
... word line.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/108 H01L 21/8242 H01L 21/8238 H01L 27/092 H01L 29/78

Claims (2)

(57) [Claims] A first conductive type impurity selectively introduced into a surface portion of a first conductive type region in a surface portion of a semiconductor substrate;
A one-transistor memory cell having a transfer transistor having a second conductive type impurity layer and a second second conductive type impurity layer as drains and sources, respectively, and a storage capacitor connected to the transfer transistor;
A third second conductivity type impurity layer and a fourth second conductivity type impurity layer formed in the same process as the second conductivity type impurity layer and the second second conductivity type impurity layer, and the third second conductivity type impurity layer. A fifth second conductivity type impurity layer in which a second impurity different from the first impurity is selectively introduced into the conductivity type impurity layer and the fourth second conductivity type impurity layer by self-alignment therewith, respectively; A semiconductor memory device, comprising: a double-diffusion transistor having a sixth second conductivity type impurity layer as a drain and a source, respectively. 2. The semiconductor memory device according to claim 1, wherein said first impurity and said second impurity are arsenic and phosphorus, respectively.