JPS5833710B2 - semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory devices, and more particularly to dynamic memory devices.

For example, a memory cell for a conventional dynamic memory device is a memory cell using two polycrystalline silicon layers as shown in FIG.
The transistor has a 1-capacitance configuration.

In FIG. 1, a memory cell selection transistor region 4 is formed between an N region 2 used as a column line and a capacitance region 3 formed in the middle of a semiconductor substrate 1.

Above the capacitance region 3, a first
A polycrystalline silicon layer 6 is formed, and a memory capacitance C8 is formed between the silicon layer 6 and the capacitance layer 3 with an insulating film 5 interposed therebetween.

A second polycrystalline silicon layer 8 is formed above the transistor region 4 with an insulating film 7 interposed therebetween, and is used as a gate electrode.

The entire memory cell thus formed is covered with a thick insulating layer 9 having contact holes, and the aluminum film 10 is formed in the contact holes so as to be used as row lines.

FIG. 2 is an equivalent circuit diagram of the memory cell shown in FIG. 1, and parts corresponding to those in FIG. 1 are given the same reference numerals.

The memory cell having such a configuration is a memory device that stores charge in the capacitance C8 via the transistor 4 and stores data of "1:'091" depending on the presence or absence of the amount of charge.

Therefore, the transistor 4 of the memory cell functions only as a gate for selecting the selected address.

On the other hand, the dynamic RAM memory cell proposed by P. K. Chatteyie et al. at the 15SCC held in February 1979 has a structure as shown in FIG.

This forms a P-type channel region between the two field insulating layers 12, 13, an N-shape region 15 below this channel region 14, and a polysilicon gate layer above the channel region 14. 16 is formed.

Source and drain regions 17 and 18 are formed under the field insulating layers 12 and 13, respectively.

An equivalent circuit diagram of a dynamic memory cell having such a configuration is shown in FIG.

Corresponding parts are given the same reference numbers.

In FIGS. 3 and 4, charges corresponding to 1" and "On are accumulated in the N shadow region 15 by the voltage applied to the gate 16, and the conductance of the channel 14 is changed to "1" and "091" by this charge. It changes depending on the situation.

Therefore, in this example, the charge accumulated in the N shadow area 15 is not read, and in this point the operating principle is fundamentally different from the example shown in FIGS. 1 and 2.

In the conventional examples shown in FIGS. 1 and 2, if the capacitance of the data line and digit line of the memory cell is CD, and the capacitance of the memory cell is Cs, then Cs>
A 1/20 CD is required.

Therefore, the capacitance Cs of the memory cell cannot be made very small, which is a major drawback in increasing the density of dynamic RAM.

As one method for solving these drawbacks, a method as shown in FIGS. 3 and 4 was proposed.

However, according to pages 22-23 of the I5SCC technical paper digest published in February 1979, when writing "1'", the source and drain are both connected to +5 volts, as shown in Figure 5 a and b. It is necessary to reduce the voltage to 0 volts, and to prevent it from writing, it is necessary to keep both the source and drain at +5 volts.

This means that for each memory cell, as shown in FIG.
, which means that it is necessary to wire the Y line.

In the conventional memory cell shown in Fig. 3, for example, it is not possible to use a method in which the source line is shared and only the drains are selected in the column direction, which is extremely disadvantageous in achieving high density and is not suitable for practical use. It is clear that you will not get it.

Therefore, an object of the present invention is to provide a dynamic memory device that can achieve high density.

According to the present invention, this purpose includes: a buried region of a second conductivity type formed on one surface of a semiconductor substrate of a first conductivity type;
a second buried region of a first conductivity type formed in the first buried region; a source/drain region of a second conductivity type for forming a field effect transistor in the first buried region; This is achieved by a semiconductor memory device characterized by having a gate electrode of a predetermined conductivity formed on the surface of a semiconductor substrate between source and drain regions with an insulating film interposed therebetween.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 6, an N type first buried region 22 is formed in one surface of a P type semiconductor substrate 21, and this first
A P+ type second buried region 23 is further formed within the buried region 22 .

Eleven pairs of N 2 regions 24 and 25 are formed on the surface of this first buried region 22 with a P+ region 26 in between, forming a field effect transistor.

A gate electrode 28 is formed on the surface of the first buried region 22 with a thin insulating film 27 interposed therebetween.

N+ area 24.25 has XI and Y2 lines 29.3 respectively
0 is connected, the Y1 line is connected to the gate electrode 28, and the second buried layer 23 is used as the X2 line.

An equivalent circuit diagram of the memory cell constructed in this manner is shown in FIG.

Since parts corresponding to those in FIG. 6 are given the same reference numerals, there is no need to particularly explain this equivalent circuit diagram.

However, the Y1 line is a row line used for writing,
The ¥2 line is a row line used for reading, the X1 line is a column line used for reading, and the X2 column line is used for writing.

Next, the manufacturing process of the memory cell of the embodiment shown in FIG. 6 will be explained with reference to FIG. 8.

First, as shown in Figure 8a, a P substrate, for example, a resistivity of 5
Using the photoresist 40 as a mask, phosphorus is added to the substrate 21 of 08-α through the 8102 layer 41, and the number of impurities is 5×101.
After forming the N2 layer 22 by implanting 3A-rrL2 using the ion implantation method, the N-type well 22 is formed by diffusing this phosphorus to a depth of 5μ by thermal diffusion as shown in b.

As a result, the impurity concentration of the N well 22 is approximately 1×1O17
/CrrL3.

Next, cl/l in the same figure: As shown, boron is implanted into the N region 22 by IX 1013/Crr.
A P region 23 is formed by implanting at a ratio of L2, and a P layer 42 with an impurity concentration of about 1×10'4/c3 is formed on this by epitaxial growth to a thickness of about 3 μm, as shown in figure d. .

Next, as shown in FIG.
Form layer 43.

Next, as shown in FIG. 8f, field portions 45 and 46 made of SiO,i are formed in the areas where the photoresist 44 has been removed, and then field oxidation is performed.

Through a series of heat treatments for oxidation performed at this time, the phosphorus implanted layer 43 created in the process shown in Figure e expands by diffusion, reaches the N region 22 already formed inside, and merges with it. , a memory cell structure is created in which the second buried region 23 is embedded within the first N buried region 22.

In the process shown in FIG.
It is left at the bottom of 46.

Next, place an extremely shallow layer of 1×1011/
A number of boron atoms approximately equal to CrrL2 are implanted through the insulating layer 27 to form the P region 26.

Thereafter, a polycrystalline silicon layer 28 is formed on the insulating layer 27.

This is etched into a gate shape, and using this as a mask, N+ source/drain regions 24 and 25 are formed by arsenic ion implantation.

Finally, as shown in FIG. 8g, predetermined passivation and aluminum metallization are performed to connect aluminum leads 50 and 51 to the N+ regions (source/drain) in the contact holes 48 and 49 formed in the insulating layer 47. 25, the memory cell of one embodiment according to the present invention is completely defeated.

As another example of the steps after the step d in FIG. 8, it is also possible to manufacture by the steps shown in FIG. 9.

Figure 9a shows the same process as Figure 8d; the difference is that P
1×l Q instead of epitaxial growth of region 42
The N-region 60 with a concentration of 1''/CrrL'' is lengthened by about 3μ.

This N 2 region 60 is a single crystal of silicon.

Next, as shown in FIG. 9, a portion of the N-region 60 corresponding to the field portion is removed by etching to a depth of approximately 500'oλ, and then boron is implanted into this etched portion by ion implantation. field inversion prevention layer 61
．． 62, and Wl from this prevention layer 61 and 62, respectively.

Field oxide films 64 and 65 are formed in the N region 60 at a distance of W2 (Wl-=W2) using the oxide film (S+3N4) 63 as a mask, as shown in FIG. 9C.

At this time, the field inversion prevention layer 6L62 is formed by the oxide film 64.
．． At the same time as the 65-type beam is heated, it expands and reaches the surface of the substrate 21 by diffusion.

In this way, in this step, the field inversion prevention layer 61.
It has the advantage that no special heat treatment step is required for the formation of 62.

The following steps for forming the polycrystalline silicon layer 28° insulating cover 47, contact holes 48, 49, and aluminum leads 50, 51 for the gate electrode are the same as steps f+g in FIG.

Next, in the equivalent circuit diagram of FIG.
The case of writing "" will be explained with reference to FIG. 10, and the case of writing "On" will be explained with FIG. 11.

In both FIGS. 10 and 11, the read-only lines XI and Y2 are fixed at +5 volts, respectively, as shown in a.

1P writing is performed by changing the potential of the X2 line from +5 volts to O volts as shown in FIG. 10C, and from O volts to 15 volts as shown in Y1 line b.

011 writing is performed simply by fixing the potential of the \1 line to O volts as shown in FIG. 11 and changing the voltage of the X2 line from +5 volts to 0 volts as shown in FIG.

When writing '1'', a positive charge is transferred to the gate 28 in Figure 6.
It accumulates in the P+ region 26 below.

By this, the source and drain 2
The conductance between 4 and 25 becomes smaller, and as a result,
1'' can be read.

Further, in the "0" write state, ++ charges are not accumulated on the surface of the P region 26, so the conductance between the source and drain 24, 25 increases, and as a result, a 0" can be read.

In this way, writing and reading of data of 1'' and ``0'' is performed.

Next, the advantages of this invention will be described.

First, according to the present invention, a memory cell with one transistor and one bit is obtained, the read line and the write line are separate lines, and the degree of integration is larger than that of the conventional example.

In the embodiment shown in FIG. 6, a P region 26 and a gate region 28 form a storage capacitance for holding "1" and "O".
is the field effect transistor (area 22) during readout.
, 24.

25), and the area occupied by one bit is small.

Also, in this invention, a line for write control is created.

In the embodiment of FIG. 6, this is the second buried layer 23, and its presence ensures that data can be reliably written into selected memory cells when a matrix configuration of memory cells is created.

In addition, the write control line 23 is located below the charge storage +P region 26.28, and although the number of wiring lines has increased by the line 23, the occupied area has not increased. , memory cells have been realized that facilitate the design of high-density write and read systems.

Furthermore, as is clear from the explanation of the manufacturing process in FIG.
The second buried layer can be easily formed by epitaxially growing an N-type silicon layer on the well and etching it appropriately.

In the above embodiments, an n-channel field effect transistor was used, but of course a p-channel field effect transistor may also be used.

In the embodiment shown in FIG. 6, the P 2 region 26 is used for charge storage, but the P 2 region may not be used as the charge storage portion.

In short, the gist of the present invention is a dynamic memory cell having a structure in which there is a buried layer 23, charge storage is performed on the substrate surface or other parts, and as a result, the conductance of the field effect transistor is controlled. Various modifications are possible without departing from this.

[Brief Description of the Drawings] Figure 1 is a configuration diagram showing an example of a conventional dynamic memory cell, Figure 2 is an equivalent circuit diagram of the memory cell in Figure 1, and Figure 3 is another conventional dynamic memory cell. 4 is an equivalent circuit diagram of the memory cell shown in FIG. 3, FIG. 5 is a time chart for explaining the operation of the memory cell shown in FIGS. 3 and 4, and FIG. 6 is a block diagram showing an example of a cell. 7 is an equivalent circuit diagram of the memory cell shown in FIG. 6, and FIG. 8 is an example of the process for manufacturing the dynamic memory cell of the present invention. 9 is a process diagram for explaining another example of the manufacturing process, and FIGS. 10 and 11 are operation diagrams of the memory cell of the embodiment shown in FIGS. 6 and 7. It is a time chart for explaining. 21... Semiconductor substrate, 22... First buried layer,
23... Second buried layer, 24, 25... Source/drain region, 26... Charge storage region, 27...
Thin insulating layer, 28...gate electrode, 29...X1 line 30...¥2 line.

Claims (1)

[Claims] 1 A second conductivity type formed on one surface of a semiconductor substrate of a first conductivity type.
a buried region of a conductivity type, a second buried region of a first conductivity type formed in the first buried region, and a second conductivity type for forming a field effect transistor in the first buried region. source/drain region and this source/drain region.
1. A semiconductor memory device comprising a gate electrode formed on the surface of a semiconductor substrate between drain regions with an insulating film interposed therebetween.