JP3059668B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device.
Regarding a manufacturing method , in particular, a flash type nonvolatile memory element
The present invention relates to a technique which is effective when applied to a method of manufacturing a storage device having a child .

[0002]

BACKGROUND ART Electrically Erasable a nonvolatile memory circuit of the read-only capable EEPROM (E lectrically E rasab
le P rogrammable R ead O nly M emory) nonvolatile memory device as a device type non-volatile memory device have been proposed. This nonvolatile memory element is constituted by a field effect transistor having an information storage gate electrode (floating gate electrode) and a control gate electrode (control gate electrode). The source region of the field effect transistor is connected to a source line, and the drain region is connected to a data line.

The nonvolatile memory element is called a flash type nonvolatile memory element, and is of a hot electron writing type and a tunnel erasing type. That is, the information writing operation of the nonvolatile memory element is
Hot electrons are generated in a high electric field near the drain region, and the hot electrons are injected into the information storage gate electrode. On the other hand, the information erasing operation of the nonvolatile memory element is performed by tunneling the electrons stored in the information storage gate electrode into the source region.

As described above, the EEPROM composed of the flash type nonvolatile memory elements has a feature that the capacity can be increased because the cell area can be reduced with the one-element type as described above.

In the above-mentioned EEPROM, 1
985 IED Technical Digest, pp. 468-471 (1985 IEDM Te
ch Dig. pp 468-471).

[0006]

SUMMARY OF THE INVENTION The present inventor has proposed the above-mentioned E
As a result of studying the EPROM, it has been found that the following problems occur.

(1) In order to improve the information erasing efficiency in the information erasing operation of the flash type nonvolatile memory element, it is necessary to increase the impurity concentration of the source region and make the junction depth deeper. That is, when the impurity concentration of the source region is increased, depletion of the surface of the source region can be reduced, and voltage drop on the surface of the source region can be reduced.
The amount of tunnel current can be increased. Also, when the junction depth of the source region is increased, the diffusion amount of the source region toward the channel formation region increases, the overlapping area between the source region and the information storage gate electrode increases, and the tunnel area increases. The amount of tunnel current can be increased. However, since the source region and the drain region are formed in the same manufacturing process, the impurity concentration of the drain region is high and the junction depth is deep. That is, since the overlapping area between the drain region and the information storage gate electrode increases, the coupling capacitance increases. For this reason, in the information writing operation, the potential of the information storage gate electrode rises due to the coupling capacitance in the unselected memory cell in which the control gate electrode is grounded and the drain electrode is set to the high potential, and the memory element becomes conductive. As a result, a leak current flows, and the information writing characteristics of the selected memory element deteriorate.

(2) When the impurity concentration in the drain region increases, the electric field intensity near the drain region increases. For this reason, in the information writing operation, the non-selected nonvolatile memory element in which writing has already been performed and only the drain electrode is set to the high potential generates a hot hole and is erased, so that the electrical reliability is reduced. Further, when the impurity concentration of the drain region is high and the junction depth is deep,
In the information writing operation, writing is already performed, and a non-selected nonvolatile memory element in which only the drain electrode is set to a high potential easily tunnels between the information storage gate electrode and the drain region. Electrical reliability decreases.

(3) When the impurity concentration of the drain is high and the junction depth is deep, the parasitic capacitance added to the data line increases. For this reason, the information reading operation speed is reduced, so that the operation speed cannot be increased.

(4) In order to solve the above-mentioned problem (1), the channel length is increased and the coupling capacitance formed between the drain region and the information storage gate electrode is made relatively small. It is possible to do. However, an increase in the channel length increases the area occupied by the nonvolatile memory element, and thus cannot achieve high integration.

It is an object of the present invention to provide a technique capable of improving information erasing efficiency and information writing characteristics in a semiconductor integrated circuit device having a nonvolatile memory circuit.

Another object of the present invention is to provide a technique capable of improving electrical reliability in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of increasing the operation speed of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of achieving high integration in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of reducing the number of manufacturing steps of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a semiconductor integrated circuit device provided with a nonvolatile memory circuit composed of a flash type nonvolatile memory element, the impurity concentration or the junction depth of a source region of a field effect transistor of the flash type nonvolatile memory element is increased. The field effect transistor has a low impurity concentration in the drain region or a shallow junction depth.

According to the above-described means, (1) the depletion of the surface of the source region in the information erasing operation is reduced by increasing the impurity concentration of the source region of the field effect transistor of the nonvolatile memory element;
Since the voltage drop on the surface of the source region can be reduced, the amount of tunnel current can be increased and the information erasing efficiency can be improved.

(2) Since the junction depth of the source region is increased, the amount of diffusion of the source region toward the channel forming region is increased, and the overlapping area between the source region and the information storage gate electrode is increased. As a result, the tunnel area can be increased, so that the tunnel current amount can be increased and the information erasing efficiency can be improved.

(3) Since the impurity concentration in the drain region is reduced, the electric field intensity in the vicinity of the drain region can be reduced, and the generation of hot holes can be reduced. Since the information in the non-selected nonvolatile memory element in the non-selected state can be prevented from being erased, electrical reliability can be improved.
Further, since the surface is easily depleted by lowering the impurity concentration of the drain region, the amount of tunnel current can be reduced, and erasure of information of the already written memory element can be prevented.

(4) Since the junction depth of the drain region is reduced, the amount of diffusion of the drain region toward the channel formation region is reduced, and the overlapping area between the drain region and the information storage gate electrode is reduced. As a result, the coupling capacitance between the drain region and the information storage gate electrode can be reduced, so that the conduction phenomenon of the non-selected memory cells during the information writing operation is prevented, and the leakage current is prevented to prevent the information writing. Characteristics can be improved.

(5) Also, by lowering the impurity concentration of the drain region and reducing the junction depth, the parasitic capacitance added to the data line can be reduced and the information reading operation speed can be increased. The operation speed can be increased.

(6) Since the channel length of the nonvolatile memory element can be reduced by reducing the coupling capacitance of the above (4), the cell area can be reduced.
High integration can be achieved.

An embodiment of the present invention applied to a semiconductor integrated circuit device having an EEPROM constituted by flash nonvolatile memory elements will be described below.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS EE which is one embodiment of the present invention
The structure of the PROM is shown in FIG. FIG.
The flash-type nonvolatile memory element is shown on the left side of the figure, and the peripheral circuit elements are shown on the right side of the figure.

As shown in FIG. 1, the EEPROM comprises a p-type semiconductor substrate 1 made of single crystal silicon. Flash nonvolatile memory element Qm and n-channel MI
In the formation region of the SFET Qn, a p-type well region 3 is provided on the main surface of the semiconductor substrate 1. In the formation region of the p-channel MISFET Qp, an n-type well region 2 is provided on the main surface of the semiconductor substrate 1.

An element isolation insulating film 4 is provided on the main surfaces of the n-type well region 2 and the p-type well region 3 between the element formation regions. On the main surface of the p-type well region 3, a p-type channel stopper region 5 is provided below the element isolation insulating film 4.

The flash type nonvolatile memory element Qm is
It is formed on the main surface of the p-type well region 3 in a region defined by the element isolation insulating film 4 and the channel stopper region 5. That is, the flash nonvolatile memory element Qm includes the p-type well region 3, the gate insulating film 6, the information storage gate electrode (floating gate electrode) 7,
It comprises a gate insulating film 8, a control gate electrode (control gate electrode) 9, a source region and a drain region. This flash type nonvolatile memory element Qm has n
It is composed of a channel field-effect transistor and is of a one-element type.

The p-type well region 3 is used as a channel forming region.

Gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the surface of p-type well region 3. The gate insulating film 6 is formed with a thickness of, for example, about 100 to 150 [Å].

The information storage gate electrode 7 is formed of, for example, a polycrystalline silicon film into which an n-type impurity has been introduced.

The gate insulating film 8 is formed of, for example, a silicon oxide film obtained by oxidizing the surface of the information storage gate electrode 7 (polycrystalline silicon film). The gate insulating film 8 is, for example, 200 to 25.
It is formed with a thickness of about 0 [Å].

The control gate electrode 9 is formed of, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. Further, the control gate electrode 9 may be formed of a single layer of a high melting point metal film or a high melting point metal silicide film, or a composite film in which the metal films are stacked on a polycrystalline silicon film. The control gate electrode 9 is integrally formed with the control gate electrode 9 of another flash type nonvolatile memory element Qm arranged adjacently in the gate width direction to form a word line (WL). .

The source region includes an n + -type semiconductor region 11 having a high impurity concentration and an n-type semiconductor region 12 having a low impurity concentration. The n-type semiconductor region 12 is the n + -type semiconductor region 1
1 is provided along the outer periphery. That is, the source region has a so-called double diffusion structure. The n + -type semiconductor region 11 having a high impurity concentration is mainly configured to increase the impurity concentration and increase the junction depth. The n-type semiconductor region 12 having a low impurity concentration is mainly configured to increase the junction depth. That is, when a high voltage is applied between the source region and the control gate electrode 9 during the information erasing operation, the impurity concentration is increased in the n + -type semiconductor region 11 so that the surface is not depleted. The source region increases the amount of diffusion (diffusion distance) to the channel formation region side by the high impurity concentration n + -type semiconductor region 11 or the low impurity concentration n-type semiconductor region 12 or both, and the information storage gate. The overlapping area with the electrode 7 (the amount of overlap) is increased, and the tunnel area during the information erasing operation is increased. Each of the semiconductor regions 11 and 12 is formed in self-alignment with the gate electrodes 7 and 9.

The drain region comprises a low impurity concentration n-type semiconductor region 14 and a high impurity concentration n + type semiconductor region 17.
It is composed of The low impurity concentration n-type semiconductor region 14 of the drain region is configured to control particularly the information writing characteristics of the flash nonvolatile memory element Qm. That is, the low impurity concentration n-type semiconductor region 1
Numeral 4 has a low impurity concentration and a shallower junction depth than the n + -type semiconductor region 11 having a high impurity concentration in the source region, but has a concentration sufficient to generate hot electrons during a write operation. It is composed. That is, the drain region mainly reduces the electric field intensity near the drain region in the non-selected memory element while maintaining the generation of hot electrons in the n-type semiconductor region 14 having a low impurity concentration in the selected memory element during the write operation, The configuration is such that generation of hot holes in the flash nonvolatile memory element can be reduced. In the drain region, the diffusion amount to the channel formation region side is reduced mainly by the n-type semiconductor region 14 having a small junction depth, the overlapping area with the information storage gate electrode 7 is reduced, and the drain region and the information storage The configuration is such that the coupling capacitance formed between the gate electrode 7 and the gate electrode 7 can be reduced. N-type semiconductor region 14 is formed in self-alignment with gate electrodes 7 and 9. The n + type semiconductor region 17 is formed in self alignment with the side wall spacer 16 formed in self alignment with the gate electrodes 7 and 9.

A high impurity concentration p + -type semiconductor region 13 is provided on the main surface of the semiconductor substrate 1 along the outer periphery of the drain region.
Is provided. The p + -type semiconductor region 13 enhances the electric field strength near the drain region, and in particular, promotes the generation of hot electrons in the flash nonvolatile memory element Qm in the selected state during the information writing operation, so that the information writing efficiency can be improved. It is configured.

This flash type nonvolatile memory element Qm
The wiring (data line DL) 21 is connected to the n + -type semiconductor region 17 which is the drain region of. The wiring 21
It extends over the interlayer insulating film 19 and is connected to the n + -type semiconductor region 17 through a connection hole 20 formed in the interlayer insulating film 19. The wiring 21 is formed of, for example, an aluminum alloy film.

The flash type nonvolatile memory element Qm
Examples of operating voltages used in each of the information writing operation, the information reading operation, and the information erasing operation are shown in Table 1 at the end of the specification.

Peripheral circuit elements such as a decoder circuit are composed of, but not limited to, complementary MISFETs (CMOS). N-channel MISFET Q
n is an element isolation insulating film 4 and a channel stopper region 5
The periphery of the p-type well region 3 is defined. That is, the n-channel MISFET Qn includes a p-type well region 3, a gate insulating film 8, a gate electrode 9, and a pair of n-type semiconductor regions 14 serving as a source region and a drain region.
And an n + type semiconductor region 17. The n-channel MISFET Qn has an LDD structure. The n + type semiconductor region 17 of the n channel MISFET Qn
Is connected to a wiring 21.

Of CMOS, p-channel MISFET
Qp has its periphery defined by the element isolation insulating film 4 and is formed on the main surface of the n-type well region 2. That is, the p-channel MISFET Qp includes the n-type well region 2, the gate insulating film 8, the gate electrode 9, and a pair of the p-type semiconductor region 15 and the p + -type semiconductor region 18 that are the source and drain regions
It is composed of p channel MISFET Qp is LD
It has a D structure. This p-channel MISFET
The wiring 21 is connected to the p + type semiconductor region 18 of Qp.

Next, the method of manufacturing the EEPROM will be described with reference to FIGS.
This will be briefly described with reference to FIG.

First, a p- type semiconductor substrate 1 is prepared.

Next, in the formation region of the p-channel MISFET Qp, an n-type well region 2 is formed on the main surface of the semiconductor substrate 1. The p-type well region 3 is, for example, 2 × 10
It is formed with an impurity concentration of about ^{16 to} 3 × 10 ¹⁶ [atoms / cm ³ ]. Thereafter, in each of the formation regions of the flash nonvolatile memory element Qm and the n-channel MISFET Qn, the p-type well region 3 is formed on the main surface of the semiconductor substrate 1.

Next, an element isolation insulating film 4 is formed on each of the main surfaces of the n-type well region 2 and the p-type well region 3, and a p-type channel stopper region 5 is formed on the main surface of the p-type well region 3. To form

Next, as shown in FIG. 2, a gate insulating film 6 is formed on each of the main surfaces of the n-type well region 2 and the p-type well region 3 in the semiconductor element formation region.

Next, a conductive film 7A is formed on the entire surface of the substrate including the gate insulating film 6. The conductive film 7A is formed of, for example, a polycrystalline silicon film deposited by a CVD method. An n-type impurity such as P is introduced into the polycrystalline silicon film to reduce the resistance. Thereafter, as shown in FIG. 3, the conductive film 7A is patterned into a predetermined shape. The conductive film 7A remains only in the formation region of the flash nonvolatile memory element Qm, and the size of the conductive film 7A in the channel width direction is defined.

Next, the flash type nonvolatile memory element Q
In the formation region of m, the gate insulating film 8 is formed on the surface of the conductive film 7A. The p-type well region 3 in the formation region of the n-channel MISFET Qn and n in the formation region of the p-channel MISFET Qp
A gate insulating film 8 is formed on each main surface of the mold well region 2. Thereafter, as shown in FIG. 4, a conductive film 9A is formed on the entire surface of the substrate including the gate insulating film 8. The conductive film 9A is formed of, for example, a polycrystalline silicon film deposited by a CVD method. An n-type impurity such as P is introduced into the polycrystalline silicon film to reduce the resistance.

Next, the flash nonvolatile memory element Q
In the formation region of m, each of the conductive films 9A and 7A is sequentially patterned to form the control gate electrode 9 and the information storage gate electrode 7. This patterning is RIE
This is performed by a so-called overlap cutting technique using anisotropic etching. Thereafter, patterning is performed on the conductive film 9A in the formation region of the peripheral circuit element to form the gate electrode 9. Thereafter, an oxidation process is performed on the entire surface of the substrate to form an insulating film 10 that covers the respective surfaces of the gate electrodes 7 and 9 as shown in FIG. The insulating film 10 is formed mainly to improve the retention characteristics of the information stored in the information storage gate electrode 7 of the flash nonvolatile memory element Qm.

Next, the flash type nonvolatile memory element Q
An impurity introduction mask 30 having an opening in a region where a source region of m is formed is formed. The impurity introduction mask 30 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 6, each of the n-type impurities 12n and 11n is sequentially introduced into the main surface portion of the p-type well region 3 serving as a source region formation region using the impurity introduction mask 30. The order of introducing the n-type impurities 12n and 11n may be reversed. The n-type impurity 12n is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ [atoms /
cm ² ] and 50 [Ke].
[V].
The n-type impurity 11n is, for example, 5 × 10 ¹⁵ to 1 × 10
It is introduced by ion implantation at an energy of about 60 [KeV] using As ions having an impurity concentration of about ¹⁶ [atoms / cm ² ]. The n-type impurities 11n and 12n are introduced using the same impurity introduction mask 30, and are introduced in a self-aligned manner with respect to the information storage gate electrode 7 and the control gate electrode 9. Then, the impurity introduction mask 30
Is removed.

Next, the flash type nonvolatile memory element Q
An impurity introduction mask 31 having an opening in the region where the m drain region is formed is formed. The impurity introduction mask 31 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 7, a p-type impurity 13p is introduced into the main surface portion of the p-type well region 3 serving as a drain region formation region using the impurity introduction mask 31. The p-type impurity 13p is, for example, 5
BF ₂ ions having an impurity concentration of about × 10 ^{13 to} 1.5 × 10 ¹⁴ [atoms / cm ² ] are introduced by ion implantation at an energy of about 60 [KeV]. p-type impurity 13p
Are introduced in a self-aligned manner with respect to the information storage gate electrode 7 and the control gate electrode 9. Then, the impurity introduction mask 31 is removed.

Next, in a nitrogen gas atmosphere, about 1000
[° C.], and the introduced n-type impurity 11 is removed.
Each of the n, 12n and p-type impurities 13p is stretched and diffused. By diffusion of the n-type impurity 12n, the n-type semiconductor region 12 can be formed. n-type semiconductor region 1
2 is formed with a deep junction depth of about 0.5 [μm]. By diffusion of the n-type impurity 11n, the n + -type semiconductor region 11 having a high impurity concentration can be formed. The n + type semiconductor region 11 is formed with a deep junction depth of about 0.3 [μm]. By the diffusion of the p-type impurity 13p, the p + -type semiconductor region 13 having a high impurity concentration can be formed. The p + type semiconductor region 13 has a thickness of about 0.3 to 0.5 [μm].
It is formed with a deep junction depth.

Next, the flash type nonvolatile memory element Q
An impurity introduction mask 32 having an opening in a region where m is formed is formed. The impurity introduction mask 32 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 8, the p + -type semiconductor region 1 is mainly formed using the impurity introduction mask 32.
An n-type impurity 14n is introduced into the main surface portion of No. 3. The n-type impurity 14n is, for example, 5 × 10 ^{14 to} 3 × 10 ¹⁵ [atoms / c
m ² ], and 60 [Ke
[V].
The n-type impurity 14n is introduced into the information storage gate electrode 7 and the control gate electrode 9 in a self-aligned manner. The n-type semiconductor region 14 formed by the n-type impurities 14n has a thickness of about 0.3.
It is formed with a shallow junction depth of about 1 to 0.2 [μm].
After the introduction of the n-type impurity 14n, the impurity introduction mask 32 is removed.

Next, an impurity introduction mask having an opening in the formation region of the n-channel MISFET Qn is formed. Then, using this impurity introduction mask, an n-type impurity is introduced into the main surface of the p-type well region 3 to form an n-type semiconductor region 14 having a low impurity concentration for forming an LDD structure. The n-type impurity is, for example, P ions having a low impurity concentration of about 10 ¹³ [atoms / cm ² ] and is introduced by ion implantation at an energy of about 50 [KeV]. The n
The type semiconductor region 14 is formed by self-alignment with the gate electrode 9. Thereafter, the impurity introduction mask is removed.

Next, an impurity introduction mask having an opening in the formation region of the p-channel MISFET Qp is formed. Then, using the impurity introduction mask, a p-type impurity is introduced into the main surface of the n-type well region 2 to form a p-type semiconductor region 15 having a low impurity concentration for forming an LDD structure. As the p-type impurity, for example, BF ₂ ions having a low impurity concentration of about 10 ¹³ [atoms / cm ² ] are used, and
[V].
The p-type semiconductor region 15 is formed in self-alignment with the gate electrode 9. Thereafter, as shown in FIG. 9, the impurity introduction mask is removed.

Next, a sidewall spacer 16 is formed on each side wall of each of the gate electrodes 7 and 9. The sidewall spacers 16 can be formed, for example, by depositing a silicon oxide film on the entire surface of the substrate by a CVD method, and performing anisotropic etching such as RIE on the entire surface of the substrate corresponding to the deposited film thickness.

Next, since the main surfaces of the n-type well region 2, the p-type well region 3 and the like are exposed by the anisotropic etching, oxidation treatment is performed, and the surfaces are covered with a thin silicon oxide film.

Next, the flash type nonvolatile memory element Q
An impurity introduction mask is formed in which the respective formation regions of the m and n channel MISFETs Qn are opened. Then, using this impurity introduction mask, an n-type impurity is introduced into the main surface of each region to form an n + -type semiconductor region 17 having a high impurity concentration. The n-type impurity is, for example, 5 × 10 ¹⁵ [atom
s / cm ² ], using As ions having a low impurity concentration of about 60
It is introduced by an ion implantation method with energy of about [KeV]. The n + type semiconductor region 17 is formed with a junction depth of about 0.2 [μm]. The n + type semiconductor region 17 is formed in a self-aligned manner with respect to each of the gate electrodes 7 and 9.
Thereafter, the impurity introduction mask is removed. This n
By the process of forming the + type semiconductor region 17, the field effect transistor and the n-channel MISFET Qn, which are the flash type nonvolatile memory elements Qm, are completed.

Next, an impurity introduction mask having an opening in the formation region of the p-channel MISFET Qp is formed. Then, using this impurity introduction mask, a p-type impurity is introduced into the main surface of the p-type semiconductor region 15 to form a p-type impurity having a high impurity concentration.
A + type semiconductor region 18 is formed. The p-type impurity is, for example, B having a high impurity concentration of about 2 × 10 ¹⁵ [atoms / cm ² ].
It is introduced by an ion implantation method using F ₂ ions at an energy of about 60 [KeV]. The p + type semiconductor region 1
8 is formed in self-alignment with the gate electrode 9.
Thereafter, as shown in FIG. 10, the impurity introduction mask is removed. By forming the p + type semiconductor region 18, the p-channel MISFET Qp is completed.

Next, an interlayer insulating film 19 is formed on the entire surface of the substrate. The interlayer insulating film 19 is made of, for example, BPS deposited by CVD.
It is formed with a G film. Then, a connection hole 20 is formed in the interlayer insulating film 19, a glass flow is applied to the interlayer insulating film 19, and then a wiring 21 is formed as shown in FIG. By performing these series of manufacturing steps, the EEPR of the present embodiment is obtained.
OM is completed. Although not shown, a passivation film is provided above the wiring 21.

As described above, in the semiconductor integrated circuit device provided with the EEPROM constituted by the flash type nonvolatile memory element Qm, the source region (the n + type semiconductor region 11) of the field effect transistor of the flash type nonvolatile memory element Qm is provided. ) Is configured to have a high impurity concentration, and the drain region (n-type semiconductor region 14) is configured to have a low impurity concentration. According to this configuration, (1) the depletion of the surface of the source region in the information erasing operation can be reduced and the voltage drop on the surface of the source region can be reduced, so that the tunnel current amount is increased and the information erasing efficiency is improved. And (2) relaxing the electric field strength near the drain region,
Since the generation of hot holes and the amount of tunnel current can be reduced, it is possible to prevent the information of the flash type nonvolatile memory element Qm in the non-selected state from being erased at the time of the information writing operation. Performance can be improved.

Further, the junction depth of the source region (n + type semiconductor region 11) of the field effect transistor of the flash type nonvolatile memory element Qm is made large, and the junction depth of the drain region (n type semiconductor region 14) is formed. Shallow. With this configuration, (3) the tunnel area can be increased by increasing the diffusion amount of the source region toward the channel formation region and increasing the overlapping area between the source region and the information storage gate electrode 7. The amount of tunnel current can be increased to improve the information erasing efficiency, and (4) the amount of diffusion of the drain region toward the channel formation region can be reduced, so that the overlapping area between the drain region and the information storage gate electrode 7 And the coupling capacitance between the drain region and the information storage gate electrode 7 can be reduced, so that the conduction phenomenon of the non-selected memory cell during the information writing operation can be prevented, and the leakage current can be prevented. Information writing characteristics can be improved.

Further, the drain region (n-type semiconductor region 14) of the flash type nonvolatile memory element Qm is configured to have a low impurity concentration and a small junction depth, thereby being added to the data line DL (wiring 21). Since the parasitic capacitance can be reduced and the information reading operation speed can be increased,
The operation speed can be increased.

The channel length of the flash nonvolatile memory element Qm is reduced by reducing the coupling capacitance formed between the drain region and the information storage gate electrode 7 of the flash nonvolatile memory element Qm. Therefore, the memory cell area can be reduced and high integration can be achieved.

The resistance value of the source region and the source line can be reduced by increasing the impurity concentration of the source region of the flash type nonvolatile memory element Qm or reducing the junction depth. And a stable information writing operation, an information reading operation, and an information erasing operation can be performed.

The source region of the flash type nonvolatile memory element Qm includes an n-type impurity 11n forming a high impurity concentration n + type semiconductor region 11 and a low impurity concentration n
Since each of the n-type impurities 12n forming the type semiconductor region 12 is introduced by using the same impurity introduction mask 30, the EEP corresponds to the step of introducing one impurity.
The number of manufacturing steps of the ROM can be reduced.

The method of manufacturing the EEPROM is not limited to the above-described manufacturing method, but can be formed by another manufacturing method described below.

<Manufacturing Method 1> First, after the step shown in FIG. 5, an n-type impurity 12n is introduced into the formation region of the source region of the flash nonvolatile memory element Qm.

Next, the flash type nonvolatile memory element Q
The p-type impurity 13p and n
A type impurity 14n is introduced.

Next, the introduced impurity is stretched and diffused to remove the low impurity concentration n-type semiconductor region 12, the high impurity concentration p + type semiconductor region 13, and the low impurity concentration n-type semiconductor region 14 respectively. Form.

Next, the flash nonvolatile memory element Q
An n-type impurity 11n is introduced into the formation region of the m source region, and the n-type impurity 11n is stretched and diffused to form n-type impurity 11n.
The + type semiconductor region 11 is formed.

Thereafter, the steps shown in FIG. 9 and the subsequent steps are performed to complete the EEPROM.

<Manufacturing Method 2> First, after the step shown in FIG. 5, an n-type impurity 12n is introduced into the formation region of the source region of the flash nonvolatile memory element Qm.

Next, the flash type nonvolatile memory element Q
A p-type impurity 13p is introduced into the formation region of the m drain region.

Next, the introduced impurities are stretched and diffused to form an n-type semiconductor region 12 having a low impurity concentration and a p + -type semiconductor region 13 having a high impurity concentration, respectively.

Next, the flash type nonvolatile memory element Q
The n-type impurity 14 is introduced into the formation region of the m drain region, and the n-type impurity 14 is extended and diffused to form the n-type semiconductor region 14 having a low impurity concentration.

Next, the flash type nonvolatile memory element Q
An n-type impurity 11n is introduced into the formation region of the m source region, and the n-type impurity 11n is stretched and diffused to form n-type impurity 11n.
The + type semiconductor region 11 is formed.

Thereafter, the steps shown in FIG. 9 and the subsequent steps are performed to complete the EEPROM.

<Manufacturing Method 3> First, after the step shown in FIG. 5, an n-type impurity 12n is introduced into the formation region of the source region of the flash nonvolatile memory element Qm.

Next, the flash type nonvolatile memory element Q
An n-type impurity 14n is introduced into the formation region of the m drain region.

Next, the flash type nonvolatile memory element Q
An n-type impurity 11n is introduced into the formation region of the m source region.

Next, the introduced impurities are stretched and diffused to remove the low impurity concentration n-type semiconductor region 12, the high impurity concentration n + -type semiconductor region 11, and the low impurity concentration n-type semiconductor region 14 respectively. Form.

Next, the flash type nonvolatile memory element Q
A p-type impurity 13p is introduced into the formation region of the drain region of m, and the p-type impurity 13p is stretched and diffused to form a p + -type semiconductor region 13 having a high impurity concentration.

Thereafter, the steps shown in FIG. 9 and subsequent steps are performed to complete the EEPROM.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

The flash nonvolatile memory element of the EEPROM according to the present invention comprises a field effect transistor having an information storage gate electrode and a control gate electrode.

[0088]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a nonvolatile memory circuit, information erasing efficiency and information writing characteristics can be improved.

Further, the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, the operation speed of the semiconductor integrated circuit device can be increased.

Further, high integration of the semiconductor integrated circuit device can be achieved.

[0093]

[Table 1]

[Brief description of the drawings]

FIG. 1 is a sectional view showing a main part of a configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 3 is a sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 4 is a sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 5 is a cross-sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 6 is a cross-sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 7 is a cross-sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 8 is a cross-sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 9 is a cross-sectional view of a main part of the EEPROM shown in each manufacturing process.

FIG. 10 is a cross-sectional view of a main part of the EEPROM shown in each manufacturing process.

[Explanation of symbols]

2,3 ... well region, 6,8 ... gate insulating film, 7,9 ...
Gate electrode, 11, 12, 13, 14, 15, 17, 1
8 ... semiconductor region, 11n, 12n, 13p, 114n ...
Impurity, Qm: Flash type nonvolatile memory element, Q
n, Qp... MISFET.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hitoshi Kume 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside Hitachi, Ltd. Central Research Laboratory (72) Inventor Yoshiaki Kamigaki 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Hitachi, Ltd. (56) References JP-A-2-372 (JP, A) JP-A-2-129968 (JP, A) JP-A-2-128477 (JP, A) JP-A-62-276878 (JP, A) A) JP-A-62-71277 (JP, A) JP-A-61-127179 (JP, A) JP-A-61-123186 (JP, A) JP-A-60-207385 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (13)

(57) [Claims] A semiconductor substrate having a main surface; a first semiconductor region and a second semiconductor region formed in the semiconductor substrate; and a first semiconductor region and a second semiconductor region in the semiconductor substrate .
A channel forming region formed between the semiconductor region, a first gate insulating film formed over the channel forming region, a floating gate electrode formed over the first gate insulating film; a second gate insulating film formed over the gate electrode, have a memory cell composed of an upper the formed control gate electrode of the second gate insulating film, injecting hot carriers into the floating gate electrode
Alternatively, a semiconductor memory device that records or erases information by discharging the injected hot carriers from the floating gate electrode to the first semiconductor region by tunneling through the first gate insulating film is manufactured.
A first gate insulating film on a main surface of the semiconductor substrate;
Floating gate electrode, second gate insulating film, controller
Forming by sequentially laminating roll gate electrode, itself to one end of the control gate electrode
A first semiconductor is added to the semiconductor substrate by introducing impurities in a consistent manner;
A first introduction step for forming a region, and at least one other end of the control gate electrode
To the semiconductor substrate by introducing impurities in a self-aligned manner.
A second introduction step of forming a second semiconductor region, wherein the first semiconductor region has the same conductivity as the second semiconductor region.
And the impurity concentration of the first semiconductor region is the same as that of the second semiconductor region.
Wherein the impurity concentration is higher than the impurity concentration in the region . 2. A first step of introducing the impurity, claims, characterized in that is introduced using a mask film covering a top of said second semiconductor forming region as a mask
2. The method for manufacturing a semiconductor memory device according to item 1 . Wherein the impurity had contact with the first introduction step and the second introduction <br/> step is arsenic, the first semiconductor region
3. The method according to claim 1 , wherein the impurity concentration of the second semiconductor region is higher than the impurity concentration of the second semiconductor region. 4. 4. introducing a self-aligned manner with impurities relative to one end of the control gate electrode, the third introduction for forming the deep third semiconductor region than the first semiconductor region in a semiconductor substrate includes the step, the impurity in the third step of introducing is phosphorus, the impurity concentration of phosphorus in the third introduction step, the first than the impurity concentration of arsenic definitive in the semiconductor area low rot
The method of manufacturing a semiconductor memory device according to claim 3, characterized in that that. 5. introducing a self-aligned manner with impurities relative to one end of the control gate electrode, the semiconductor <br/> board, at least a portion of the second semiconductor region side of the channel forming region A fourth introduction step of forming a fourth semiconductor region in the fourth semiconductor region, wherein the fourth semiconductor region has a conductivity type opposite to a conductivity type of the first semiconductor region; the impurity concentration of the manufacturing method of the semiconductor memory device according to claim 4, wherein the molder higher than the impurity concentration of the semiconductor substrate. 6. the amount of overlap between the floating gate electrode and the first semiconductor region, said floating gate
6. The method of manufacturing a semiconductor memory device according to claim 1 , wherein an amount of overlap between the gate electrode and the second semiconductor region is larger. 7. A junction depth of the first semiconductor region, the semiconductor memory device according to any one of claims 1 to 6, characterized in that deeper than the junction depth of the second semiconductor region Manufacturing method. 8. A semiconductor substrate having a main surface, a first semiconductor region and a second semiconductor region formed in the semiconductor substrate, and the first semiconductor region and the second semiconductor region in the semiconductor substrate .
A channel forming region formed between the semiconductor region, a first gate insulating film formed over the channel forming region, a floating gate electrode formed over the first gate insulating film; A memory cell including a second gate insulating film formed over the gate electrode, a control gate electrode formed over the second gate insulating film, and MISFE forming a peripheral circuit
Possess a T, injecting hot carriers into the floating gate electrode
Alternatively, the injected hot carrier is flowed
Through the first gate insulating film from the first gate insulating film
Releasing to the first semiconductor region by tunneling;
And a method for recording or erasing information in the semiconductor memory device, wherein a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are sequentially stacked on the main surface of the semiconductor substrate. And in the peripheral circuit formation region of the main surface, the MISF
Forming a gate insulating film of ET and a gate electrode of the MISFET on the gate insulating film; and introducing an impurity in the memory cell forming region in a self-aligned manner with respect to one end of the control gate electrode. the forming the first semiconductor region in the semiconductor substrate and
1 of the introduction step, in the memory cell forming region, the control gate electrode and the second forming a second semiconductor region by introducing a self-aligning manner impurities in said semiconductor substrate at least to the other end Introducing the MISFE in the peripheral circuit forming region on the main surface.
A fifth introduction step of introducing an impurity in a self-alignment manner with respect to one end of the T gate electrode to form a fifth semiconductor region in the semiconductor substrate ; after the introduction step, in the memory cell formation region of the main surface, forming a first sidewall spacer in a self-aligned manner with respect to the side walls of the control gate electrode and floating gate electrode, and,
Forming a second sidewall spacer in the peripheral circuit formation region in a self-aligned manner with respect to the side wall of the gate electrode of the MISFET; Forming a sixth semiconductor region in the semiconductor substrate by introducing impurities in a self-aligned manner .
And a step of introducing said first, a second, fifth and sixth semiconductor regions are the same conductivity type, the impurity concentration of definitive to the first semiconductor area, from the impurity concentration definitive in the second semiconductor area high is formed, the impurity concentration of definitive to the first semiconductor area, said fifth formed higher than definitive impurity concentration in the semiconductor area, said sixth impurity concentration definitive in the semiconductor area is in the fifth semiconductor area formed higher than definitive impurity concentration, the junction depth of the sixth semiconductor region, it said fifth deeper than the junction depth of the semiconductor region, said fifth semiconductor region, said sixth semiconductor region and the channel formation region of the MISFET is formed between the fifth and sixth semiconductor regions, a method of manufacturing a semiconductor memory device characterized by acting as a drain of the MISFET. Wherein said impurities have you to the first introduction step and the second introduction <br/> step is arsenic, the first semiconductor region
9. The method according to claim 8, wherein the impurity concentration of the second semiconductor region is higher than the impurity concentration of the second semiconductor region. 10. introducing a self-aligning manner impurities relative to one end of the control gate electrode, the third introduction for forming the deep third semiconductor region than the first semiconductor region in a semiconductor substrate includes the step, the impurity in the third step of introducing is phosphorus, the impurity concentration of phosphorus in the third introduction step, the first than the impurity concentration of arsenic definitive in the semiconductor area low rot
The method of manufacturing a semiconductor memory device according to claim 9, characterized in that that. 11. introducing a self-aligning manner impurities relative to one end of the control gate electrode, wherein the semiconductor base plate, the fourth semiconductor at least a second semiconductor region side portions of the channel forming region A fourth introduction step of forming a region, wherein the fourth semiconductor region has a conductivity type opposite to a conductivity type of the first semiconductor region, and an impurity concentration of the fourth semiconductor region is: claim 10, characterized in that spoil higher than the impurity concentration of said semiconductor substrate
6. The method for manufacturing a semiconductor memory device according to claim 1. 12. the amount of overlap between the floating gate electrode and the first semiconductor region, said floating gate
12. The semiconductor device according to claim 8 , wherein the overlap amount is larger than an overlap amount between the gate electrode and the second semiconductor region.
13. The method for manufacturing a semiconductor memory device according to item 13. 13. The semiconductor memory device according to claim 8 , wherein a junction depth of said first semiconductor region is deeper than a junction depth of said second semiconductor region. Manufacturing method.