JPH08213489A - Production of semiconductor storage device - Google Patents

Abstract

PURPOSE: To improve the information erasing efficiency and information writing characteristic by constituting a field effect transistor for flash type nonvolatile memory element in a manner that its source area is heavily doped and has a large joint depth and a drain area is lightly doped and has a small joint depth. CONSTITUTION: The heavily doped n<+> type semiconductor area 11 in a source area is constituted mainly as to increase the impurity concentration and make the joint depth large. The lightly doped n type semiconductor area 12 is constituted mainly as to make the joint depth large. In addition, the lightly doped n type semiconductor area 14 in a drain area is constituted as to be lightly doped and has a small joint depth in comparison with the heavily doped area 11 in the source area, however its concentration is set appropriately for producing hot electrons during writing operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a nonvolatile memory circuit.

[0002]

BACKGROUND ART nonvolatile storage circuit of the read electrical erasable private (E lectrically E rasable P rogrammable
R ead O nly M emory) nonvolatile memory device as a device type non-volatile memory device have been proposed. This non-volatile memory element is composed of a field effect transistor having an information storage gate electrode (floating gate electrode) and a control gate electrode (control gate electrode). The source region of the field effect transistor is connected to the source line, and the drain region is connected to the data line.

The non-volatile memory device is called a flash type non-volatile memory device, and is of a hot electron writing type and a tunnel erasing type. That is, the information writing operation of the nonvolatile memory element is
Hot electrons are generated in a high electric field near the drain region, and the hot electrons are injected into the information storage gate electrode. On the other hand, the information erasing operation of the nonvolatile memory element is performed by tunneling the electrons accumulated in the information storing gate electrode to the source region.

The EEPROM composed of this flash type non-volatile memory element has a feature that it can be made large in capacity because the cell area can be reduced by the one element type as described above.

For the above-mentioned EEPROM, 1
985 IDM Technical Digest pp. 468-471 (1985 IEDM Te
ch Dig. pp468-471).

[0006]

DISCLOSURE OF THE INVENTION The present inventor has proposed the above-mentioned E
As a result of examining the EPROM, it was found that the following problems occur.

(1) To improve the information erasing efficiency in the information erasing operation of the flash type nonvolatile memory element, it is necessary to increase the impurity concentration of the source region and make the junction depth deep. That is, when the impurity concentration of the source region is increased, depletion of the surface of the source region can be reduced and a voltage drop on the surface of the source region can be reduced.
The amount of tunnel current can be increased. Further, when the junction depth of the source region is increased, the diffusion amount of the source region toward the channel formation region side increases, the overlapping area of the source region and the information storage gate electrode increases, and the tunnel area increases, The amount of tunnel current can be increased. However, since the source region and the drain region are formed in the same manufacturing process, the drain region has a high impurity concentration and a deep junction depth. That is, the area of overlap between the drain region and the information storage gate electrode increases, so that the coupling capacitance increases. Therefore, in the information writing operation, in the unselected memory cell in which the control gate electrode is grounded and the drain electrode is set to the high potential, the potential of the information storage gate electrode rises due to the coupling capacitance, and the memory element becomes conductive. As a result, a leak current flows and the information writing characteristics of the selected memory element deteriorate.

(2) Further, when the impurity concentration in the drain region becomes high, the electric field strength near the drain region becomes high. Therefore, in the information writing operation, the non-volatile memory element in the non-selected state in which the writing is already performed and only the drain electrode is set to the high potential generates the hot hole and is erased, so that the electrical reliability is deteriorated. Further, if the impurity concentration of the drain region is high and the junction depth is deep,
In the information writing operation, since the non-selected non-volatile memory element in which the writing is already performed and only the drain electrode is set to the high potential easily tunnels between the information storage gate electrode and the drain region, erroneous erasing occurs, The electrical reliability is reduced.

(3) When the impurity concentration of the drain is high and the junction depth is deep, the parasitic capacitance added to the data line increases. As a result, the information read operation speed is reduced, and the operation speed cannot be increased.

(4) In order to solve the problem (1), the channel length is increased and the coupling capacitance formed between the drain region and the information storage gate electrode is made relatively small. It is possible to do it. However, since the increase in channel length increases the occupied area of the non-volatile memory element, high integration cannot be achieved.

An object of the present invention is to provide a technique capable of improving information erasing efficiency and information writing characteristics in a semiconductor integrated circuit device having a non-volatile memory circuit.

Another object of the present invention is to provide a technique capable of improving the electrical reliability of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of increasing the operating speed of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of achieving high integration in the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of reducing the number of manufacturing steps of the semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In a semiconductor integrated circuit device having a nonvolatile memory circuit composed of a flash type nonvolatile memory element, the impurity concentration of the source region of the field effect transistor of the flash type nonvolatile memory element is increased or the junction depth is increased. The drain region of the field effect transistor is made deep and the impurity concentration is made low or the junction depth is made shallow.

According to the above-mentioned means, (1) by increasing the impurity concentration of the source region of the field effect transistor of the nonvolatile memory element, the depletion of the surface of the source region in the information erasing operation is reduced,
Since the voltage drop on the surface of the source region can be reduced, the tunnel current amount can be increased and the information erasing efficiency can be improved.

(2) Further, by increasing the junction depth of the source region, the diffusion amount of the source region toward the channel formation region side is increased, and the overlapping area of the source region and the information storage gate electrode is increased. Therefore, the tunnel area can be increased, so that the tunnel current amount can be increased and the information erasing efficiency can be improved.

(3) Also, since the impurity concentration in the drain region is lowered, the electric field strength near the drain region can be relaxed and the generation of hot holes can be reduced. Since it is possible to prevent the information in the non-volatile memory element in the non-selected state from being erased, it is possible to improve the electrical reliability.
Further, since the surface of the drain region is easily depleted by lowering the impurity concentration of the drain region, the tunnel current amount can be reduced and the already written information of the memory element can be prevented from being erased.

(4) Further, by making the junction depth of the drain region shallow, the amount of diffusion of the drain region toward the channel formation region side is reduced, and the overlap area between the drain region and the information storage gate electrode is reduced. Since it is possible to reduce the coupling capacitance between the drain region and the information storage gate electrode, it is possible to prevent the conduction phenomenon of the memory cells in the non-selected state at the time of the information writing operation and prevent the leak current from writing the information. The characteristics can be improved.

(5) Further, by making the impurity concentration of the drain region low and making the junction depth shallow, the parasitic capacitance added to the data line can be reduced and the information read operation speed can be increased. The operating speed can be increased.

(6) Further, since the channel length of the non-volatile memory element can be reduced by reducing the coupling capacitance of (4), the cell area can be reduced.
High integration can be achieved.

With respect to the configuration of the present invention, an embodiment in which the present invention is applied to a semiconductor integrated circuit device having an EEPROM composed of a flash type nonvolatile memory element will be described below.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION EE which is an embodiment of the present invention
The structure of the PROM is shown in FIG. Figure 1
The flash type nonvolatile memory element is shown on the left side of the figure, and the peripheral circuit element is shown on the right side of the figure.

As shown in FIG. 1, the EEPROM is composed of a p--type semiconductor substrate 1 made of single crystal silicon. Flash type nonvolatile memory element Qm and n channel MI
A p-type well region 3 is provided in the main surface portion of the semiconductor substrate 1 in the formation region of the SFET Qn. An n-type well region 2 is provided in the main surface portion of the semiconductor substrate 1 in the formation region of the p-channel MISFET Qp.

An element isolation insulating film 4 is provided on the main surfaces of the n-type well region 2 and the p-type well region 3 between the element formation regions. A p-type channel stopper region 5 is provided under the element isolation insulating film 4 on the main surface of the p-type well region 3.

The flash type non-volatile memory device Qm is
It is formed on the main surface of the p-type well region 3 in a region defined by the element isolation insulating film 4 and the channel stopper region 5. That is, the flash type nonvolatile memory element Qm includes the p-type well region 3, the gate insulating film 6, the information storage gate electrode (floating gate electrode) 7,
It is composed of a gate insulating film 8, a control gate electrode (control gate electrode) 9, a source region and a drain region. This flash type nonvolatile memory element Qm has n
It is composed of a channel field effect transistor, and is composed of a single element type.

The p-type well region 3 is used as a channel forming region.

The gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the surface of the p-type well region 3. The gate insulating film 6 is formed with a film thickness of, for example, about 100 to 150 [Å].

The information storage gate electrode 7 is formed of, for example, a polycrystalline silicon film having an n-type impurity introduced therein.

The gate insulating film 8 is formed of, for example, a silicon oxide film obtained by oxidizing the surface of the information storage gate electrode 7 (polycrystalline silicon film). The gate insulating film 8 is, for example, 200 to 25
It is formed with a film thickness of about 0 [Å].

The control gate electrode 9 is formed of, for example, a polycrystalline silicon film doped with an n-type impurity. Further, the control gate electrode 9 may be formed of a single layer of a refractory metal film or a refractory metal silicide film, or a composite film in which those metal films are laminated on a polycrystalline silicon film. The control gate electrode 9 is integrally formed with the control gate electrode 9 of another flash type nonvolatile memory element Qm arranged adjacently in the gate width direction to form a word line (WL). .

The source region is composed of an n + type semiconductor region 11 having a high impurity concentration and an n type semiconductor region 12 having a low impurity concentration. The n-type semiconductor region 12 is the n + -type semiconductor region 1
It is provided along the outer periphery of 1. That is, the source region has a so-called double diffusion structure. The n + type semiconductor region 11 having a high impurity concentration is mainly configured to increase the impurity concentration and further increase the junction depth. The low impurity concentration n-type semiconductor region 12 is mainly configured to increase the junction depth. That is, in the source region, the impurity concentration is increased in the n + type semiconductor region 11 so that the surface is not depleted when a high voltage is applied between the source region and the control gate electrode 9. In the source region, the n + -type semiconductor region 11 having a high impurity concentration and / or the n-type semiconductor region 12 having a low impurity concentration increases the diffusion amount (diffusion distance) toward the channel formation region side, thereby increasing the information storage gate. The overlapping area (overlap amount) with the electrode 7 is increased to increase the tunnel area during the information erasing operation. Each of the semiconductor regions 11 and 12 is formed in self-alignment with the gate electrodes 7 and 9.

The drain region is a low impurity concentration n-type semiconductor region 14 and a high impurity concentration n + -type semiconductor region 17.
It is composed of The low-impurity-concentration n-type semiconductor region 14 in the drain region is configured to control especially the information writing characteristic of the flash type nonvolatile memory element Qm. That is, this low impurity concentration n-type semiconductor region 1
4 has a low impurity concentration and a shallow junction depth as compared with the n + type semiconductor region 11 having a high impurity concentration in the source region, but the concentration is such that hot electrons are sufficiently generated during the write operation. Is configured. That is, the drain region mainly relaxes the electric field strength in the vicinity of the drain region in the non-selected memory element while maintaining the generation of hot electrons in the n-type semiconductor region 14 having a low impurity concentration in the selected memory element during the write operation. It is configured to reduce the generation of hot holes in the flash nonvolatile memory element. In the drain region, the amount of diffusion toward the channel forming region side is reduced mainly in the n-type semiconductor region 14 having a shallow junction depth, the overlap area with the information storage gate electrode 7 is reduced, and the drain region and the information storage are formed. It is configured so that the coupling capacitance formed with the use gate electrode 7 can be reduced. The n-type semiconductor region 14 is formed in self-alignment with the gate electrodes 7 and 9. The n + type semiconductor region 17 is formed in self alignment with the sidewall spacer 16 formed in self alignment with the gate electrodes 7 and 9.

A high impurity concentration p + type semiconductor region 13 is formed on the main surface of the semiconductor substrate 1 along the outer periphery of the drain region.
Is provided. The p + type semiconductor region 13 enhances the electric field strength in the vicinity of the drain region, and in particular, promotes the generation of hot electrons in the flash type nonvolatile memory element Qm in the selected state during the information writing operation, thereby improving the information writing efficiency. It is configured.

This flash type nonvolatile memory element Qm
A wiring (data line DL) 21 is connected to the n + type semiconductor region 17 which is the drain region of the. The wiring 21 is
It extends on the interlayer insulating film 19 and is connected to the n + type semiconductor region 17 through a connection hole 20 formed in the interlayer insulating film 19. The wiring 21 is formed of, for example, an aluminum alloy film.

The flash type nonvolatile memory element Qm
Table 1 at the end of the specification shows the example operating voltages used in each of the information writing operation, the information reading operation, and the information erasing operation.

Peripheral circuit elements such as the decoder circuit are composed of, but not limited to, complementary MISFET (CMOS). N-channel MISFETQ of CMOS
n is an element isolation insulating film 4 and a channel stopper region 5
The periphery is defined by and is formed on the main surface of the p-type well region 3. That is, the n-channel MISFET Qn has the p-type well region 3, the gate insulating film 8, the gate electrode 9, and the pair of n-type semiconductor regions 14 which are the source region and the drain region.
And an n + type semiconductor region 17. The n-channel MISFET Qn has an LDD structure. The n + type semiconductor region 17 of this n channel MISFET Qn
The wiring 21 is connected to.

Of CMOS, p-channel MISFET
The periphery of Qp is defined by the element isolation insulating film 4, and is formed on the main surface of the n-type well region 2. That is, the p-channel MISFET Qp is composed of the n-type well region 2, the gate insulating film 8, the gate electrode 9, the pair of p-type semiconductor regions 15 and p + -type semiconductor regions 18 which are the source and drain regions.
It is composed of p channel MISFET Qp is LD
It has a D structure. This p-channel MISFET
A wiring 21 is connected to the p + type semiconductor region 18 of Qp.

Next, a method of manufacturing the EEPROM will be described with reference to FIGS. 2 to 10 (cross-sectional views of an essential part shown in each manufacturing process).
Will be briefly explained.

First, the p-type semiconductor substrate 1 is prepared.

Next, the n-type well region 2 is formed in the main surface portion of the semiconductor substrate 1 in the formation region of the p-channel MISFET Qp. The p-type well region 3 has, for example, 2 × 10
It is formed with an impurity concentration of about ^{16 to} 3 × 10 ¹⁶ [atoms / cm ³ ]. After that, the p-type well region 3 is formed in the main surface portion of the semiconductor substrate 1 in the formation regions of the flash nonvolatile memory element Qm and the n-channel MISFET Qn, respectively.

Next, the element isolation insulating film 4 is formed on the main surfaces of the n-type well region 2 and the p-type well region 3, and the p-type channel stopper region 5 is formed on the main surface of the p-type well region 3. To form.

Next, as shown in FIG. 2, a gate insulating film 6 is formed on each main surface of the n-type well region 2 and the p-type well region 3 in the semiconductor element forming region.

Next, a conductive film 7A is formed on the entire surface of the substrate including the gate insulating film 6. The conductive film 7A is formed of, for example, a polycrystalline silicon film deposited by the CVD method. An n-type impurity such as P is introduced into the polycrystalline silicon film to reduce the resistance. Then, as shown in FIG. 3, the conductive film 7A is patterned into a predetermined shape. The conductive film 7A remains only in the formation region of the flash type nonvolatile memory element Qm, and the conductive film 7A has a dimension in the channel width direction defined.

Next, the flash non-volatile memory device Q
In the formation region of m, the gate insulating film 8 is formed on the surface of the conductive film 7A. By the manufacturing process substantially the same as this process, the p-type well region 3 in the formation region of the n-channel MISFET Qn and the n-type region in the formation region of the p-channel MISFET Qp are formed.
A gate insulating film 8 is formed on each main surface of the mold well region 2. Thereafter, as shown in FIG. 4, a conductive film 9A is formed on the entire surface of the substrate including the gate insulating film 8. The conductive film 9A is formed of, for example, a polycrystalline silicon film deposited by the CVD method. An n-type impurity such as P is introduced into the polycrystalline silicon film to reduce the resistance.

Next, the flash type non-volatile memory device Q
In the formation region of m, the conductive films 9A and 7A are sequentially patterned to form the control gate electrode 9 and the information storage gate electrode 7. This patterning is RIE
This is performed by a so-called overlapping cutting technique using anisotropic etching such as. After that, the conductive film 9A in the formation region of the peripheral circuit element is patterned to form the gate electrode 9. After that, the entire surface of the substrate is subjected to an oxidation treatment to form an insulating film 10 covering the respective surfaces of the gate electrodes 7 and 9 as shown in FIG. The insulating film 10 is formed mainly for improving the retention characteristic of the information stored in the information storage gate electrode 7 of the flash nonvolatile memory element Qm.

Next, the flash type nonvolatile memory device Q
An impurity introduction mask 30 having an opening in the formation region of the source region of m is formed. The impurity introduction mask 30 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 6, using the impurity introducing mask 30, n-type impurities 12n and 11n are sequentially introduced into the main surface portion of the p-type well region 3 which is a source region forming region. The introduction order of the n-type impurities 12n and 11n may be reversed. The n-type impurity 12n is, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁵ [atoms /
cm ² ] with an impurity concentration of about 50 [Ke
V] is introduced by the ion implantation method.
The n-type impurity 11n is, for example, 5 × 10 ¹⁵ to 1 × 10 5.
It is introduced by an ion implantation method using As ions having an impurity concentration of about ¹⁶ [atoms / cm ² ] and an energy of about 60 [KeV]. The n-type impurities 11n and 12n are introduced using the same impurity introduction mask 30 and introduced in self-alignment with the information storage gate electrode 7 and the control gate electrode 9. Then, the impurity introduction mask 30
Is removed.

Next, the flash type nonvolatile memory device Q
An impurity introduction mask 31 having an opening in the formation region of the drain region of m is formed. The impurity introduction mask 31 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 7, the impurity introduction mask 31 is used to introduce the p-type impurity 13p into the main surface portion of the p-type well region 3 serving as the drain region formation region. The p-type impurity 13p is, for example, 5
It is introduced by an ion implantation method with an energy of about 60 [KeV] using BF ₂ ions having an impurity concentration of about × 10 ^{13 to} 1.5 × 10 ¹⁴ [atoms / cm ² ]. p-type impurity 13p
Are introduced in self-alignment with the information storage gate electrode 7 and the control gate electrode 9. Then, the impurity introducing mask 31 is removed.

Next, in a nitrogen gas atmosphere, about 1000
After the heat treatment at [° C.], the introduced n-type impurities 11
The n, 12n, and p-type impurities 13p are stretched and diffused. The diffusion of the n-type impurity 12n can form the n-type semiconductor region 12. n-type semiconductor region 1
2 is formed with a deep junction depth of about 0.5 [μm]. By diffusing the n-type impurity 11n, the n + -type semiconductor region 11 having a high impurity concentration can be formed. The n + type semiconductor region 11 is formed with a deep junction depth of about 0.3 [μm]. By diffusion of the p-type impurity 13p, the p + -type semiconductor region 13 having a high impurity concentration can be formed. The p + type semiconductor region 13 is about 0.3 to 0.5 [μm].
It is formed with a deep junction depth.

Next, a flash type non-volatile memory device Q
An impurity introduction mask 32 having an opening in the formation region of m is formed. The impurity introduction mask 32 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 8, the p + type semiconductor region 1 is mainly formed by using the impurity introducing mask 32.
An n-type impurity 14n is introduced into the main surface portion of No. 3. The n-type impurity 14n is, for example, 5 × 10 ^{14 to} 3 × 10 ¹⁵ [atoms / c
m ² ] and an As ion with an impurity concentration of about 60 [Ke
V] is introduced by the ion implantation method.
The n-type impurity 14n is introduced in self-alignment with the information storage gate electrode 7 and the control gate electrode 9. The n-type semiconductor region 14 formed of the n-type impurity 14n has a density of about 0.
It is formed with a shallow junction depth of about 1 to 0.2 [μm].
After the introduction of the n-type impurity 14n, the impurity introduction mask 32 is removed.

Next, an impurity introduction mask having an opening in the formation region of the n-channel MISFET Qn is formed. Then, using this impurity introduction mask, an n-type impurity is introduced into the main surface portion of the p-type well region 3 to form an n-type semiconductor region 14 having a low impurity concentration for forming an LDD structure. The n-type impurities are introduced by an ion implantation method with energy of about 50 [KeV] using P ions with a low impurity concentration of about 10 ¹³ [atoms / cm ² ], for example. N
The type semiconductor region 14 is formed in self-alignment with the gate electrode 9. After that, the impurity introduction mask is removed.

Next, an impurity introduction mask having an opening in the formation region of the p-channel MISFET Qp is formed. Then, using this impurity introduction mask, p-type impurities are introduced into the main surface portion of the n-type well region 2 to form a p-type semiconductor region 15 having a low impurity concentration for forming an LDD structure. As the p-type impurity, for example, BF ₂ ions having a low impurity concentration of about 10 ¹³ [atoms / cm ² ] are used, and 60 [Ke
V] is introduced by the ion implantation method.
The p-type semiconductor region 15 is formed in self-alignment with the gate electrode 9. After that, as shown in FIG. 9, the impurity introduction mask is removed.

Next, sidewall spacers 16 are formed on the respective sidewalls of the gate electrodes 7 and 9. The sidewall spacers 16 can be formed, for example, by depositing a silicon oxide film on the entire surface of the substrate by a CVD method and performing anisotropic etching such as RIE on the entire surface of the substrate by the amount corresponding to the deposited film thickness.

Next, since the principal surfaces of the n-type well region 2, the p-type well region 3 and the like are exposed by the anisotropic etching, an oxidation treatment is performed and the surfaces thereof are covered with a thin silicon oxide film.

Next, a flash type non-volatile memory device Q
An impurity introduction mask having openings in the formation regions of the m and n channel MISFETs Qn is formed. Then, using this impurity introduction mask, n-type impurities are introduced into the main surface portion of each region to form an n + -type semiconductor region 17 having a high impurity concentration. The n-type impurity is, for example, 5 × 10 ¹⁵ [atom
s / cm ² ] and using As ions with a low impurity concentration of about 60
It is introduced by the ion implantation method with an energy of about [KeV]. The n + type semiconductor region 17 is formed with a junction depth of about 0.2 [μm]. The n + type semiconductor region 17 is formed in self-alignment with each gate electrode 7 and 9.
After that, the impurity introduction mask is removed. This n
By the process of forming the + type semiconductor region 17, the field effect transistor and the n-channel MISFET Qn which are the flash type nonvolatile memory element Qm are completed.

Next, an impurity introduction mask having an opening in the formation region of the p-channel MISFET Qp is formed. Then, using this impurity introduction mask, p-type impurities are introduced into the main surface portion of the p-type semiconductor region 15, and p with a high impurity concentration is added.
A + type semiconductor region 18 is formed. The p-type impurity is B having a high impurity concentration of about 2 × 10 ¹⁵ [atoms / cm ² ], for example.
It is introduced by an ion implantation method using F ₂ ions and an energy of about 60 [KeV]. The p + type semiconductor region 1
8 is formed in self alignment with the gate electrode 9.
After that, as shown in FIG. 10, the impurity introduction mask is removed. By forming the p + type semiconductor region 18, the p channel MISFET Qp is completed.

Next, an interlayer insulating film 19 is formed on the entire surface of the substrate. The interlayer insulating film 19 is, for example, BPS deposited by the CVD method.
It is formed of a G film. Then, a connection hole 20 is formed in the interlayer insulating film 19, a glass flow is applied to the interlayer insulating film 19, and then a wiring 21 is formed as shown in FIG. By performing these series of manufacturing steps, the EEPR of this embodiment is
OM is completed. Although not shown, a passivation film is provided on the wiring 21.

As described above, in the semiconductor integrated circuit device provided with the EEPROM constituted by the flash type nonvolatile memory element Qm, the source region (n + type semiconductor region 11) of the field effect transistor of the flash type nonvolatile memory element Qm. 2) is configured to have a high impurity concentration, and the drain region (n-type semiconductor region 14) is configured to have a low impurity concentration. With this configuration, (1) the depletion of the surface of the source region in the information erasing operation can be reduced and the voltage drop on the surface of the source region can be reduced, so that the tunnel current amount is increased and the information erasing efficiency is improved. And (2) alleviating the electric field strength near the drain region,
Since the generation of hot holes and the amount of tunnel current can be reduced, it is possible to prevent the information in the non-selected flash type nonvolatile memory element Qm from being erased at the time of the information writing operation, so that the electrical reliability is improved. It is possible to improve the property.

Further, the junction depth of the source region (n + type semiconductor region 11) of the field effect transistor of the flash type nonvolatile memory element Qm is set deep and the junction depth of the drain region (n type semiconductor region 14) is set. To be shallow. With this configuration, (3) the diffusion amount of the source region toward the channel formation region side can be increased, and the overlapping area of the source region and the information storage gate electrode 7 can be increased to increase the tunnel area. The tunnel current amount can be increased to improve the information erasing efficiency, and (4) the diffusion amount of the drain region toward the channel formation region side can be reduced, and the overlap area between the drain region and the information storage gate electrode 7 can be reduced. Since it is possible to reduce the coupling capacitance between the drain region and the information storage gate electrode 7, it is possible to prevent the conduction phenomenon of the memory cells in the non-selected state at the time of the information writing operation and prevent the leakage current. Information writing characteristics can be improved.

The drain region (n-type semiconductor region 14) of the flash type nonvolatile memory element Qm is added to the data line DL (wiring 21) by making the impurity concentration low and the junction depth shallow. Since the parasitic capacitance can be reduced and the information read operation speed can be increased,
The operating speed can be increased.

The channel length of the flash type nonvolatile memory element Qm is reduced by reducing the coupling capacitance formed between the drain region of the flash type nonvolatile memory element Qm and the information storage gate electrode 7. Therefore, the area of the memory cell can be reduced and high integration can be achieved.

Further, the resistance value of the source region and the source line can be reduced by configuring the source region of the flash type nonvolatile memory element Qm to have a high impurity concentration or a shallow junction depth. It is possible to perform stable information writing operation, information reading operation, and information erasing operation without any voltage drop or rise.

In the source region of the flash type nonvolatile memory element Qm, the n-type impurity 11n forming the high impurity concentration n + type semiconductor region 11 and the low impurity concentration n are formed.
Since each of the n-type impurities 12n forming the type semiconductor region 12 is introduced by using the same impurity introduction mask 30, the EEP is equivalent to the step of introducing one impurity.
The number of ROM manufacturing steps can be reduced.

The manufacturing method of the EEPROM is not limited to the above-described manufacturing method, and can be formed by the following other manufacturing methods.

<Manufacturing Method 1> First, after the step shown in FIG. 5, the n-type impurity 12n is introduced into the formation region of the source region of the flash type nonvolatile memory element Qm.

Next, the flash type nonvolatile memory device Q
In the formation region of the drain region of m, p-type impurities 13p and n
A type impurity 14n is introduced.

Next, the introduced impurities are expanded and diffused to remove the low impurity concentration n-type semiconductor region 12, the high impurity concentration p + type semiconductor region 13, and the low impurity concentration n-type semiconductor region 14, respectively. Form.

Next, the flash type nonvolatile memory device Q
The n-type impurity 11n is introduced into the formation region of the source region of m, and the n-type impurity 11n is stretched and diffused to obtain n.
A + type semiconductor region 11 is formed.

Thereafter, the steps shown in FIG. 9 and subsequent steps are performed to complete the EEPROM.

<Manufacturing Method 2> First, after the step shown in FIG. 5, the n-type impurity 12n is introduced into the formation region of the source region of the flash type nonvolatile memory element Qm.

Next, the flash non-volatile memory device Q
A p-type impurity 13p is introduced into the formation region of the drain region of m.

Next, the introduced impurities are stretched and diffused to form the low impurity concentration n-type semiconductor region 12 and the high impurity concentration p + -type semiconductor region 13, respectively.

Next, the flash type non-volatile memory device Q
The n-type impurity 14 is introduced into the formation region of the drain region of m, and the n-type impurity 14 is expanded and diffused to form the n-type semiconductor region 14 of low impurity concentration.

Next, the flash type nonvolatile memory device Q
The n-type impurity 11n is introduced into the formation region of the source region of m, and the n-type impurity 11n is stretched and diffused to obtain n.
A + type semiconductor region 11 is formed.

After this, the steps shown in FIG. 9 and subsequent steps are performed to complete the EEPROM.

<Manufacturing Method 3> First, after the step shown in FIG. 5, the n-type impurity 12n is introduced into the formation region of the source region of the flash type nonvolatile memory element Qm.

Next, the flash type nonvolatile memory device Q
An n-type impurity 14n is introduced into the formation region of the drain region of m.

Next, the flash type nonvolatile memory device Q
An n-type impurity 11n is introduced into the formation region of the source region of m.

Next, the introduced impurities are stretched and diffused to remove the low impurity concentration n-type semiconductor region 12, the high impurity concentration n + type semiconductor region 11, and the low impurity concentration n-type semiconductor region 14, respectively. Form.

Next, the flash type nonvolatile memory element Q
A p-type impurity 13p is introduced into the formation region of the drain region of m, and the p-type impurity 13p is expanded and diffused to form the p + -type semiconductor region 13 of high impurity concentration.

Thereafter, the steps shown in FIG. 9 and subsequent steps are performed to complete the EEPROM.

As described above, the invention made by the present inventor is
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, the present invention can be applied to an ultraviolet erasing type read-only nonvolatile memory circuit (EPROM). The flash type nonvolatile memory element of the EEPROM is composed of a field effect transistor having an information storage gate electrode and a control gate electrode.

[0088]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a non-volatile memory circuit, it is possible to improve information erasing efficiency and information writing characteristics.

Further, the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, the operating speed of the semiconductor integrated circuit device can be increased.

Further, high integration of the semiconductor integrated circuit device can be achieved.

[0093]

[Table 1]

[Brief description of drawings]

FIG. 1 is a main-portion cross-sectional view showing the structure of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a sectional view of an essential part of the EEPROM, showing each manufacturing step.

FIG. 3 is a sectional view of an essential part of the EEPROM shown in each manufacturing step.

FIG. 4 is a sectional view of an essential part of the EEPROM shown in each manufacturing step.

FIG. 5 is a sectional view of an essential part of the EEPROM, showing each manufacturing step.

FIG. 6 is a sectional view of an essential part of the EEPROM, showing each manufacturing step.

FIG. 7 is a cross-sectional view of an essential part of the EEPROM shown in each manufacturing process.

FIG. 8 is a sectional view of an essential part of the EEPROM shown in each manufacturing step.

FIG. 9 is a sectional view of an essential part of the EEPROM, showing each manufacturing step.

FIG. 10 is a sectional view of an essential part of the EEPROM, showing each manufacturing step.

[Explanation of symbols]

2, 3 ... Well regions, 6, 8 ... Gate insulating film, 7, 9 ...
Gate electrode, 11, 12, 13, 14, 15, 17, 1
8 ... Semiconductor region, 11n, 12n, 13p, 114n ...
Impurities, Qm ... Flash type nonvolatile memory element, Q
n, Qp ... MISFET.

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[Procedure amendment]

[Submission date] December 6, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0001

[Correction method] Change

[Correction content]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
The present invention relates to a manufacturing method , in particular, a flash type nonvolatile memory device.
The present invention relates to a technique effectively applied to a method of manufacturing a storage device having a child .

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

BACKGROUND ART Electrically Erasable a nonvolatile memory circuit of the read-only capable EEPROM (E lectrically E rasab
le P rogrammable R ead O nly M emory) nonvolatile memory device as a device type non-volatile memory device have been proposed. This non-volatile memory element is composed of a field effect transistor having an information storage gate electrode (floating gate electrode) and a control gate electrode (control gate electrode). The source region of the field effect transistor is connected to the source line, and the drain region is connected to the data line.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification number Reference number in the agency FI Technical indication location H01L 27/115 (72) Inventor Hitoshi Kume 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Hitachi Central Inside the research institute (72) Inventor Yoshiaki Kamaki 1-280, Higashi Koigakubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (13)

[Claims] 1. A semiconductor substrate having a main surface, a first semiconductor region and a second semiconductor region formed in the semiconductor substrate, and between the first semiconductor region and the second semiconductor region in the semiconductor substrate. A channel forming region to be formed, a first gate insulating film formed on the channel forming region, a floating gate electrode formed on the first gate insulating film, and a floating gate electrode formed on the floating gate electrode. Injecting hot carriers into the floating gate electrode in a method of manufacturing a semiconductor memory device having a memory cell including a formed second gate insulating film and a control gate electrode formed on the second gate insulating film. Information is stored in the memory cell, and the injected hot carriers are passed from the floating gate electrode through the first gate insulating film. Method of manufacturing a semiconductor memory device characterized by erasing the information by releasing to the first semiconductor region by tunneling. 2. A semiconductor substrate having a main surface, a first semiconductor region and a second semiconductor region formed in the semiconductor substrate, and between the first semiconductor region and the second semiconductor region in the semiconductor substrate. A channel forming region to be formed, a first gate insulating film formed on the channel forming region, a floating gate electrode formed on the first gate insulating film, and a floating gate electrode formed on the floating gate electrode. A second gate insulating film and a control gate electrode formed on the second gate insulating film, and stores information by injecting hot carriers into the floating gate electrode, The injected hot carriers are tunneled from the floating gate electrode through the first gate insulating film to the first semiconductor region. In a method of manufacturing a semiconductor memory device in which information is erased by discharging into a region, a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode are sequentially stacked on the main surface of the semiconductor substrate. Forming a first semiconductor region in the semiconductor substrate by introducing impurities in a self-aligned manner with respect to one end of the control gate electrode; Forming a second semiconductor region in the semiconductor substrate by introducing an impurity in a self-aligned manner with respect to an end portion, the first semiconductor region having the same conductivity type as the second semiconductor region, The impurity dose amount in the first semiconductor region forming step is higher than the impurity dose amount in the second semiconductor region forming step, In-band formation step, the impurity is
A method of manufacturing a semiconductor memory device, wherein a mask film covering an upper portion of the second semiconductor formation region is used as a mask. 3. The impurity in the first semiconductor region forming step and the second semiconductor region forming step is arsenic, and the dose amount of arsenic in the first semiconductor region forming step is equal to that of arsenic in the second semiconductor region forming step. The method for manufacturing a semiconductor memory device according to claim 2, wherein the dose amount is higher than the dose amount. 4. A step of introducing impurities into one end of the control gate electrode in a self-aligning manner to form a third semiconductor region deeper than the first semiconductor region in the semiconductor substrate, The impurity in the third semiconductor region forming step is phosphorus, and a dose amount of phosphorus in the third semiconductor region forming step is lower than an arsenic dose amount in the first semiconductor region forming step. 3. The semiconductor memory device according to item 3. 5. An impurity is introduced into one end of the control gate electrode in a self-aligning manner, and a fourth impurity is introduced into at least a second semiconductor region side of the channel forming region in the semiconductor substrate. Including a step of forming a semiconductor region, wherein the fourth semiconductor region has a conductivity type opposite to a conductivity type of the first semiconductor region, and an impurity concentration of the fourth semiconductor region is higher than an impurity concentration of the semiconductor substrate. The method for manufacturing a semiconductor memory device according to claim 4, wherein the manufacturing method is high. 6. The extension of the first semiconductor region to the channel formation region below the floating gate electrode is larger than the extension of the second semiconductor region to the channel formation region. The semiconductor memory device according to 1. 7. The method of manufacturing a semiconductor memory device according to claim 3, wherein a junction depth of the first semiconductor region is deeper than a junction depth of the second semiconductor region. 8. A semiconductor substrate having a main surface, a first semiconductor region and a second semiconductor region formed in the semiconductor substrate, and between the first semiconductor region and the second semiconductor region in the semiconductor substrate. A channel forming region to be formed, a first gate insulating film formed on the channel forming region, a floating gate electrode formed on the first gate insulating film, and a floating gate electrode formed on the floating gate electrode. MISFET forming a peripheral circuit, and a memory cell including a formed second gate insulating film and a control gate electrode formed on the second gate insulating film.
A method of manufacturing a semiconductor memory device having: a first gate insulating film, a floating gate electrode, a second gate insulating film, and a control gate electrode, which are sequentially laminated on the main surface of the semiconductor substrate, and In the peripheral circuit formation region of the main surface, the MISF is formed on the main surface.
Forming a gate insulating film of ET and a gate electrode of the MISFET on the gate insulating film; and introducing impurities in self-alignment with respect to one end of the control gate electrode in the memory cell forming region. And forming a first semiconductor region in the semiconductor substrate, and in the memory cell formation region, introducing impurities in a self-aligned manner into at least the other end of the control gate electrode in the semiconductor substrate. Forming a second semiconductor region on the main surface, and forming the second semiconductor region in the peripheral circuit formation region of the main surface.
Forming a fifth semiconductor region in the semiconductor substrate by introducing impurities in a self-aligned manner to one end of the T gate electrode; and forming the first, second and fifth semiconductor regions. After that, first sidewall spacers are formed in self-alignment with the sidewalls of the control gate electrode and the floating gate electrode in the memory cell formation region of the main surface, and the MIS is formed in the peripheral circuit formation region.
Forming a second sidewall spacer in a self-aligned manner with respect to the side wall of the gate electrode of the FET; and introducing impurities in a self-aligned manner with respect to the second sidewall spacer in the peripheral circuit formation region of the main surface. And forming a sixth semiconductor region in the semiconductor substrate, wherein the first, second, fifth and sixth semiconductor regions are of the same conductivity type, and the impurities of the first semiconductor region forming step are included. The dose amount is higher than the impurity dose amount in the second semiconductor region forming step, the impurity dose amount in the first semiconductor region forming step is higher than the impurity dose amount in the fifth semiconductor region forming step, and The impurity dose amount in the sixth semiconductor region forming step is higher than the impurity dose amount in the fifth semiconductor region forming step, and Junction depth is deeper than the junction depth of the fifth semiconductor region, the fifth semiconductor region is formed between the sixth semiconductor region and the channel formation region of the MISFET, and the fifth and sixth semiconductor regions are formed. A method of manufacturing a semiconductor memory device, wherein a semiconductor region acts as a drain of the MISFET. 9. The impurity in the first semiconductor region forming step and the second semiconductor region forming step is arsenic, and the dose amount of arsenic in the first semiconductor region forming step is equal to that of the arsenic in the second semiconductor region forming step. The method of manufacturing a semiconductor memory device according to claim 8, wherein the dose amount is higher than the dose amount. 10. A step of introducing an impurity into one end of the control gate electrode in a self-aligned manner to form a third semiconductor region deeper than the first semiconductor region in the semiconductor substrate, The impurity in the third semiconductor region forming step is phosphorus, and a dose amount of phosphorus in the third semiconductor region forming step is lower than an arsenic dose amount in the first semiconductor region forming step. 9. The semiconductor memory device according to item 9. 11. An impurity is introduced into one end of the control gate electrode in a self-aligned manner to form at least a second portion of the channel formation region in the semiconductor substrate.
A step of forming a fourth semiconductor region in a portion on the semiconductor region side, wherein the fourth semiconductor region has a conductivity type opposite to the conductivity type of the first semiconductor region, and the impurity concentration of the fourth semiconductor region is 10. The method of manufacturing a semiconductor memory device according to claim 9, wherein the impurity concentration is higher than that of the semiconductor substrate. 12. The extension of the first semiconductor region to the channel formation region below the floating gate electrode is larger than the extension of the second semiconductor region to the channel formation region. The semiconductor memory device according to 1. 13. The method of manufacturing a semiconductor memory device according to claim 9, wherein a junction depth of the first semiconductor region is deeper than a junction depth of the second semiconductor region.