JPH06334156A - Nor type flash memory - Google Patents

Abstract

PURPOSE:To overlap a ground line a and a bit line on a semiconductor layer as an active layer and enhance the degree of integration by making the area of a memory cell small. CONSTITUTION:The upper layer and the lower layer of a Si layer 44 as the active layer of a transistor 16 for memory cell are extended the AlSiCu film 72 and Ti/TiN/Ti film 71 as the bit line and the tungsten polyside film 38 as the ground line. The ground line is connected to the source 14 of the transistor 16 through an impurity region 64 provided through the Si layer 44 and the bit line is connected to the drain 15 of the transistor 16 through a contact hole 62.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NOR flash memory in which data is written and erased in batch by injecting electrons into the entire surface of a channel and extracting the electrons from a substrate.

[0002]

21 and 22 show a floating gate type NOR.
Shows a type flash memory. In this flash memory, the floating gate 12 is formed on the gate insulating film on the surface of the p-type semiconductor substrate 11 or the well, and the control gate 13 extends on the floating gate 12 via the insulating film for capacitive coupling. is doing. Floating gate 12 and control gate 1
A source 14 and a drain 15 are formed in the n ⁺ -type impurity region on the semiconductor substrate 11 on both sides of 3, and the transistor 16 forms one memory cell.

FIG. 23 shows a MONOS type NOR flash memory. In this flash memory,
SiO is formed on the surface of the p-type semiconductor substrate 11 or the well.
_{The second} film 17, the Si ₃ N ₄ film 18, and the SiO ₂ film 19 are sequentially laminated, and the control gate 13 is formed on the SiO ₂ film 19.
Has been extended. Semiconductor substrate 1 on both sides of control gate 13
1, a source 14 and a drain 15 are formed in an n ⁺ type impurity region, and one memory cell is formed by this transistor 21.

There are two types of NOR flash memory, a hot electron injection type and a Fowler-Nordheim tunnel injection type. However, it is necessary to increase the number of times of writing / erasing and reduce the current consumption at the time of injection.
The Fowler-Nordheim tunnel injection type in which the deterioration of the gate insulating film is small and the channel current does not flow is becoming mainstream. The Fowler-Nordheim tunnel injection type also has the following two methods.

First, in the first method, as shown in FIG. 21A, a channel 22 is formed between the source 14 and the drain 15.
21 is formed and electrons are injected into the floating gate 12 from the channel 22 and the drain 15 or the source 14, and FIG.
As shown in (b), electrons are extracted from the floating gate 12 to the drain 15 or the source 14. Note that + V _i is a voltage for injecting electrons into the floating gate 12, and −V _e
− (+ V _CC ) is a voltage for extracting electrons from the floating gate 12, and F indicates a floating state.

In the second method, as shown in FIG. 22A, a channel 22 is formed between the source 14 and the drain 15.
Then, electrons are injected from the channel 22 to the floating gate 12, and as shown in FIG.
Electrons are extracted from the semiconductor substrate 11 to the semiconductor substrate 11. In the second method, the SiO ₂ film 19 is used even in the MONOS type shown in FIG.
This is possible by injecting electrons into the trap 23 existing at the interface between the Si ₃ N ₄ film 18 and the Si ₃ N ₄ film 18 and extracting the electron from the trap 23.

22 and 23, + V _i is a voltage for injecting electrons into the floating gate 12 or the trap 23, and −V _E is a voltage for extracting electrons from the floating gate 12 or the trap 23. , F indicate a floating state.

By the way, as shown in FIG. 21, the drain 1
In the method of extracting electrons to 5, the Fowler-Nordheim tunnel current flows only in the narrow overlapping region of the floating gate 12 and the drain 15, so that the current density is high. Therefore, the gate insulating film is easily deteriorated, and the upper limit of the number of writing / erasing is about 10 ⁶ . This number is 10 ⁶ to 10 ⁷
In order to increase the number of times or more, since it is possible to extract electrons in a large area, it is possible to reduce the density of Fowler-Nordheim tunnel current. As shown in FIGS. 22 and 23, the method of extracting electrons to the semiconductor substrate 11 is advantageous. Is.

FIG. 25 shows a 4-bit memory cell array in the first conventional example of the floating gate type NOR flash memory, and FIG. 24 shows an equivalent circuit thereof. In the first conventional example, the active region 24 extends in a stripe shape in the semiconductor substrate 11, and the word lines W ₁ and W _2, that is, the control gate 13 is formed in the active region 24 on the semiconductor substrate 11.
It extends in a direction orthogonal to. Under the word lines W ₁ and W ₂ , the floating gate 12 is arranged corresponding to each of the memory cells M _{11 to} M ₂₂ .

Bit lines B ₁ and B ₂ extending in a direction orthogonal to the word lines W ₁ and W ₂ are connected to the drain 15 of each of the memory cells M _{11 to} M ₂₂ via a contact hole 25. Has been done. The word line W _1, the W memory cell M ₁₁ in a row in the direction perpendicular to _2, M ₂₁ and M _12, common source 14 to M _22, the word line W _1, W ₂ parallel to the clogging A ground line S extending in a direction orthogonal to the bit lines B ₁ and B ₂ is connected via a contact hole 26.

FIG. 27 shows a 4-bit memory cell array in the second conventional example of the floating gate type NOR flash memory, and FIG. 26 shows an equivalent circuit thereof. In this second conventional example, the ground lines S ₁ and S ₂ are extended in the direction orthogonal to the word lines W ₁ and W ₂ , that is, in the direction parallel to the bit lines B ₁ and B ₂ . It has substantially the same structure as the first conventional example shown in FIG.

The following Tables 1 and 2 show operating voltages at the time of collective erasing and at the time of writing and reading to / from the memory cell M ₂₂ , respectively, in the method of drawing electrons to the drain 15 and the method of drawing electrons to the semiconductor substrate 11. ing. Tables 1 and 2 show the case of a floating gate type NOR flash memory using NMOS transistors.
When using a MOS transistor, the sign of the voltage may be reversed. The same can be applied to the case of a MONOS NOR flash memory.

In the method of extracting electrons to the drain 15 as shown in FIG. 21, each of the memory cells M _{11 to} M ₂₂ can be selected for both injection and extraction, but it is shown in FIGS. As described above, in the method of extracting electrons into the semiconductor substrate 11, each memory cell M _{11 is} only injected at the time of injection.
~ M ₂₂ cannot be selected. Therefore, in Table 1, electron extraction is written, but in Table 2, electron injection is written.

[0014]

[0015] The voltage between the word line and a bit line + V _i - (+
In the memory cell M ₂₁ , which is V _M ), no electrons are injected into the floating gate.

[0016]

By the way, in the first conventional example shown in FIG. 25, the drain 15 as shown in FIG.
With the method of extracting electrons to the H, there is no hindrance to the operation. However, in the method of extracting electrons into the semiconductor substrate 11 as shown in FIG. 22, in a write operation to the memory cell M ₂₂ shown in Table 2, the bit line B ₁ (+ V _M) → memory cells M
₂₁ drain 15 → memory cell M ₂₁ channel 22 → memory cell M ₂₁ source 14 → ground line S → memory cell M ₂₂
Source 14 → current flows through a path of the drain 15 → bit line B ₂ channels 22 → memory cell M ₂₂ in the memory cell M ₂₂ (0V) of.

Therefore, in the first conventional example shown in FIG. 25, the current consumption increases and at the same time, the bit lines B ₁ and B ₂
Voltage fluctuates from + V _M and 0 V, respectively, resulting in write failure and write disturb. On the other hand, FIG.
In the second conventional example shown in (1), no current flows through the above-mentioned path.

However, in the first conventional example shown in FIG.
Although the bit lines B ₁ and B ₂ and the ground line S can be orthogonal to each other, in the second conventional example shown in FIG. 27, the bit lines B ₁ and B ₂ and the ground lines S ₁ and S ₂ are opposite to each other. Must extend in the same direction. Therefore, in the first conventional example, it is not necessary to consider the positional relationship between the contact holes 25 and 26, but in the second conventional example, the bit lines B ₁ and B ₂ do not contact the ground lines S ₁ and S _2. The contact holes 25, 26
It is necessary to shift them in the extending direction of the word lines W ₁ and W ₂ .

Therefore, in order to increase the number of times of writing / erasing, a method of extracting electrons to the semiconductor substrate 11 is adopted as shown in FIG. 22, and even if this method is adopted, current consumption is reduced and writing is performed. If the second conventional example shown in FIG. 27 is adopted instead of the first conventional example shown in FIG. 25 in order to prevent a defect or a write disturb from occurring, FIG.
As can be seen from the comparison between the memory cell area 27 in FIG. 5 and the memory cell area 27 in FIG.
Became large and it was difficult to increase the degree of integration.

[0020]

According to another aspect of the NOR flash memory of the present invention, a semiconductor layer 44 in which a source 14, a drain 15 and a channel region of a transistor 16 for a memory cell are formed extends in a strip shape. The ground line 38 and the bit lines 71 and 72 extend along the semiconductor layer 44 via the insulating films 36, 55, 56 and 67 in one of the upper layer and the lower layer of the semiconductor layer 44, and The ground line 38 and the bit lines 71 and 72 are connected to the source 14
Alternatively, it is electrically connected to the drain 15.

According to another aspect of the NOR type flash memory of the present invention, in the NOR type flash memory of the first aspect, the semiconductor is formed through contact holes 61 and 62 formed in self alignment with the gates 52 and 54 of the transistor 16. An impurity region 64 formed of an impurity 63 of the same conductivity type as the source 14 or the drain 15 introduced into the layer 44 and penetrating the semiconductor layer 44.
The ground line 38 or the bit lines 71, 72 and the source 14 or the drain 15 in the lower layer.
And are electrically connected.

A NOR type flash memory according to a third aspect is the NOR type flash memory according to the first or second aspect, wherein the mask layer 5 has an opening 57a extending in a strip shape in a direction intersecting with the gates 52 and 54 of the transistor 16.
7, the gates 52 and 54 and the semiconductor layer 4
The contact hole 6 self-aligned with the gates 52 and 54 by etching the insulating film 56 covering
1, 62 are formed.

According to the NOR type flash memory of claim 4, in the NOR type flash memory of any one of claims 1 to 3, charges are accumulated in the floating gate 52.

According to the NOR type flash memory of the fifth aspect, in the NOR type flash memory according to any one of the first to third aspects, charges are accumulated in the traps of the insulating films 18 and 19.

[0025]

In the NOR flash memory of the first aspect, the ground line 38 and the bit lines 71 and 72 extend above and below the semiconductor layer 44 which is the active layer of the transistor 16 for the memory cell. , Ground line 38 and bit lines 71, 7
Although both 2 and 2 extend in the same direction along the semiconductor layer 44, these ground line 38 and bit lines 71, 72
The ground line 38 and the bit lines 71 and 72 can be superposed on the semiconductor layer 44 without arranging and to be shifted in the direction perpendicular to the semiconductor layer 44.

According to another aspect of the NOR flash memory of the present invention, the ground line 38 or the bit line 7 under the semiconductor layer 44 is provided.
Impurity regions 64 that electrically connect 1 and 72 to the source 14 or the drain 15 of the transistor 16 are formed in contact holes 61 and 62 that are formed in self-alignment with the gates 52 and 54 of the transistor 16. Since it is formed of the impurity 63 introduced into the semiconductor layer 44, the impurity region 64 can be easily formed.

According to another aspect of the NOR flash memory of the present invention, the mask layer 57 for forming the contact holes 61, 62 self-aligned with the gates 52, 54 of the transistor 16 is in a direction intersecting the gates 52, 54. Since the band-shaped opening 57a has an opening 57a extending in a band shape and the width of the band-shaped opening 57a can be narrower than that of an isolated hole-shaped opening, the contact holes 61 and 62 can be miniaturized. .

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention applied to a floating gate type NOR flash memory will be described below with reference to FIGS.

1 to 5 show this embodiment. In order to manufacture this embodiment, as shown in FIG.
P>100> plane and resistivity of 10 to 20 Ω · cm
On the surface of the Si substrate 31 of the mold
_{2 The} film 32 is formed by thermal oxidation or CVD. Then, in addition to the element isolation region of the memory cell portion, the photoresist 33 is processed into a pattern having an alignment mark and an isolation region between the P well and the N well in an area to be formed later.

Thereafter, by using the photoresist 33 as a mask, the SiO ₂ film 32 and the Si substrate 31 are anisotropically dry-etched to form a trench 34 having a width of 500 nm or less and a depth of 400 nm in the Si substrate 31. To do. Then, after removing the photoresist 33, NH ₄
The surface of the Si substrate 31 is 5-10 nm with OH + H ₂ O ₂ liquid.
Wet etch over the thickness of to remove any damage that was encountered with dry etching.

Next, as shown in FIG. 7A, the photoresist 35 is processed into a pattern having an opening in the portion of the ground line and a wiring formed at the same time later. Then, using this photoresist 35 as a mask, S is diluted with dilute hydrofluoric acid solution.
The iO ₂ film 32 is removed by wet etching. Then, the photoresist 35 is removed.

Next, a 10 nm thick SiO ₂ film is formed on the surface of the Si substrate 31 by thermal oxidation, and then a 270 nm thick SiO ₂ film 36 is formed by CVD as shown in FIG. 7B.
Then, the trench 34 is flattened. Then N
₂ Anneal at 900 ℃ for 30 minutes,
The SiO ₂ film 36 is densified.

Next, the SiO ₂ film 36 is anisotropically dry-etched by using a photoresist (not shown) as a mask, so that a ground line and a Si substrate 31 to be formed later are formed as shown in FIG. The contact hole 37 is formed in the trench 34.
400 × 460 nm ² at the specified position by aligning with
Make a hole with the size of.

Next, as shown in FIG. 9, the film thickness is 200 nm.
By sequentially depositing a phosphorus-doped polycrystalline Si film and a WSi ₂ film having a thickness of 100 nm, a tungsten polycide film 38 having a thickness of 300 nm is formed on the entire surface. Then, using a photoresist (not shown) as a mask, the tungsten polycide film 38 is anisotropically dry-etched to form a ground line.

At this time, as shown in FIG. 10, the space b between the tungsten polycide films 38 and the SiO 2 at the end portions of the tungsten polycide film 38 and the memory cell array portion.
The distance b between the step portion of the _two films 36 is made equal to each other.
When forming the tungsten polycide film 38, instead of depositing a phosphorus-doped polycrystalline Si film, a polycrystalline Si film containing no impurities is deposited, and an implantation energy of 50 keV and 5 is applied to the polycrystalline Si film. × 10 ¹⁵
Ion-implant phosphorus or arsenic at a dose of cm ^-2
Annealing may be performed at 000 ° C. for 10 seconds.

Next, as shown in FIG.
A 300 nm SiO ₂ film 41 is deposited by CVD. By the way, as shown in FIG. 10, since the film thickness a of the tungsten polycide film 38 and the film thickness a of the SiO ₂ film 32 are equal to each other, the SiO ₂ at the end of the memory cell array portion is formed.
The level difference between the _two films 36 and the film thickness of the tungsten polycide film 38 are equal to each other, and as described above, the interval b between the tungsten polycide films 38 and the step difference between the tungsten polycide film 38 and the SiO ₂ film 36 are formed. The intervals b between them are also equal to each other.

Therefore, the entire surface of the Si substrate 31 is flattened by the deposited SiO ₂ film 41. After that, the surface of the SiO ₂ film 41 is polished as needed to improve the flatness of the surface.

Next, as shown in FIG. 12A, a film thickness of 100 nm is formed on the surface of the Si substrate 42 different from the Si substrate 31.
The BPSG film 43 is deposited, and the surface of the BPSG film 43 is polished as needed to improve the flatness of the surface. Then, the SiO ₂ film 41 of the Si substrate 31 and the BPSG film 43 of the Si substrate 42 are brought into contact with each other, and a temperature of 950 ° C. is applied for 10 minutes to bond the Si substrate 31 and the Si substrate 42 together.

Next, as shown in FIG. 12B, Si is formed until the SiO ₂ film 36 filling the trench 34 is exposed.
The surface of the substrate 31 opposite to the SiO ₂ film 41 is ground and polished. As a result, the Si substrate 31 remains in a striped shape surrounded by the SiO ₂ film 36, and the Si substrate 31 becomes the Si layer 44 as an active layer.

Next, a portion of the Si layer 44 including the memory cell array portion where the P well is to be formed is masked with a photoresist (not shown), and the portion where the N well is to be formed is set to 150 keV. Implantation energy and 1 × 10 ¹³
Phosphorus is ion-implanted at a dose of cm ^-2 to change the conductivity type of the Si layer 44 in this portion to n-type.

After removing the photoresist in the portion where the P well is to be formed, the N layer of the Si layer 44 is removed.
Photoresist (not shown) where the well is to be formed
Mask with. Then, in the portion where the P well is to be formed,
Boron is ion-implanted at an implantation energy of 150 keV and a dose amount of 1 × 10 ¹⁴ cm ⁻² , and the Si layer 4 at this portion is implanted.
The conductivity type of No. 4 is converted to p ⁺ , leaving the vicinity of the surface.

After that, high-speed annealing is performed at 950 ° C. for 10 seconds to form an N well 45 and a P well 46 as shown in FIG. Then, as shown in FIG. 13B, a SiO ₂ film 47 having a thickness of 200 nm is formed on the wide element isolation region in the N well 45 and the P well 46 as L
It is formed by the OCOS method. Under the SiO ₂ film 47,
The channel stopper 48 is formed.

Next, after ion implantation of impurities for controlling the threshold voltage, as shown in FIG. 14, a Si layer 44 is formed.
8n of SiO ₂ film 51 as a gate insulating film on the surface of
It is formed to a film thickness of m. Then, the polycrystalline Si film 5 having a film thickness of 30 nm and a phosphorus concentration of 0.5 to 1 × 10 ²⁰ cm ⁻³
2 is deposited, and the polycrystalline Si film 52 is anisotropically dry-etched into a pattern extending along the Si layer 44.

After that, a SiO ₂ film 53 as an insulating film for capacitive coupling is formed on the surface of the polycrystalline Si film 52 to a thickness of 12 nm. Then, a tungsten polycide film 54 consisting of a polycrystalline Si film having a film thickness of 50 nm and a WSi ₂ film having a film thickness of 100 nm is formed on the entire surface, and a film thickness of 200 is further formed.
A SiO ₂ film 55 nm of thickness is deposited on the tungsten polycide film 54 by CVD.

Thereafter, the SiO ₂ film 55, the tungsten polycide film 54, the SiO ₂ film 53, and the polycrystalline Si film 52 are continuously anisotropically dry-etched into a pattern extending orthogonal to the Si layer 44. As a result, a control gate is formed of the tungsten polycide film 54 and a floating gate is formed of the polycrystalline Si film 52.

Then, using the SiO ₂ film 55, the tungsten polycide film 54, etc. as a mask, arsenic is ion-implanted into the Si layer 44 at an implantation energy of 10 keV and a dose of 1 × 10 ¹⁴ cm ^-2 , and the temperature is set to 1000 ° C. By performing annealing for 10 minutes, the source 1 which is an n-type impurity region
4 and the drain 15 are formed. Up to this point, the transistor 16 forming a memory cell is completed.

Although the transistor 16 in the memory cell portion has a non-LDD structure, the transistor (not shown) in the peripheral circuit portion has an LDD structure. Therefore, following the ion implantation for forming the n-type impurity region, arsenic is ion-implanted again at an implantation energy of 10 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² , so that the n ⁺ -type impurity region is implanted. Also forms.

Next, as shown in FIG. 15, the film thickness is 120 n.
m of SiO ₂ film 56 is deposited on the entire surface by CVD, and then S
The photoresist 57 is processed into a pattern having an opening 57a extending in a band shape in a direction orthogonal to the tungsten polycide film 54 above the i layer 44. Then, using this photoresist 57 as a mask, the SiO ₂ is removed until the surface of the Si layer 44 in the source 14 and the drain 15 appears.
The film 56 is anisotropically dry etched.

As a result, the side wall made of the SiO ₂ film 56 is formed on the side surface of the tungsten polycide film 54 in the portion corresponding to the opening 57a, and the contact holes 61 and 62 reaching the source 14 and the drain 15 are formed by the tungsten polycide. The side film 54 and the polycrystalline Si film 52 are opened in a self-aligned manner.

Next, as shown in FIG. 16, the photoresist 57 and SiO ₂ are left with the photoresist 57 left.
Using the films 55, 56, etc. as a mask, phosphorus 63 is 100 ke
Implantation energy of V and dose of 5 × 10 ¹⁴ cm ^-2 and 2
Ions are implanted into the Si layer 44 from the contact holes 61 and 62 in two steps with an implantation energy of 00 keV and a dose amount of 5 × 10 ¹⁴ cm ⁻² , and then annealing is performed at 1000 ° C. for 10 seconds. As a result, an n ⁺ type impurity region 64 penetrating the Si layer 44 is formed, and the source 14 and the tungsten polycide film 38 are electrically connected.

The impurity for forming the impurity region 64 may be of the same conductivity type as the source 14 and the drain 15, and arsenic may be used instead of the phosphorus 63. Further, since the drain 15 is electrically connected not to the tungsten polycide film 38 as the ground line but to the bit line to be formed later, it is not necessary to form the impurity region 64 in the drain 15. However, in order to prevent the impurity region 64 from being formed in the drain 15, the contact hole 6
Since a photoresist with a pattern covering 2 is required,
It is easier to form the impurity region 64 in the drain 15 as well.

Next, the photoresist 57 and the source 1
After removing the native oxide film on the surface of 4 and the drain 15,
As shown in FIG. 17, a polycrystalline Si film 65 containing no impurities
Is deposited over the entire surface to a thickness of 120 nm to fill the recesses between the contact holes 61 and 62 and the tungsten polycide film 54. Then, the polycrystalline Si film 65 is etched back until the film thickness of the polycrystalline Si film 65 between the tungsten polycide films 54 becomes about 100 nm. At this time, the etching selection ratio of polycrystalline Si and SiO ₂ is set to 2
Set a high value of about 00: 1.

Thereafter, arsenic was ion-implanted into the polycrystalline Si film 65 at an implantation energy of 20 keV and a dose amount of 5 × 10 ¹⁵ cm ^-2 , and further annealed at 900 ° C. for 10 seconds in an N ₂ atmosphere, A part of the polycrystalline Si film 65 in the thickness direction is turned into n ⁺ .

Next, as shown in FIG. 18, a Si ₃ N ₄ film 6 is formed.
6 is deposited to a thickness of 50 nm on the entire surface, and only the Si ₃ N ₄ film 66 in the portion covering the contact hole 62 on the drain 15 is left, and the Si ₃ N ₄ film 66 in the other portion is removed by etching. Then, using the Si ₃ N ₄ film 66 as an oxidation-resistant mask, the polycrystalline Si film 65 in the portion not covered with the Si ₃ N ₄ film 66 is oxidized to form a SiO ₂ film 67.

At this time, the oxidizing conditions are 850 ° C., H ₂ / O ₂
= 1.5, 60 minutes, all the portions of the polycrystalline Si film 65 other than those on the contact holes 61, 62 are converted into the SiO ₂ film 67. During this oxidation, polycrystalline S
Arsenic that has already been doped is diffused into the i film 65, and the entire portion of the polycrystalline Si film 65 that remains without being oxidized is turned into n ⁺ .

Next, as shown in FIG. 19, the Si ₃ N ₄ film 66 is etched with hot phosphoric acid at 160 ° C. Then, the Ti film having a thickness of 2 nm and the TiN film having a thickness of 12 nm are C
The Ti / TiN / Ti film 71 is formed as a barrier metal film by sequentially depositing by VD and further by depositing a Ti film with a thickness of 30 nm by sputtering.
The AlSiCu film 72 having a thickness of nm is deposited.

After that, a photoresist (not shown) is processed into a bit line pattern, and the AlSiCu film 72 and the Ti / TiN / Ti film 7 are used as a mask for this photoresist.
1 and 2 are anisotropically dry-etched to form a bit line. This bit line is in contact with the drain 15 through the polycrystalline Si film 65 remaining under the Si ₃ N ₄ film 66. After that, conventionally known processes such as formation of a surface protective film (not shown) are executed to complete the present embodiment.

Although the present invention is applied to the floating gate type NOR flash memory using the NMOS transistor in the above embodiment, the present invention is also applied to the floating gate type NOR flash memory using the PMOS transistor. The invention can be applied.

Further, as shown in FIG. 20, a 2 nm thick SiO ₂ film 17, a 5 nm thick Si ₃ N ₄ film 18 and a 3 nm thick SiO ₂ film 19 are sequentially laminated. And a tungsten polycide film 54 having a thickness of 150 nm extends as a control gate on these.
The S-type NOR flash memory is also different from the above-described embodiment only in the gate structure, and thus the invention of the present application can be applied.

[0060]

According to the NOR type flash memory of the present invention, even though both the ground line and the bit line extend in the same direction along the semiconductor layer, these ground line and the bit line are formed in the semiconductor. Since the layers can be overlapped with each other, the area of the memory cell can be reduced and the degree of integration can be increased.

In the NOR flash memory of the second aspect, the impurity region electrically connecting the ground line or bit line under the semiconductor layer and the source or drain of the transistor can be easily formed. Easy to manufacture.

In the NOR type flash memory of the third aspect, the contact hole formed in self-alignment with the gate of the transistor can be miniaturized, so that the memory cell area can be further reduced and the integration degree can be improved. It can be further increased.

[Brief description of drawings]

FIG. 1 is a plan view of an embodiment of the present invention.

FIG. 2 is a side sectional view taken along a line II-II in FIG.

FIG. 3 is a side sectional view taken along a line III-III in FIG.

FIG. 4 is a side sectional view taken along a line IV-IV in FIG.

5 is a side sectional view taken along the line VV in FIG.

6A and 6B show a first step for manufacturing one example, FIG. 6A is a plan view, and FIG. 6B is a side sectional view taken along a line BB in FIG. 6A.

FIG. 7 is a side sectional view sequentially showing a step following FIG.

FIG. 8 shows a step following FIG. 7B, in which FIG. 8A is a plan view, and FIGS. 8B and 8C are views taken along the line BB and the line CC in FIG. 8A, respectively. It is a sectional side view.

FIG. 9 shows a step that follows FIG. 8, in which (a) is a plan view, and (b) and (c) are respectively BB line and C- line of (a).
It is a sectional side view in the position which follows the C line.

FIG. 10 is a side cross-sectional view including an end portion of a memory cell portion at a time point of FIG. 9 (c).

FIG. 11 is a side sectional view showing a step that follows FIGS.

FIG. 12 is a side sectional view sequentially showing a step following FIG.

FIG. 13 is a side sectional view sequentially showing a step following FIG. 12 (b).

FIG. 14 shows a step that follows FIG.
(A) is a plan view, (b) and (c) are B- of (a), respectively.
It is a sectional side view in the position which follows a B line and a CC line.

15 shows a step following FIG. 14, in which (a) is a plan view, (b) and (c) are BB lines and C of (a), respectively.
It is a sectional side view in the position which follows the -C line.

16 shows a step following FIG. 15, in which (a) is a plan view, (b) and (c) are BB lines and C of (a), respectively.
It is a sectional side view in the position which follows the -C line.

FIG. 17 shows a step that follows FIG. 16, in which (a) is a plan view, and (b), (c) and (d) are BB of (a), respectively.
It is a side sectional view in the position which meets a line, a CC line, and a DD line.

FIG. 18 shows a step that follows FIG. 17, in which (a) is a plan view, and (b), (c), (d), and (e) are B of (a), respectively.
It is a sectional side view in the position which follows the -B line, the CC line, the DD line, and the EE line.

FIG. 19 shows a step following FIG. 18, in which (a) is a plan view, (b) and (c) are BB lines and C of (a), respectively.
It is a sectional side view in the position which follows the -C line.

FIG. 20 is a side sectional view of an essential part in another embodiment of the present invention.

21A and 21B are side cross-sectional views for explaining a method of extracting electrons to the drain in the floating gate type, where FIG. 21A shows the injection of electrons and FIG. 21B shows the extraction of electrons.

22A and 22B are side sectional views for explaining a method of extracting electrons to a substrate to which the invention of the present application can be applied in a floating gate type, in which FIG. 22A is a diagram showing electron injection and FIG. 22B is a diagram showing electron extraction. Shows.

23A and 23B are side sectional views for explaining a method of extracting electrons to a substrate to which the invention of the present application can be applied in the MONOS type, where FIG. 23A is a diagram showing electron injection and FIG. 23B is a diagram showing electron extraction. ing.

FIG. 24 is an equivalent circuit diagram of a first conventional example of the present invention.

FIG. 25 is a plan view of a first conventional example.

FIG. 26 is an equivalent circuit diagram of a second conventional example and one embodiment of the present invention.

FIG. 27 is a plan view of a second conventional example.

[Explanation of symbols]

14 Source 15 Drain 16 Transistor 18 Si ₃ N ₄ Film 19 SiO ₂ Film 36 SiO ₂ Film 38 Tungsten Polycide Film 44 Si Layer 52 Polycrystalline Si Film 54 Tungsten Polycide Film 55 SiO ₂ Film 56 SiO ₂ Film 57 Photoresist 57a Opening 61 Contact hole 62 Contact hole 63 Phosphorus 64 Impurity region 67 SiO ₂ film 71 Ti / TiN / Ti film 72 AlSiCu film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G11C 16/06 G11C 17/00 309C

Claims (5)

[Claims] 1. A source of a transistor for a memory cell,
A semiconductor layer in which a drain and a channel region are formed extends in a strip shape, and a ground line and a bit line extend along the semiconductor layer through an insulating film in one and the other of the upper and lower layers of the semiconductor layer. A NOR flash memory that is present and in which the ground line and the bit line are electrically connected to the source or the drain. 2. The semiconductor layer is formed of impurities of the same conductivity type as the source or the drain introduced into the semiconductor layer through a contact hole formed in self-alignment with the gate of the transistor. 2. The NOR flash memory according to claim 1, wherein the ground line or the bit line of the lower layer is electrically connected to the source or the drain by an impurity region penetrating therethrough. 3. Self-alignment with respect to the gate by etching the insulating film covering the gate and the semiconductor layer using a mask layer having an opening extending in a strip shape in a direction intersecting with the gate of the transistor. 3. The NOR flash memory according to claim 1, wherein a typical contact hole is formed. 4. The charge is stored in the floating gate.
4. The NOR flash memory according to any one of 3 to 3. 5. The NOR flash memory according to claim 1, wherein charges are accumulated in a trap of an insulating film.